From: Kuogee Hsieh <quic_khsieh@quicinc.com>
To: Stephen Boyd <swboyd@chromium.org>, <agross@kernel.org>,
<airlied@linux.ie>, <bjorn.andersson@linaro.org>,
<daniel@ffwll.ch>, <dianders@chromium.org>,
<dmitry.baryshkov@linaro.org>, <robdclark@gmail.com>,
<sean@poorly.run>, <vkoul@kernel.org>
Cc: <quic_abhinavk@quicinc.com>, <quic_aravindh@quicinc.com>,
<quic_sbillaka@quicinc.com>, <freedreno@lists.freedesktop.org>,
<dri-devel@lists.freedesktop.org>,
<linux-arm-msm@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] drm/msm/dp: Always clear mask bits to disable interrupts at dp_ctrl_reset_irq_ctrl()
Date: Mon, 9 May 2022 14:56:18 -0700 [thread overview]
Message-ID: <0276a7f8-538f-a601-cdb5-46e3ad636e8f@quicinc.com> (raw)
In-Reply-To: <CAE-0n52HvhT_RFbJHhijKCCt8jQM70fo6ceAbnYEfOfO-dRxVA@mail.gmail.com>
On 5/6/2022 5:29 PM, Stephen Boyd wrote:
> Quoting Kuogee Hsieh (2022-05-06 14:41:07)
>> dp_catalog_ctrl_reset() will software reset DP controller. But it will
>> not reset programmable registers to default value. DP driver still have
>> to clear mask bits to interrupt status registers to disable interrupts
>> after software reset of controller. This patch removes the enable flag
>> condition checking to always clear mask bits of interrupt status
>> registers to disable interrupts if enable flag is false.
> Another paragraph is needed which is that this (partially?) fixes the
> suspend path where we call dp_catalog_ctrl_reset() but the irq is still
> unmasked and can come in while we're suspending. This leads to bus hangs
> if the irq is handled after we power down the DP hardware because we run
> the irq handler and access a device register assuming that no irq could
> ever come in if we powered down the device. We don't know when the irq
> will be handled though, so it's possible the irq is pending from before
> we disable the irq in the hardware. Don't we need some irq synchronize
> to make sure it doesn't run?
Since irqs are converted into events and executed in event thread
context, as long as no irq disabled then event q will be emptied
accordingly.
Also, i think synchronize_irq() have higher risk of deadlocking if
resources are hold by others.
>> Fixes: ba0a422be723 ("drm/msm/dp: do not initialize phy until plugin interrupt received")
>> Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
>> ---
>> drivers/gpu/drm/msm/dp/dp_ctrl.c | 9 +++++++--
>> 1 file changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
>> index 38026f2..cbf3399 100644
>> --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
>> +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
>> @@ -1379,8 +1379,13 @@ void dp_ctrl_reset_irq_ctrl(struct dp_ctrl *dp_ctrl, bool enable)
>>
>> dp_catalog_ctrl_reset(ctrl->catalog);
>>
>> - if (enable)
>> - dp_catalog_ctrl_enable_irq(ctrl->catalog, enable);
>> + /*
>> + * all dp controller programmable registers will not
>> + * be reset to default value after DP_SW_RESET
>> + * therefore interrupt mask bits have to be updated
>> + * to enable/disable interrupts
>> + */
>> + dp_catalog_ctrl_enable_irq(ctrl->catalog, enable);
>> }
>>
>> void dp_ctrl_phy_init(struct dp_ctrl *dp_ctrl)
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
>> a Linux Foundation Collaborative Project
>>
prev parent reply other threads:[~2022-05-09 21:56 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-06 21:41 [PATCH] drm/msm/dp: Always clear mask bits to disable interrupts at dp_ctrl_reset_irq_ctrl() Kuogee Hsieh
2022-05-07 0:29 ` Stephen Boyd
2022-05-09 21:56 ` Kuogee Hsieh [this message]
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