From: "Yang, Fei" <fei.yang@intel.com>
To: David Cohen <david.a.cohen@linux.intel.com>,
"tglx@linutronix.de" <tglx@linutronix.de>,
"mingo@redhat.com" <mingo@redhat.com>,
"hpa@zytor.com" <hpa@zytor.com>,
"x86@kernel.org" <x86@kernel.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"Brown, Mark F" <mark.f.brown@intel.com>,
Kuppuswamy Sathyanarayanan
<sathyanarayanan.kuppuswamy@linux.intel.com>
Subject: RE: [PATCH] x86: intel-mid: add Merrifield platform support
Date: Wed, 23 Oct 2013 00:49:41 +0000 [thread overview]
Message-ID: <02E7334B1630744CBDC55DA85862258348EDC9B0@ORSMSX102.amr.corp.intel.com> (raw)
In-Reply-To: <1382484820-5912-1-git-send-email-david.a.cohen@linux.intel.com>
+ if (intel_mid_identify_cpu() ==
+ INTEL_MID_CPU_CHIP_TANGIER) {
+ if (!strncmp(pentry->name,
+ "r69001-ts-i2c", 13))
+ /* active low */
+ irq_attr.polarity = 1;
+ else if (!strncmp(pentry->name,
+ "synaptics_3202", 14))
+ /* active low */
+ irq_attr.polarity = 1;
+ else if (irq == 41)
+ /* fast_int_1 */
+ irq_attr.polarity = 1;
Do you really want to upstream these very hardware specific hacks? It's needed for
Saltbay, but might not be correct for other Merrifield based hardware, if any.
-Fei
next prev parent reply other threads:[~2013-10-23 0:49 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-10-18 21:18 [PATCH 0/3] Add maintainers + Clovertrail support to Intel Mid David Cohen
2013-10-18 21:18 ` [PATCH 1/3] MAINTAINERS: INTEL MID SOC: add maintainers David Cohen
2013-10-18 21:21 ` Joe Perches
2013-10-18 21:30 ` David Cohen
2013-10-18 21:34 ` [PATCH v1.1 " David Cohen
2013-10-18 21:18 ` [PATCH 2/3] x86: intel-mid: move Medfield code out of intel-mid.c core file David Cohen
2013-10-18 21:18 ` [PATCH 3/3] x86: intel-mid: add Clovertrail platform support David Cohen
2013-10-22 23:33 ` [PATCH] x86: intel-mid: add Merrifield " David Cohen
2013-10-23 0:49 ` Yang, Fei [this message]
2013-10-23 2:49 ` David Cohen
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