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[82.131.98.15]) by smtp.gmail.com with ESMTPSA id x25-20020a056512131900b00492c59a4bccsm413248lfu.206.2022.08.25.03.18.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 Aug 2022 03:18:14 -0700 (PDT) Message-ID: <0454105e-38f5-ea8f-0c1f-1d1fd835ea6c@linaro.org> Date: Thu, 25 Aug 2022 13:18:13 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.13.0 Subject: Re: [PATCH v2] dt-bindings: arm: mediatek: mmsys: change compatible for MT8195 Content-Language: en-US To: Bo-Chen Chen , robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com Cc: jason-jh.lin@mediatek.com, nancy.lin@mediatek.com, ck.hu@mediatek.com, chunkuang.hu@kernel.org, angelogioacchino.delregno@collabora.com, hsinyi@google.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Project_Global_Chrome_Upstream_Group@mediatek.com References: <20220825091448.14008-1-rex-bc.chen@mediatek.com> From: Krzysztof Kozlowski In-Reply-To: <20220825091448.14008-1-rex-bc.chen@mediatek.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 25/08/2022 12:14, Bo-Chen Chen wrote: > From: "Jason-JH.Lin" > > For previous MediaTek SoCs, such as MT8173, there are 2 display HW > pipelines binding to 1 mmsys with the same power domain, the same > clock driver and the same mediatek-drm driver. > > For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to > 2 different power domains, different clock drivers and different > mediatek-drm drivers. > > Moreover, Hardware pipeline of VDOSYS0 has these components: COLOR, > CCORR, AAL, GAMMA, DITHER. They are related to the PQ (Picture Quality) > and they makes VDOSYS0 supports PQ function while they are not > including in VDOSYS1. > > Hardware pipeline of VDOSYS1 has the component ETHDR (HDR related > component). It makes VDOSYS1 supports the HDR function while it's not > including in VDOSYS0. > > To summarize0: > Only VDOSYS0 can support PQ adjustment. > Only VDOSYS1 can support HDR adjustment. > > Therefore, we need to separate these two different mmsys hardwares to > 2 different compatibles for MT8195. > > Fixes: 81c5a41d10b9 ("dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding") > Signed-off-by: Jason-JH.Lin > Signed-off-by: Bo-Chen Chen > --- Acked-by: Krzysztof Kozlowski Best regards, Krzysztof