From: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
To: Jianjun Wang <jianjun.wang@mediatek.com>,
Chunfeng Yun <chunfeng.yun@mediatek.com>,
Kishon Vijay Abraham I <kishon@ti.com>,
Vinod Koul <vkoul@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
linux-phy@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, rex-bc.chen@mediatek.com,
randy.wu@mediatek.com, jieyy.yang@mediatek.com,
chuanjia.liu@mediatek.com, qizhong.cheng@mediatek.com,
jian.yang@mediatek.com
Subject: Re: [PATCH 2/2] dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY
Date: Fri, 11 Mar 2022 15:28:28 +0100 [thread overview]
Message-ID: <0454647b-7aa3-ed70-0b92-1e5c98d0adc0@canonical.com> (raw)
In-Reply-To: <20220311133527.5914-3-jianjun.wang@mediatek.com>
On 11/03/2022 14:35, Jianjun Wang wrote:
> Add YAML schema documentation for PCIe PHY on MediaTek chipsets.
>
> Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
> ---
> .../bindings/phy/mediatek,pcie-phy.yaml | 71 +++++++++++++++++++
> 1 file changed, 71 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
> new file mode 100644
> index 000000000000..da15b4bf3117
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml
> @@ -0,0 +1,71 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek PCIe PHY Device Tree Binding
Title is for hardware, so s/Device Tree Binding//
> +
> +maintainers:
> + - Jianjun Wang <jianjun.wang@mediatek.com>
> +
> +description: |
> + The PCIe PHY supports physical layer functionality for PCIe Gen3 port.
> +
> +properties:
> + compatible:
> + const: mediatek,pcie-phy
Is it going to be exactly one pcie-phy for all Mediatek chipsets for
next years? Are you sure about that? It sounds highly unlikely....
> +
> + reg:
> + maxItems: 1
> +
> + reg-names:
> + items:
> + - const: sif
> +
> + "#phy-cells":
> + const: 0
> +
> + nvmem-cells:
> + maxItems: 7
> + description:
> + Phandles to nvmem cell that contains the efuse data, if unspecified,
> + default value is used.
> +
> + nvmem-cell-names:
> + items:
> + - const: glb_intr
> + - const: tx_ln0_pmos
> + - const: tx_ln0_nmos
> + - const: rx_ln0
> + - const: tx_ln1_pmos
> + - const: tx_ln1_nmos
> + - const: rx_ln1
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - "#phy-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + pciephy: phy@11e80000 {
> + compatible = "mediatek,pcie-phy";
> + #phy-cells = <0>;
> + reg = <0x11e80000 0x10000>;
> + reg-names = "sif";
> + nvmem-cells = <&pciephy_glb_intr>,
> + <&pciephy_tx_ln0_pmos>,
> + <&pciephy_tx_ln0_nmos>,
> + <&pciephy_rx_ln0>,
> + <&pciephy_tx_ln1_pmos>,
> + <&pciephy_tx_ln1_nmos>,
> + <&pciephy_rx_ln1>;
> + nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
> + "tx_ln0_nmos", "rx_ln0",
> + "tx_ln1_pmos", "tx_ln1_nmos",
> + "rx_ln1";
> + };
Best regards,
Krzysztof
next prev parent reply other threads:[~2022-03-11 14:28 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-11 13:35 [PATCH 0/2] phy: mediatek: Add PCIe PHY driver Jianjun Wang
2022-03-11 13:35 ` [PATCH 1/2] " Jianjun Wang
2022-03-17 7:49 ` Chen-Yu Tsai
2022-03-17 9:34 ` Jianjun Wang
2022-03-11 13:35 ` [PATCH 2/2] dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY Jianjun Wang
2022-03-11 14:28 ` Krzysztof Kozlowski [this message]
2022-03-14 1:42 ` Jianjun Wang
2022-03-15 3:15 ` Chunfeng Yun
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