From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00B98C433EF for ; Tue, 5 Jul 2022 03:54:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233178AbiGEDyN (ORCPT ); Mon, 4 Jul 2022 23:54:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35678 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234484AbiGEDxx (ORCPT ); Mon, 4 Jul 2022 23:53:53 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D0E4713CCC; Mon, 4 Jul 2022 20:53:51 -0700 (PDT) X-UUID: f5b855bd032b430f98d58c6e765c4837-20220705 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8,REQID:4ad43b80-c143-4025-a870-2a6f13e35daf,OB:30,L OB:20,IP:0,URL:5,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,A CTION:release,TS:50 X-CID-INFO: VERSION:1.1.8,REQID:4ad43b80-c143-4025-a870-2a6f13e35daf,OB:30,LOB :20,IP:0,URL:5,TC:0,Content:0,EDM:0,RT:0,SF:45,FILE:0,RULE:Release_Ham,ACT ION:release,TS:50 X-CID-META: VersionHash:0f94e32,CLOUDID:d34a6b63-0b3f-4b2c-b3a6-ed5c044366a0,C OID:34be4a092cbd,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,QS:nil,BEC:nil,COL:0 X-UUID: f5b855bd032b430f98d58c6e765c4837-20220705 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1889993485; Tue, 05 Jul 2022 11:53:46 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 5 Jul 2022 11:53:44 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Tue, 5 Jul 2022 11:53:44 +0800 Message-ID: <04e3ec85fdb4be1456f0cca3b7493439047c059f.camel@mediatek.com> Subject: Re: [PATCH v15 10/16] drm/mediatek: dpi: move swap_shift to SoC config From: CK Hu To: Bo-Chen Chen , , , , , , , CC: , , , , , , , , , , , , Date: Tue, 5 Jul 2022 11:53:44 +0800 In-Reply-To: <20220701035845.16458-11-rex-bc.chen@mediatek.com> References: <20220701035845.16458-1-rex-bc.chen@mediatek.com> <20220701035845.16458-11-rex-bc.chen@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Bo-Chen: On Fri, 2022-07-01 at 11:58 +0800, Bo-Chen Chen wrote: > From: Guillaume Ranquet > > Add flexibility by moving the swap shift value to SoC specific > config. Applied to mediatek-drm-next [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next Regards, CK > > Signed-off-by: Guillaume Ranquet > Signed-off-by: Bo-Chen Chen > Reviewed-by: Rex-BC Chen > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > Reviewed-by: CK Hu > --- > drivers/gpu/drm/mediatek/mtk_dpi.c | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c > b/drivers/gpu/drm/mediatek/mtk_dpi.c > index 11724432e2f2..70a83a3c0570 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dpi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c > @@ -125,6 +125,7 @@ struct mtk_dpi_yc_limit { > * @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and > VSYNC_PORCH > * (no shift). > * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift). > + * @channel_swap_shift: Shift value of channel swap. > */ > struct mtk_dpi_conf { > unsigned int (*cal_factor)(int clock); > @@ -137,6 +138,7 @@ struct mtk_dpi_conf { > bool swap_input_support; > u32 dimension_mask; > u32 hvsize_mask; > + u32 channel_swap_shift; > }; > > static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, > u32 mask) > @@ -367,7 +369,9 @@ static void mtk_dpi_config_channel_swap(struct > mtk_dpi *dpi, > break; > } > > - mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << CH_SWAP, > CH_SWAP_MASK); > + mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, > + val << dpi->conf->channel_swap_shift, > + CH_SWAP_MASK << dpi->conf->channel_swap_shift); > } > > static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool > enable) > @@ -817,6 +821,7 @@ static const struct mtk_dpi_conf mt8173_conf = { > .swap_input_support = true, > .dimension_mask = HPW_MASK, > .hvsize_mask = HSIZE_MASK, > + .channel_swap_shift = CH_SWAP, > }; > > static const struct mtk_dpi_conf mt2701_conf = { > @@ -830,6 +835,7 @@ static const struct mtk_dpi_conf mt2701_conf = { > .swap_input_support = true, > .dimension_mask = HPW_MASK, > .hvsize_mask = HSIZE_MASK, > + .channel_swap_shift = CH_SWAP, > }; > > static const struct mtk_dpi_conf mt8183_conf = { > @@ -842,6 +848,7 @@ static const struct mtk_dpi_conf mt8183_conf = { > .swap_input_support = true, > .dimension_mask = HPW_MASK, > .hvsize_mask = HSIZE_MASK, > + .channel_swap_shift = CH_SWAP, > }; > > static const struct mtk_dpi_conf mt8192_conf = { > @@ -854,6 +861,7 @@ static const struct mtk_dpi_conf mt8192_conf = { > .swap_input_support = true, > .dimension_mask = HPW_MASK, > .hvsize_mask = HSIZE_MASK, > + .channel_swap_shift = CH_SWAP, > }; > > static int mtk_dpi_probe(struct platform_device *pdev)