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Subject: Re: [PATCH 10/13] MIPS: mscc: add ocelot dtsi
To: Alexandre Belloni <alexandre.belloni@free-electrons.com>,
        Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org
References: <20171128152643.20463-1-alexandre.belloni@free-electrons.com>
 <20171128152643.20463-11-alexandre.belloni@free-electrons.com>
From: Florian Fainelli <f.fainelli@gmail.com>
Message-ID: <0596b316-f3a3-6d06-75f4-acad4fde3b5f@gmail.com>
Date: Tue, 28 Nov 2017 10:40:31 -0800
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On 11/28/2017 07:26 AM, Alexandre Belloni wrote:
> Add a device tree include file for the Microsemi Ocelot SoC.
> 
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---

> +	ahb {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;

You could provide the base address and size of the bus range, such that
your nodes all become relative to that base address, e.g:

		ranges = <0 0x70000000 0x10000>;

What a strange physical address to place registers on a MIPS system
though...

> +
> +		interrupt-parent = <&intc>;
> +
> +		cpu_ctrl: syscon@70000000 {
> +			compatible = "syscon";
> +			reg = <0x70000000 0x2c>;
> +		};

Then this becomes:

		syscon@0 {
			compatible = "syscon";
			reg = <0x0 0x2c>;
		};

etc.

> +
> +		intc: interrupt-controller@70000070 {
> +			compatible = "mscc,ocelot-icpu-intr";
> +			reg = <0x70000070 0x70>;
> +			#interrupt-cells = <1>;
> +			interrupt-controller;
> +			interrupt-parent = <&cpuintc>;
> +			interrupts = <2>;
> +		};
> +
> +		uart0: serial@70100000 {
> +			pinctrl-0 = <&uart_pins>;
> +			pinctrl-names = "default";
> +			compatible = "ns16550a";
> +			reg = <0x70100000 0x20>;
> +			interrupts = <6>;
> +			clocks = <&ahb_clk>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +
> +			status = "disabled";
> +		};
> +
> +		uart2: serial@70100800 {
> +			pinctrl-0 = <&uart2_pins>;
> +			pinctrl-names = "default";
> +			compatible = "ns16550a";
> +			reg = <0x70100800 0x20>;
> +			interrupts = <7>;
> +			clocks = <&ahb_clk>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +
> +			status = "disabled";
> +		};
> +
> +		chip_regs: syscon@71070000 {
> +			compatible = "simple-mfd", "syscon";
> +			reg = <0x71070000 0x1c>;
> +
> +			reset {
> +				compatible = "mscc,ocelot-chip-reset";
> +				mscc,cpucontrol = <&cpu_ctrl>;
> +			};
> +		};
> +
> +		gpio: pinctrl@71070034 {
> +			compatible = "mscc,ocelot-pinctrl";
> +			reg = <0x71070034 0x28>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&gpio 0 0 22>;
> +
> +			uart_pins: uart-pins {
> +				pins = "GPIO_6", "GPIO_7";
> +				function = "uart";
> +			};
> +
> +			uart2_pins: uart2-pins {
> +				pins = "GPIO_12", "GPIO_13";
> +				function = "uart2";
> +			};
> +		};
> +	};
> +};
> 


-- 
Florian