From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935239AbdAEGl5 (ORCPT ); Thu, 5 Jan 2017 01:41:57 -0500 Received: from mailout3.samsung.com ([203.254.224.33]:36128 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751386AbdAEGTT (ORCPT ); Thu, 5 Jan 2017 01:19:19 -0500 X-AuditID: b6c32a18-f79056d00000397d-80-586de562fa33 Subject: Re: [PATCH V2 3/5] Documetation: binding: modify the exynos5440 pcie binding To: Jaehoon Chung , linux-pci@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com, kgene@kernel.org, krzk@kernel.org, kishon@ti.com, jingoohan1@gmail.com, vivek.gautam@codeaurora.org, alim.akhtar@samsung.com, cpgs@samsung.com From: "pankaj.dubey" Message-id: <059c5912-8078-0191-f677-e85a3b3d91ce@samsung.com> Date: Thu, 05 Jan 2017 11:51:58 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-version: 1.0 In-reply-to: <20170104123435.30740-4-jh80.chung@samsung.com> Content-type: text/plain; charset=windows-1252 Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrAJsWRmVeSWpSXmKPExsWy7bCmsG7S09wIgzfP5CwezNvGZrGkKcPi 5SFNi/lHzrFa3PjVxmqx4stMdov+x6+ZLS487WGzOH9+A7vF5V1z2CzOzjvOZjHj/D4mi6XX LzJZtO49wm5x4ucOZgd+jzXz1jB6XO7rZfLYOesuu8eCTaUem1Z1snn0bVnF6HH8xnYmj8+b 5AI4olJtMlITU1KLFFLzkvNTMvPSbZW8g+Od403NDAx1DS0tzJUU8hJzU22VXHwCdN0yc4BO V1IoS8wpBQoFJBYXK+nb2RTll5akKmTkF5fYKkUbGhrpGRqY6xkZGemZGMVaGZkClSSkZrQ+ Kypokai4eOkYUwPjOuEuRk4OCQETiWUflrNB2GISF+6tB7K5OIQEljFKdPyaxgThfGaU6F5y gAmmo6nlNAtEYiujxI6ve8HahQXCJU7tfAeU4OAQEXCVmL4oAqSGWWAbk8SsQ12sIDVsAvoS 0x9vA6vnFbCTaG+fzwJiswioSDy+0M4IYosKREgcOnabGaJGUOLkzCdgNZwCNhKLDi0CizML GEgcWTSHFcKWl9j+dg4zyDIJgZfsEj+f9zOBHCEhICux6QAzxNEuElO2z2eEsIUlXh3fwg5h S0k03T7FAtHbzCjRsHUKlDODUWLBzslQL9tLHLgyhwViG5/E4vUP2CAW8Ep0tAlBlHhIXJj+ hRUi7Chx4bggJIAOMkrcatjFPoFRbhaSf2Yh+WEWkh8WMDKvYhRPLSjOTU8tNi4wNNArTswt Ls1L10vOz93ECE6tWhI7GDes8DrEKMDBqMTDq2iRGyHEmlhWXJl7iFGCg1lJhLftEVCINyWx siq1KD++qDQntfgQoykwkCcyS4km5wPTfl5JvKGJmaGJkZmhoYmlkbmSOO/FausIIYH0xJLU 7NTUgtQimD4mDk6pBsaZ1Yd6DjSaRlys/HLtwHax8qM1sfHyds7dXULe82Xfvpi01Su2rU04 yCl7jiQzs53KHOk1dUrVwZEb9ulyLb/pJcV4qfvWixzD9JNzb5TeNa7ifOVYJ6p42fbJW5t+ No5TbtoP6neFXLqtfGX59MlXjjz4uM/ky8wwnfYKTku5/fM8sj9s+6DEUpyRaKjFXFScCACJ FrWlwwMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrJIsWRmVeSWpSXmKPExsWSnRNcq5v0NDfCYPJsQYsH87axWSxpyrB4 eUjTYv6Rc6wWN361sVqs+DKT3aL/8WtmiwtPe9gszp/fwG5xedccNouz846zWcw4v4/JYun1 i0wWrXuPsFuc+LmD2YHfY828NYwel/t6mTx2zrrL7rFgU6nHplWdbB59W1Yxehy/sZ3J4/Mm uQCOKDebjNTElNQihdS85PyUzLx0W6XQEDddCyWFvMTcVFulCF3fkCAlhbLEnFIgz8gADTg4 B7gHK+nbJbhltD4rKmiRqLh46RhTA+M64S5GTg4JAROJppbTLBC2mMSFe+vZuhi5OIQENjNK LLnzhREkISwQLrHmbStrFyMHh4iAq8T0RREQNQcZJSac7mIEcZgFtjFJzDr3gw2kgU1AX2L6 421gNq+AnUR7+3ywDSwCKhKPL7QzggwSFYiQaDicDlEiKHFy5hOwEk4BG4lFhxYxg9jMAnoS O67/YoWw5SW2v53DPIGRfxaSlllIymYhKVvAyLyKUSy1oDg3Pbe4wMBYrzgxt7g0L10vOT93 EyMwWrcdVpLYwbhghdchRgEORiUe3hUpuRFCrIllxZW5hxglOJiVRHjbHgGFeFMSK6tSi/Lj i0pzUosPMZoCfTGRWUo0OR+YSPJK4g1NTC0sLEwsjY2NLUyUxHljpz8LFxJITyxJzU5NLUgt gulj4uCUamDMdzF+upn7X9tetds/hZg2KDVahytr9vbm2Z5fJfTw1OtDE0P2h06YKPLXxEh4 8imr5OcfXyfrPMme09h7/++UR958575dKZ3NY2oROL1S/V9fcmf9N/fQiYxZMfdPHPBQcrIJ f5j95IFlqsmkh/+fBJ+pn7mkrnT1xi/fFP4rVy36WpLiohGqxFKckWioxVxUnAgAvytEJ+wC AAA= X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170105061914epcas3p4c750360deb0c78c68d1b1693bfff2af5 X-Msg-Generator: CA X-Sender-IP: 182.195.34.24 X-Local-Sender: =?UTF-8?B?7YyQ7Lm07KaIG1NTSVItVHVybiBLZXkgU29sdXRpb25zGw==?= =?UTF-8?B?7IK87ISx7KCE7J6QGy4vQ2hpZWYgRW5naW5lZXI=?= X-Global-Sender: =?UTF-8?B?UEFOS0FKIEtVTUFSIERVQkVZG1NTSVItVHVybiBLZXkgU29s?= =?UTF-8?B?dXRpb25zG1NhbXN1bmcgRWxlY3Ryb25pY3MbLi9DaGllZiBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG1NXQUhRG0MxMElEMDdJRDAxMDk5Nw==?= CMS-TYPE: 103P DLP-Filter: Pass X-CFilter-Loop: Reflected X-HopCount: 7 X-CMS-RootMailID: 20170104123436epcas1p1040f1e074748fabe58af52eb0b833713 X-RootMTR: 20170104123436epcas1p1040f1e074748fabe58af52eb0b833713 References: <20170104123435.30740-1-jh80.chung@samsung.com> <20170104123435.30740-4-jh80.chung@samsung.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jaehoon, On Wednesday 04 January 2017 06:04 PM, Jaehoon Chung wrote: > According to using PHY framework, updates the exynos5440-pcie binding. > For maintaining backward compatibility, leaves the current dt-binding. > (It should be deprecated.) > > Recommends to use the Phy Framework and "config" property to follow > the designware-pcie binding. > If you use the old way, can see "mssing *config* reg space" message. > Because the getting configuration space address from range is old way. > > NOTE: When use the "config" property, first name of 'reg-names' must be > set to "elbi". Otherwise driver can't maintain the backward capability. > > Signed-off-by: Jaehoon Chung > --- > Changelog on V2: > - Describes more commit message > - Fixes the typos > - Adds the new example for using PHY framework > - Deprecated the old dt-binding description > - Removes 'phy-names' > > .../bindings/pci/samsung,exynos5440-pcie.txt | 29 ++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt > index 4f9d23d..1d0af0e 100644 > --- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt > @@ -7,8 +7,19 @@ Required properties: > - compatible: "samsung,exynos5440-pcie" > - reg: base addresses and lengths of the pcie controller, > the phy controller, additional register for the phy controller. > + (Registers for the phy controller are DEPRECATED. > + Use the PHY framework.) > +- reg-names : First name should be set to "elbi". > + And use the "config" instead of getting the confgiruation address space > + from "ranges". > + NOTE: When use the "config" property, reg-names must be set. > - interrupts: A list of interrupt outputs for level interrupt, > pulse interrupt, special interrupt. > +- phys: From PHY binding. Phandle for the Generic PHY. > + Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt > + > +Other common properties refer to > + Documentation/devicetree/binding/pci/designware-pcie.txt > > Example: > > @@ -54,6 +65,24 @@ SoC specific DT Entry: > num-lanes = <4>; > }; > > +With using PHY framework: > + pcie_phy0: pcie-phy@270000 { > + ... > + reg = <0x270000 0x1000>, <0x271000 0x40>; > + regn-names = "phy", "block"; typo: %s/regn-names/reg-names/ > + ... > + }; > + > + pcie@290000 { > + ... > + reg = <0x290000 0x1000>, <0x40000000 0x1000>; > + reg-names = "elbi", "config"; > + phys = <&pcie_phy0>; > + ranges = <0x81000000 0 0 0x60001000 0 0x00010000 > + 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; > + ... > + }; > + > Board specific DT Entry: > > pcie@290000 { > Other than above one typo rest is looking fine. Once you address it, feel free to add Reviewed-by: Pankaj Dubey Thanks, Pankaj Dubey