From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: ACJfBovq+loQsSH9d2u/ME/rBzVGrT6GJjVpSviatujZiDYlTgdNTdDkql8aFbiyFsuRjyptDrU7 ARC-Seal: i=1; a=rsa-sha256; t=1516270455; cv=none; d=google.com; s=arc-20160816; b=SL0ModKOYAw843wHaWjSuyvlXEOZ3W/UAwU+rWQx1pY4wK4gaojQ767b/5zQiGs8wA A7hOirApT3MsKVpRx4T4QrfIte1eAvu8wHcpKvnSAqLmZx6R+Fnp9rZ5yXgC9273dHgx wcgJJFiGJTfCo+VMf7SPC5Bs3894Ncf8CUVvraTgUwb2xXkAWB53cZjqCZLMYmXgguBn pOb6DPElvhpRRtwvRXxDdCFj+yEO/cETae1A/w/Teu6tl/GXadN+Giq3RlS+ieuBs3z2 Znq/ykuV+2yhW85TVDz1xGZIVZcNLkf8DdG4EQhKhqEBvmLilBP8mXmYMP1U/5kilxoj AWOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:content-language:in-reply-to:mime-version :user-agent:date:message-id:organization:from:references:to:subject :cc:arc-authentication-results; bh=ZQqY3WkHwBtPTAJMM3THpa2ZiD3oVHSkyW4LGO3jC8k=; b=dWK3NNvaEHqzqkXGjLrXykDsthqyZjRB1KdN7Y17spEN8HG1ELGOCpdUJEx8XM9jSV f5q0ShRa3ztgK0wQT5YnMuCxJHZ5IGAmUZ4VnGmio+xgRfDLDvbYzYF7OkUbOWbBdaZe ouonzYZFNdvpLw+R/SZLQU6k74ZORtnMsfRHq06DEPg05VuP/qSyhyt5/uX4KT++J/nx p9LxURtYPUi3LHKwis8X4hxjxDnBTSF8VyIH6ZpFko3bOHHhpw+mltj+w7+rU0mjW0pB pBjTf7YMeBIR9AA8sCafXW93GzKIIAOqe6uiAt6wKBC/k/niI0l1t6hIkG9vZu6B3oIM QNLw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of sudeep.holla@arm.com designates 217.140.101.70 as permitted sender) smtp.mailfrom=sudeep.holla@arm.com Authentication-Results: mx.google.com; spf=pass (google.com: domain of sudeep.holla@arm.com designates 217.140.101.70 as permitted sender) smtp.mailfrom=sudeep.holla@arm.com Cc: Sudeep Holla , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, hanjun.guo@linaro.org, lorenzo.pieralisi@arm.com, rjw@rjwysocki.net, will.deacon@arm.com, catalin.marinas@arm.com, gregkh@linuxfoundation.org, viresh.kumar@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, jhugo@codeaurora.org, wangxiongfeng2@huawei.com, Jonathan.Zhang@cavium.com, ahs3@redhat.com, Jayachandran.Nair@cavium.com, austinwc@codeaurora.org, lenb@kernel.org, vkilari@codeaurora.org, morten.rasmussen@arm.com, Palmer Dabbelt , Albert Ou Subject: Re: [PATCH v6 02/12] drivers: base: cacheinfo: setup DT cache properties early To: Jeremy Linton References: <20180113005920.28658-1-jeremy.linton@arm.com> <20180113005920.28658-3-jeremy.linton@arm.com> <20180115123338.GB5473@e107155-lin> <65f78c99-8b86-0098-7ced-899840a4bf16@arm.com> <15884ccc-2cfb-da91-5844-369d8237175d@arm.com> From: Sudeep Holla Organization: ARM Message-ID: <05a8b375-70c4-34d4-6cde-8dd4cd62c10b@arm.com> Date: Thu, 18 Jan 2018 10:14:06 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 In-Reply-To: <15884ccc-2cfb-da91-5844-369d8237175d@arm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1589436997037379564?= X-GMAIL-MSGID: =?utf-8?q?1589924808534170530?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: On 17/01/18 18:51, Jeremy Linton wrote: > Hi, > > On 01/17/2018 12:20 PM, Sudeep Holla wrote: >> >> >> On 16/01/18 21:07, Jeremy Linton wrote: >>> Hi, >>> >>> On 01/15/2018 06:33 AM, Sudeep Holla wrote: >>>> On Fri, Jan 12, 2018 at 06:59:10PM -0600, Jeremy Linton wrote: >>>>> The original intent in cacheinfo was that an architecture >>>>> specific populate_cache_leaves() would probe the hardware >>>>> and then cache_shared_cpu_map_setup() and >>>>> cache_override_properties() would provide firmware help to >>>>> extend/expand upon what was probed. Arm64 was really >>>>> the only architecture that was working this way, and >>>>> with the removal of most of the hardware probing logic it >>>>> became clear that it was possible to simplify the logic a bit. >>>>> >>>>> This patch combines the walk of the DT nodes with the >>>>> code updating the cache size/line_size and nr_sets. >>>>> cache_override_properties() (which was DT specific) is >>>>> then removed. The result is that cacheinfo.of_node is >>>>> no longer used as a temporary place to hold DT references >>>>> for future calls that update cache properties. That change >>>>> helps to clarify its one remaining use (matching >>>>> cacheinfo nodes that represent shared caches) which >>>>> will be used by the ACPI/PPTT code in the following patches. >>>>> >>>>> Cc: Palmer Dabbelt >>>>> Cc: Albert Ou >>>>> Signed-off-by: Jeremy Linton >>>>> --- >>>>>    arch/riscv/kernel/cacheinfo.c |  1 + >>>>>    drivers/base/cacheinfo.c      | 65 >>>>> +++++++++++++++++++------------------------ >>>>>    include/linux/cacheinfo.h     |  1 + >>>>>    3 files changed, 31 insertions(+), 36 deletions(-) >>>>> >>>>> diff --git a/arch/riscv/kernel/cacheinfo.c >>>>> b/arch/riscv/kernel/cacheinfo.c >>>>> index 10ed2749e246..6f4500233cf8 100644 >>>>> --- a/arch/riscv/kernel/cacheinfo.c >>>>> +++ b/arch/riscv/kernel/cacheinfo.c >>>>> @@ -30,6 +30,7 @@ static void ci_leaf_init(struct cacheinfo >>>>> *this_leaf, >>>>>            CACHE_WRITE_BACK >>>>>            | CACHE_READ_ALLOCATE >>>>>            | CACHE_WRITE_ALLOCATE; >>>>> +    cache_of_set_props(this_leaf, node); >>>> >>>> This may be necessary but can it be done as later patch ? So far >>>> nothing >>>> is added that may break riscv IIUC. >>> >>> Well I think you have a bisection issue where the additional information >>> will disappear between this patch and wherever we put this code back in. >>> >> >> Hmm, I am sorry but I fail to see the issue. Before this change, >> populate_cache_leaves just populated the info as per ci_leaf_init in >> arch/riscv/kernel/cacheinfo.c and cache_override_properties used to fill >> the remaining. >> >> After this patch, the same is achieved in cache_shared_cpu_map_setup. >> >> In both case, it was by the end of detect_cache_attributes, so I see no >> issue. >> > > > Hi, > > I must be misunderstanding something. > Looks like I was missing to understand something :) > AFAIK, The code in cache_setup_of_node() won't call cache_of_set_props() > because it returns when there is an existing of_node (fw_unique) created > by the riscv populate_cache_leaves(). That's why I'm making the direct > call here. If we fail to get that change in place before > cache_override_properties() is removed then the fields not set by the > riscv code (size/etc) will be missing. Indeed. I am trying to avoid use of cache_of_set_props outside. How about skipping setting up of fw_unique in ci_leaf_init instead ? -- Regards, Sudeep