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([2001:b07:6468:f312:1032:7ea1:7f8f:1e5]) by smtp.gmail.com with ESMTPSA id l9sm2821110wme.45.2019.10.09.14.15.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 09 Oct 2019 14:15:08 -0700 (PDT) Subject: Re: [PATCH AUTOSEL 5.3 28/68] KVM: x86: Expose XSAVEERPTR to the guest To: Sasha Levin , linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Sebastian Andrzej Siewior , kvm@vger.kernel.org References: <20191009170547.32204-1-sashal@kernel.org> <20191009170547.32204-28-sashal@kernel.org> From: Paolo Bonzini Openpgp: preference=signencrypt Message-ID: <05acd554-dd0a-d7cd-e17c-90627fa0ec67@redhat.com> Date: Wed, 9 Oct 2019 23:15:07 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20191009170547.32204-28-sashal@kernel.org> Content-Language: en-US X-MC-Unique: N3CRLTcIMICC9Ka9iLLLsg-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 09/10/19 19:05, Sasha Levin wrote: > From: Sebastian Andrzej Siewior >=20 > [ Upstream commit 504ce1954fba888936c9d13ccc1e3db9b8f613d5 ] >=20 > I was surprised to see that the guest reported `fxsave_leak' while the > host did not. After digging deeper I noticed that the bits are simply > masked out during enumeration. >=20 > The XSAVEERPTR feature is actually a bug fix on AMD which means the > kernel can disable a workaround. >=20 > Pass XSAVEERPTR to the guest if available on the host. >=20 > Signed-off-by: Sebastian Andrzej Siewior > Signed-off-by: Paolo Bonzini > Signed-off-by: Sasha Levin > --- > arch/x86/kvm/cpuid.c | 1 + > 1 file changed, 1 insertion(+) >=20 > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c > index fd1b8db8bf242..59b66e343fa5a 100644 > --- a/arch/x86/kvm/cpuid.c > +++ b/arch/x86/kvm/cpuid.c > @@ -479,6 +479,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_en= try2 *entry, u32 function, > =20 > =09/* cpuid 0x80000008.ebx */ > =09const u32 kvm_cpuid_8000_0008_ebx_x86_features =3D > +=09=09F(XSAVEERPTR) | > =09=09F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSB= D) | > =09=09F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON); > =20 >=20 Yet another example of a patch that shouldn't be stable material (in this case it's fine, but there can certainly be cases where just adding a single flag depends on core kernel changes). Paolo