From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AC98C28EB4 for ; Thu, 6 Jun 2019 15:46:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0448E206BB for ; Thu, 6 Jun 2019 15:46:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729483AbfFFPqm (ORCPT ); Thu, 6 Jun 2019 11:46:42 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:49358 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729185AbfFFPqm (ORCPT ); Thu, 6 Jun 2019 11:46:42 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9DEC7A78; Thu, 6 Jun 2019 08:46:41 -0700 (PDT) Received: from [10.1.196.105] (eglon.cambridge.arm.com [10.1.196.105]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EA3693F690; Thu, 6 Jun 2019 08:46:37 -0700 (PDT) Subject: Re: [PATCH 5.2 v2 2/2] dt-binding: edac: add NPCM ECC documentation To: George Hung Cc: linux-edac , linux-kernel , benjaminfair@google.com, wak@google.com, Avi.Fishman@nuvoton.com, tomer.maimon@nuvoton.com, openbmc@lists.ozlabs.org, Joel Stanley , Tali Perry , Patrick Venture , Nancy Yuen , Rob Herring , Mark Rutland , Borislav Petkov , Mauro Carvalho Chehab , davem@davemloft.net, Greg Kroah-Hartman , Nicolas Ferre , paulmck@linux.ibm.com, devicetree@vger.kernel.org, Linus Walleij , Jonathan Cameron References: <20190605141253.38554-1-ghung.quanta@gmail.com> <20190605141253.38554-2-ghung.quanta@gmail.com> From: James Morse Message-ID: <066d3d9b-f65e-7689-a3a7-d995e26fcbf3@arm.com> Date: Thu, 6 Jun 2019 16:46:33 +0100 User-Agent: Mozilla/5.0 (X11; Linux aarch64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <20190605141253.38554-2-ghung.quanta@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi George, On 05/06/2019 15:12, George Hung wrote: > Add device tree documentation for Nuvoton BMC ECC (Nit: The DT folk prefer patches adding bindings to come first in the series, before the driver that uses them). > diff --git a/Documentation/devicetree/bindings/edac/npcm7xx-sdram-edac.txt b/Documentation/devicetree/bindings/edac/npcm7xx-sdram-edac.txt > new file mode 100644 > index 000000000000..dd4dac59a5bd > --- /dev/null > +++ b/Documentation/devicetree/bindings/edac/npcm7xx-sdram-edac.txt > @@ -0,0 +1,17 @@ > +Nuvoton NPCM7xx SoC EDAC device driver > + > +The Nuvoton NPCM7xx SoC supports DDR4 memory with/without ECC and the driver > +uses the EDAC framework to implement the ECC detection and corrtection. The commit message in the driver says this is a Cadence memory controller, can we describe what it is here, and give it an additional compatible? Thanks, James > +Required properties: > +- compatible: should be "nuvoton,npcm7xx-sdram-edac" > +- reg: Memory controller register set should be <0xf0824000 0x1000> > +- interrupts: should be MC interrupt #25 > +Example: > + > + mc: memory-controller@f0824000 { > + compatible = "nuvoton,npcm7xx-sdram-edac"; > + reg = <0xf0824000 0x1000>; > + interrupts = <0 25 4>; > + }; >