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[109.252.91.213]) by smtp.googlemail.com with ESMTPSA id x1-v6sm517639ljj.56.2018.09.25.10.29.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 25 Sep 2018 10:29:31 -0700 (PDT) Subject: Re: [PATCH v1 1/5] dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30 To: Rob Herring , Peter De Schrijver Cc: Thierry Reding , Jonathan Hunter , "Rafael J. Wysocki" , Viresh Kumar , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org References: <20180830194356.14059-1-digetx@gmail.com> <20180830194356.14059-2-digetx@gmail.com> <20180925165810.GA32430@bogus> From: Dmitry Osipenko Message-ID: <074a169d-294b-ad4b-ddbd-6db742278f2a@gmail.com> Date: Tue, 25 Sep 2018 20:29:24 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.0 MIME-Version: 1.0 In-Reply-To: <20180925165810.GA32430@bogus> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 9/25/18 7:58 PM, Rob Herring wrote: > On Thu, Aug 30, 2018 at 10:43:52PM +0300, Dmitry Osipenko wrote: >> Add device-tree binding that describes CPU frequency-scaling hardware >> found on NVIDIA Tegra20/30 SoC's. >> >> Signed-off-by: Dmitry Osipenko >> --- >> .../cpufreq/nvidia,tegra20-cpufreq.txt | 38 +++++++++++++++++++ >> 1 file changed, 38 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt >> >> diff --git a/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt >> new file mode 100644 >> index 000000000000..2c51f676e958 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt >> @@ -0,0 +1,38 @@ >> +Binding for NVIDIA Tegra20 CPUFreq >> +================================== >> + >> +Required properties: >> +- clocks: Must contain an entry for each entry in clock-names. >> + See ../clocks/clock-bindings.txt for details. >> +- clock-names: Must include the following entries: >> + - pll_x: main-parent for CPU clock, must be the first entry >> + - backup: intermediate-parent for CPU clock >> + - cpu: the CPU clock > > The Cortex A9 has CLK, PERIPHCLK, and PERIPHCLKEN clocks and only CLK > is used for the cpu core. You can't just define your own clocks that > you happen to want access to. > > Otherwise, you're not defining anything new here, so a binding document > isn't required. PERIPHCLK is a different thing. Here we are defining the CPU clock and its *parent* sources, the PLLX (main) and backup (intermediate clock that is used while PLLX changes its rate). These are not some random clocks "that you happen to want access to", they are essential for the Tegra CPUFreq driver, CPU is running off them. I assume that PERIPHCLK and other clocks are derived from the "CPU" clock and their configuration is hardwired. Probably Peter knows how it's implemented in HW. I'm now working on v2 that will include more Tegra-specific stuff in the binding, like custom "opp-supported-hw" property and probably some more.