Re: [PATCH V3 2/6] perf/core: Add helper to obtain performance counter index

[Reinette Chatre <reinette.chatre@intel.com>]

Hi Peter,

On 9/17/2018 4:07 PM, Peter Zijlstra wrote:
> On Mon, Sep 17, 2018 at 09:37:14AM -0700, Reinette Chatre wrote:
>> On 9/17/2018 1:23 AM, Peter Zijlstra wrote:
> 
>>> I said arch/x86/include/asm/perf_events.h and call it:
>>> x86_perf_rdpmc_index().
>>>
>>> This function is very much x86 specific.
> 
>> Moving it to arch/x86/include/asm/perf_event.h is not trivial since this
>> file is not familiar with struct perf_event.
> 
> Urgh, right you are. Does it work if you make it a regular function
> instead of an inline? Put the thing in arch/x86/events/core.c or so and
> only an extern decl in asm/perf_event.h.

It works, but checkpatch.pl does not like it very much:
> CHECK: extern prototypes should be avoided in .h files
> #66: FILE: arch/x86/include/asm/perf_event.h:273:
> +extern int x86_perf_rdpmc_index(struct perf_event *event);

Doing this also prevents the availability of a x86_perf_rdpmc_index()
for when !CONFIG_PERF_EVENTS. I do not know if this is of big concern
since CONFIG_PERF_EVENTS is automatically selected by CONFIG_X86 ... but
at the same time there are other function definitions in
arch/x86/include/asm/perf_event.h for when !CONFIG_PERF_EVENTS.

Considering the above, would you like me to continue with the move to
arch/x86/events/core.c? Here is what I understood your suggestion to mean:

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index dfb2f7c0d019..3550d800b030 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -1033,6 +1033,27 @@ static inline void x86_assign_hw_event(struct
perf_event *event,
        }
 }

+/**
+ * x86_perf_rdpmc_index - Return PMC counter used for event
+ * @event: the perf_event to which the PMC counter was assigned
+ *
+ * The counter assigned to this performance event may change if interrupts
+ * are enabled. This counter should thus never be used while interrupts are
+ * enabled. Before this function is used to obtain the assigned counter the
+ * event should be checked for validity using, for example,
+ * perf_event_read_local(), within the same interrupt disabled section in
+ * which this counter is planned to be used.
+ *
+ * Return: The index of the performance monitoring counter assigned to
+ * @perf_event.
+ */
+int x86_perf_rdpmc_index(struct perf_event *event)
+{
+       lockdep_assert_irqs_disabled();
+
+       return event->hw.event_base_rdpmc;
+}
+
 static inline int match_prev_assignment(struct hw_perf_event *hwc,
                                        struct cpu_hw_events *cpuc,
                                        int i)
diff --git a/arch/x86/include/asm/perf_event.h
b/arch/x86/include/asm/perf_event.h
index 12f54082f4c8..b2cf84c35a6d 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -270,6 +270,7 @@ struct perf_guest_switch_msr {
 extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr);
 extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);
 extern void perf_check_microcode(void);
+extern int x86_perf_rdpmc_index(struct perf_event *event);
 #else
 static inline struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
 {

Thank you

Reinette