From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 024C5C3F68F for ; Mon, 10 Feb 2020 16:32:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DA7782080C for ; Mon, 10 Feb 2020 16:32:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727986AbgBJQcn (ORCPT ); Mon, 10 Feb 2020 11:32:43 -0500 Received: from mga14.intel.com ([192.55.52.115]:63530 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727640AbgBJQcm (ORCPT ); Mon, 10 Feb 2020 11:32:42 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Feb 2020 08:32:42 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,425,1574150400"; d="scan'208";a="312795470" Received: from jerjavec-mobl.amr.corp.intel.com (HELO arch-ashland-svkelley) ([10.251.129.77]) by orsmga001.jf.intel.com with ESMTP; 10 Feb 2020 08:32:39 -0800 Message-ID: <088c8f9d07fe4a36125b2f0e5aeb09defb5b5e13.camel@linux.intel.com> Subject: Re: RE: Re: "oneshot" interrupt causes another interrupt to be fired erroneously in Haswell system From: Sean V Kelley Reply-To: sean.v.kelley@linux.intel.com To: Thomas Gleixner , Kar Hin Ong , Bjorn Helgaas Cc: linux-rt-users , LKML , "x86@kernel.org" , "linux-pci@vger.kernel.org" , "H. Peter Anvin" , Dave Hansen , Julia Cartwright , Keng Soon Cheah , Gratian Crisan , Peter Zijlstra Date: Mon, 10 Feb 2020 08:32:39 -0800 In-Reply-To: <8736bjlqkg.fsf@nanos.tec.linutronix.de> References: <20191031230532.GA170712@google.com> <87a76oxqv1.fsf@nanos.tec.linutronix.de> <87muanwwhb.fsf@nanos.tec.linutronix.de> <8f1e5981b519acb5edf53b5392c81ef7cbf6a3eb.camel@linux.intel.com> <87muaetj4p.fsf@nanos.tec.linutronix.de> <8736bjlqkg.fsf@nanos.tec.linutronix.de> Organization: Intel Corporation Content-Type: text/plain; charset="UTF-8" User-Agent: Evolution 3.34.3 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, 2020-02-09 at 16:37 +0100, Thomas Gleixner wrote: > Sean, > > Thomas Gleixner writes: > > Sean V Kelley writes: > > > So I will ensure we actually create useful information pointing > > > to this > > > behavior either in kernel docs or online as in a white paper or > > > both. > > > > Great. > > > > > > As we have already quirks in drivers/pci/quirks.c which handle > > > > the > > > > same issue on older chipsets, we really should add one for > > > > these kind > > > > of systems to avoid fiddling with the BIOS (which you can, but > > > > most > > > > people cannot). > > > Agreed, and I will follow-up with Kar Hin Ong to get them added. > > > > Much appreciated. > > Any update on this? Hi Thomas, I've been working with Kar Hin in attempting to follow a similar pattern to the earlier PCI quirks done with ESB / ESB2 chipsets. However, the optional INTX routing table which was a part of the original quirk done about 10 years ago changed by the time these Haswell PCH arrived. The later PCH aligned with the BIOS switch becoming available and the deprecation of the bypass routing. We're testing a few more things, and I hope to have a conclusion this week. Thanks, Sean > > Thanks, > > tglx