From: Atish Patra <Atish.Patra@wdc.com>
To: "daniel.lezcano@linaro.org" <daniel.lezcano@linaro.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"palmer@sifive.com" <palmer@sifive.com>
Cc: "linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
Anup Patel <Anup.Patel@wdc.com>,
"gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>,
"info@metux.net" <info@metux.net>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"mark.rutland@arm.com" <mark.rutland@arm.com>,
"aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
"allison@lohutok.net" <allison@lohutok.net>,
"johan@kernel.org" <johan@kernel.org>,
"alexios.zavras@intel.com" <alexios.zavras@intel.com>,
"tglx@linutronix.de" <tglx@linutronix.de>,
"paul.walmsley@sifive.com" <paul.walmsley@sifive.com>,
"robh+dt@kernel.org" <robh+dt@kernel.org>
Subject: Re: [PATCH v2 1/5] RISC-V: Remove per cpu clocksource
Date: Fri, 16 Aug 2019 18:55:14 +0000 [thread overview]
Message-ID: <089a5ee46759074af391c50f5e9d28344b429de4.camel@wdc.com> (raw)
In-Reply-To: <6ba37c45-2d9b-c01e-5f17-3ab919da4de8@linaro.org>
On Fri, 2019-08-16 at 17:09 +0200, Daniel Lezcano wrote:
> On 31/07/2019 03:24, Atish Patra wrote:
> > There is only one clocksource in RISC-V. The boot cpu initializes
> > that clocksource. No need to keep a percpu data structure.
>
> That is not what is stated in the initial patch [1].
>
> Can you clarify that ?
>
I think what I meant to say was "There is only one clocksource used in
RISC-V Linux" as it is guranteed that all the timers across all the
harts are synchronized within one tick of each other [2].
Apologies for not being verbose here.
However, reading the privilege specification(1.12-draft)
Section. 3.1.10 states that
"Accurate real-time clocks (RTCs) are relatively expensive to provide
(requiring a crystal or MEMS oscillator) and have to run even when the
rest of system is powered down, and so there is usually only one in a
system located in a different frequency/voltage domain from the
processors. Hence, the RTC must be shared by all the harts in a system"
This is different from the commit text in [1].
Perhaps I misunderstood something. @Palmer ?
[2]
https://elixir.bootlin.com/linux/v5.3-rc4/source/drivers/clocksource/timer-riscv.c#L44
> Thanks
>
> -- Daniel
>
> [1] https://lkml.org/lkml/2018/8/4/51
>
>
> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > ---
> > drivers/clocksource/timer-riscv.c | 6 ++----
> > 1 file changed, 2 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/clocksource/timer-riscv.c
> > b/drivers/clocksource/timer-riscv.c
> > index 5e6038fbf115..09e031176bc6 100644
> > --- a/drivers/clocksource/timer-riscv.c
> > +++ b/drivers/clocksource/timer-riscv.c
> > @@ -55,7 +55,7 @@ static u64 riscv_sched_clock(void)
> > return get_cycles64();
> > }
> >
> > -static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = {
> > +static struct clocksource riscv_clocksource = {
> > .name = "riscv_clocksource",
> > .rating = 300,
> > .mask = CLOCKSOURCE_MASK(64),
> > @@ -92,7 +92,6 @@ void riscv_timer_interrupt(void)
> > static int __init riscv_timer_init_dt(struct device_node *n)
> > {
> > int cpuid, hartid, error;
> > - struct clocksource *cs;
> >
> > hartid = riscv_of_processor_hartid(n);
> > if (hartid < 0) {
> > @@ -112,8 +111,7 @@ static int __init riscv_timer_init_dt(struct
> > device_node *n)
> >
> > pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n",
> > __func__, cpuid, hartid);
> > - cs = per_cpu_ptr(&riscv_clocksource, cpuid);
> > - error = clocksource_register_hz(cs, riscv_timebase);
> > + error = clocksource_register_hz(&riscv_clocksource,
> > riscv_timebase);
> > if (error) {
> > pr_err("RISCV timer register failed [%d] for cpu =
> > [%d]\n",
> > error, cpuid);
> >
>
>
next prev parent reply other threads:[~2019-08-16 18:55 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-31 1:24 [PATCH v2 0/5] Miscellaneous fixes Atish Patra
2019-07-31 1:24 ` [PATCH v2 1/5] RISC-V: Remove per cpu clocksource Atish Patra
2019-08-16 15:09 ` Daniel Lezcano
2019-08-16 18:55 ` Atish Patra [this message]
2019-08-26 23:48 ` Palmer Dabbelt
2019-07-31 1:24 ` [PATCH v2 2/5] RISC-V: Add riscv_isa reprensenting ISA features common across CPUs Atish Patra
2019-07-31 4:23 ` Paul Walmsley
2019-07-31 6:27 ` Atish Patra
2019-07-31 1:24 ` [PATCH v2 3/5] RISC-V: Fix unsupported isa string info Atish Patra
2019-07-31 1:24 ` [PATCH v2 4/5] RISC-V: Export few kernel symbols Atish Patra
2019-07-31 1:24 ` [PATCH v2 5/5] dt-bindings: Update the isa string description Atish Patra
2019-07-31 4:52 ` Paul Walmsley
2019-07-31 6:43 ` Atish Patra
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