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Fri, 25 Mar 2022 08:47:38 -0700 (PDT) Received: from [192.168.1.145] ([207.188.167.132]) by smtp.gmail.com with ESMTPSA id r4-20020a05600c35c400b0038cbd8c41e9sm7504769wmq.12.2022.03.25.08.47.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 25 Mar 2022 08:47:37 -0700 (PDT) Message-ID: <09b8c4d2-6cdd-b41b-4913-f9f2f7f4d7c7@gmail.com> Date: Fri, 25 Mar 2022 16:47:36 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Content-Language: en-US To: Allen-KH Cheng , Rob Herring , Krzysztof Kozlowski , Chun-Kuang Hu Cc: Project_Global_Chrome_Upstream_Group@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Chen-Yu Tsai , Ryder Lee , Hui Liu References: <20220318144534.17996-1-allen-kh.cheng@mediatek.com> <20220318144534.17996-19-allen-kh.cheng@mediatek.com> From: Matthias Brugger Subject: Re: [PATCH v4 18/22] arm64: dts: mt8192: Add display nodes In-Reply-To: <20220318144534.17996-19-allen-kh.cheng@mediatek.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 18/03/2022 15:45, Allen-KH Cheng wrote: > Add display nodes for mt8192 SoC. > > Signed-off-by: Allen-KH Cheng > Reviewed-by: AngeloGioacchino Del Regno > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111 +++++++++++++++++++++++ > 1 file changed, 111 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index a77d405dd508..59183fb6c80b 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -1205,6 +1205,13 @@ > #clock-cells = <1>; > }; > > + mutex: mutex@14001000 { > + compatible = "mediatek,mt8192-disp-mutex"; > + reg = <0 0x14001000 0 0x1000>; > + interrupts = ; > + clocks = <&mmsys CLK_MM_DISP_MUTEX0>; We are missing power-domains property. > + }; > + > smi_common: smi@14002000 { > compatible = "mediatek,mt8192-smi-common"; > reg = <0 0x14002000 0 0x1000>; > @@ -1236,6 +1243,110 @@ > power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > }; > > + ovl0: ovl@14005000 { > + compatible = "mediatek,mt8192-disp-ovl"; > + reg = <0 0x14005000 0 0x1000>; > + interrupts = ; > + clocks = <&mmsys CLK_MM_DISP_OVL0>; > + iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, > + <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + }; > + > + ovl_2l0: ovl@14006000 { > + compatible = "mediatek,mt8192-disp-ovl-2l"; > + reg = <0 0x14006000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; > + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, > + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; olv and ovl-2l binding mention that the node should be a sibling of mmsys, but this does not hold anymore, correct? Chun-Kuang can you help to fix the binding description? > + }; > + > + rdma0: rdma@14007000 { > + compatible = "mediatek,mt8192-disp-rdma"; > + reg = <0 0x14007000 0 0x1000>; > + interrupts = ; > + clocks = <&mmsys CLK_MM_DISP_RDMA0>; > + iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; > + mediatek,larb = <&larb0>; > + mediatek,rdma-fifo-size = <5120>; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; Same here, bindings says it should be a sibling of mmsys. Apart from that the maximal rdma-fifo-size isn't specified for all SoCs including mt1892. > + }; > + > + color0: color@14009000 { > + compatible = "mediatek,mt8192-disp-color", > + "mediatek,mt8173-disp-color"; > + reg = <0 0x14009000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_COLOR0>; > + }; Same here, binding description needs fixed, please check for other bindings as well. The node here looks good. > + > + ccorr0: ccorr@1400a000 { > + compatible = "mediatek,mt8192-disp-ccorr"; > + reg = <0 0x1400a000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_CCORR0>; > + }; > + > + aal0: aal@1400b000 { > + compatible = "mediatek,mt8192-disp-aal", > + "mediatek,mt8193-disp-aal"; > + reg = <0 0x1400b000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_AAL0>; > + }; > + > + gamma0: gamma@1400c000 { > + compatible = "mediatek,mt8192-disp-gamma", > + "mediatek,mt8183-disp-gamma"; > + reg = <0 0x1400c000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_GAMMA0>; > + }; > + > + postmask0: postmask@1400d000 { > + compatible = "mediatek,mt8192-disp-postmask"; > + reg = <0 0x1400d000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_POSTMASK0>; > + iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>; No iommus mentioned in binding description. Regards, Matthias > + }; > + > + dither0: dither@1400e000 { > + compatible = "mediatek,mt8192-disp-dither", > + "mediatek,mt8183-disp-dither"; > + reg = <0 0x1400e000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_DITHER0>; > + }; > + > + ovl_2l2: ovl@14014000 { > + compatible = "mediatek,mt8192-disp-ovl-2l"; > + reg = <0 0x14014000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_OVL2_2L>; > + iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, > + <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; > + }; > + > + rdma4: rdma@14015000 { > + compatible = "mediatek,mt8192-disp-rdma"; > + reg = <0 0x14015000 0 0x1000>; > + interrupts = ; > + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_DISP_RDMA4>; > + iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>; > + mediatek,rdma-fifo-size = <2048>; > + }; > + > dpi0: dpi@14016000 { > compatible = "mediatek,mt8192-dpi"; > reg = <0 0x14016000 0 0x1000>;