From: Tudor Ambarus <tudor.ambarus@linaro.org>
To: Conor Dooley <conor@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>,
broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org,
semen.protsenko@linaro.org, krzysztof.kozlowski@linaro.org,
alim.akhtar@samsung.com, linux-spi@vger.kernel.org,
linux-samsung-soc@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, andre.draszik@linaro.org,
peter.griffin@linaro.org, kernel-team@android.com,
willmcvicker@google.com, conor+dt@kernel.org,
devicetree@vger.kernel.org, arnd@arndb.de
Subject: Re: [PATCH 01/12] spi: dt-bindings: introduce the ``fifo-depth`` property
Date: Fri, 9 Feb 2024 16:55:43 +0000 [thread overview]
Message-ID: <0ac8d573-6486-458d-afb9-090b5f8d4a21@linaro.org> (raw)
In-Reply-To: <20240209-chest-sleet-a119fc3d4243@spud>
On 2/9/24 16:21, Conor Dooley wrote:
> On Fri, Feb 09, 2024 at 01:56:56PM +0000, Tudor Ambarus wrote:
>>
>> + Geert
>>
>> On 2/8/24 18:24, Conor Dooley wrote:
>>> On Thu, Feb 08, 2024 at 01:50:34PM +0000, Tudor Ambarus wrote:
>>>> There are instances of the same IP that are configured by the integrator
>>>> with different FIFO depths. Introduce the fifo-depth property to allow
>>>> such nodes to specify their FIFO depth.
>>>>
>>>> We haven't seen SPI IPs with different FIFO depths for RX and TX, thus
>>>> introduce a single property.
>>>
>>> Some citation attached to this would be nice. "We haven't seen" offers
>>> no detail as to what IPs that allow this sort of configuration of FIFO
>>> size that you have actually checked.
>>>
>>> I went and checked our IP that we use in FPGA fabric, which has a
>>> configurable fifo depth. It only has a single knob for both RX and TX
>>> FIFOs. The Xilinx xps spi core also has configurable FIFOs, but again RX
>>> and TX sizes are tied there. At least that's a sample size of three.
>>>
>>> One of our guys is working on support for the IP I just mentioned and
>>> would be defining a vendor property for this, so
>>> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>>>
>>
>> Thanks, Conor. I had in mind that SPI has a shift register and it's
>> improbable to have different FIFO depths for RX and TX.
>
> IDK, but I've learned to expect the unexpectable, especially when it
> comes to the IPs intended for use in FPGAs.
>
>> At least I don't
>> see how it would work, I guess it will use the minimum depth between the
>> two?
>
> I'm not really sure how it would work other than that in the general
> case, but some use case specific configuration could work, but I do
> agree that it is
>
>> I grepped by "fifo" in the spi bindings and I now see that renesas is
>> using dedicated properties for RX and TX, but I think that there too the
>> FIFOs have the same depths. Looking into drivers/spi/spi-sh-msiof.c I
>> see that the of_device_id.data contains 64 bytes FIFOs for RX and TX,
>> regardless of the compatible.
>>
>> Geert, any idea if the FIFO depths can differ for RX and TX in
>> spi-sh-msiof.c?
>>
>> Anyway, even if there are such imbalanced architectures, I guess we can
>> consider them when/if they appear? (add rx/tx-fifo-depth dt properties)
>
> I think so.
>
>> Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml:
>> Override the default TX fifo size. Unit is words. Ignored if 0.
>> Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml:
>> renesas,rx-fifo-size:
>> Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml:
>> Override the default RX fifo size. Unit is words. Ignored if 0.
>
> These renesas ones seemed interesting at first glance due to these
> comments, but what's missed by grep the is "deprecated" marking on
> these. They seem to have been replaced by soc-specific compatibles.
In the driver the renesas,{rx,tx}-fifo-size properties still have the
highest priority:
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git/tree/drivers/spi/spi-sh-msiof.c#n1350
Maybe something for Geert, as I see he was the one marking these
properties as deprecated. I guess he forgot to update the driver.
Anyway, I think we shall be fine, even if we don't hear from Geert.
Cheers,
ta
next prev parent reply other threads:[~2024-02-09 16:55 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-08 13:50 [PATCH 00/12] spi: s3c64xx: remove OF alias ID dependency Tudor Ambarus
2024-02-08 13:50 ` [PATCH 01/12] spi: dt-bindings: introduce the ``fifo-depth`` property Tudor Ambarus
2024-02-08 18:24 ` Conor Dooley
2024-02-09 13:56 ` Tudor Ambarus
2024-02-09 16:21 ` Conor Dooley
2024-02-09 16:55 ` Tudor Ambarus [this message]
2024-02-12 10:38 ` Geert Uytterhoeven
2024-02-12 12:01 ` Tudor Ambarus
2024-02-09 17:41 ` Mark Brown
2024-02-09 17:13 ` Geert Uytterhoeven
2024-02-11 13:49 ` Krzysztof Kozlowski
2024-02-12 6:17 ` Tudor Ambarus
2024-02-08 13:50 ` [PATCH 02/12] spi: s3c64xx: define a magic value Tudor Ambarus
2024-02-08 13:50 ` [PATCH 03/12] spi: s3c64xx: allow full FIFO masks Tudor Ambarus
2024-02-08 13:50 ` [PATCH 04/12] spi: s3c64xx: determine the fifo depth only once Tudor Ambarus
2024-02-08 13:50 ` [PATCH 05/12] spi: s3c64xx: retrieve the FIFO depth from the device tree Tudor Ambarus
2024-02-08 13:50 ` [PATCH 06/12] spi: s3c64xx: allow FIFO depth to be determined from the compatible Tudor Ambarus
2024-02-08 13:50 ` [PATCH 07/12] spi: s3c64xx: let the SPI core determine the bus number Tudor Ambarus
2024-02-08 13:50 ` [PATCH 08/12] spi: s3c64xx: introduce s3c64xx_spi_set_port_id() Tudor Ambarus
2024-02-08 13:50 ` [PATCH 09/12] spi: s3c64xx: get rid of the OF alias ID dependency Tudor Ambarus
2024-02-08 13:50 ` [PATCH 10/12] spi: s3c64xx: deprecate fifo_lvl_mask, rx_lvl_offset and port_id Tudor Ambarus
2024-02-08 13:50 ` [PATCH 11/12] spi: s3c64xx: switch gs101 to new port config data Tudor Ambarus
2024-02-08 16:01 ` Tudor Ambarus
2024-02-08 13:50 ` [PATCH 12/12] spi: s3c64xx: switch exynos850 " Tudor Ambarus
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=0ac8d573-6486-458d-afb9-090b5f8d4a21@linaro.org \
--to=tudor.ambarus@linaro.org \
--cc=alim.akhtar@samsung.com \
--cc=andi.shyti@kernel.org \
--cc=andre.draszik@linaro.org \
--cc=arnd@arndb.de \
--cc=broonie@kernel.org \
--cc=conor+dt@kernel.org \
--cc=conor@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=geert+renesas@glider.be \
--cc=kernel-team@android.com \
--cc=krzysztof.kozlowski@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-samsung-soc@vger.kernel.org \
--cc=linux-spi@vger.kernel.org \
--cc=peter.griffin@linaro.org \
--cc=robh@kernel.org \
--cc=semen.protsenko@linaro.org \
--cc=willmcvicker@google.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).