From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753387AbeCNGXl (ORCPT ); Wed, 14 Mar 2018 02:23:41 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:46276 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751436AbeCNGXi (ORCPT ); Wed, 14 Mar 2018 02:23:38 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C9215603AF Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=architt@codeaurora.org Subject: Re: [PATCH v5 17/36] drm/bridge: analogix_dp: Fix AUX_PD bit for Rockchip To: Enric Balletbo i Serra , inki.dae@samsung.com, thierry.reding@gmail.com, hjc@rock-chips.com, seanpaul@chromium.org, airlied@linux.ie, tfiga@chromium.org, heiko@sntech.de Cc: dri-devel@lists.freedesktop.org, dianders@chromium.org, a.hajda@samsung.com, ykk@rock-chips.com, kernel@collabora.com, m.szyprowski@samsung.com, linux-samsung-soc@vger.kernel.org, jy0922.shim@samsung.com, rydberg@bitmath.org, krzk@kernel.org, linux-rockchip@lists.infradead.org, kgene@kernel.org, linux-input@vger.kernel.org, orjan.eide@arm.com, wxt@rock-chips.com, jeffy.chen@rock-chips.com, linux-arm-kernel@lists.infradead.org, mark.yao@rock-chips.com, wzz@rock-chips.com, hl@rock-chips.com, jingoohan1@gmail.com, sw0312.kim@samsung.com, linux-kernel@vger.kernel.org, kyungmin.park@samsung.com, Laurent.pinchart@ideasonboard.com, kuankuan.y@gmail.com, hshi@chromium.org References: <20180309222327.18689-1-enric.balletbo@collabora.com> <20180309222327.18689-18-enric.balletbo@collabora.com> From: Archit Taneja Message-ID: <0b27e434-92fd-0033-9a45-a87170de2da1@codeaurora.org> Date: Wed, 14 Mar 2018 11:53:20 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <20180309222327.18689-18-enric.balletbo@collabora.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Saturday 10 March 2018 03:53 AM, Enric Balletbo i Serra wrote: > From: zain wang > > There are some different bits between Rockchip and Exynos in register > "AUX_PD". This patch fixes the incorrect operations about it. You mean the register ANALOGIX_DP_PHY_PD/ANALOGIX_DP_PD, right? AUX_PD sounds like just one of the fields of the register. With that, Reviewed-by: Archit Taneja Thanks, Archit > > Cc: Douglas Anderson > Signed-off-by: zain wang > Signed-off-by: Sean Paul > Signed-off-by: Thierry Escande > Reviewed-by: Andrzej Hajda > Signed-off-by: Enric Balletbo i Serra > Tested-by: Marek Szyprowski > --- > > drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 117 ++++++++++++---------- > drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 2 + > 2 files changed, 65 insertions(+), 54 deletions(-) > > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > index bb72f8b0e603..dee1ba109b5f 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > @@ -248,76 +248,85 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, > { > u32 reg; > u32 phy_pd_addr = ANALOGIX_DP_PHY_PD; > + u32 mask; > > if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) > phy_pd_addr = ANALOGIX_DP_PD; > > switch (block) { > case AUX_BLOCK: > - if (enable) { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg |= AUX_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } else { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg &= ~AUX_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } > + if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) > + mask = RK_AUX_PD; > + else > + mask = AUX_PD; > + > + reg = readl(dp->reg_base + phy_pd_addr); > + if (enable) > + reg |= mask; > + else > + reg &= ~mask; > + writel(reg, dp->reg_base + phy_pd_addr); > break; > case CH0_BLOCK: > - if (enable) { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg |= CH0_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } else { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg &= ~CH0_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } > + mask = CH0_PD; > + reg = readl(dp->reg_base + phy_pd_addr); > + > + if (enable) > + reg |= mask; > + else > + reg &= ~mask; > + writel(reg, dp->reg_base + phy_pd_addr); > break; > case CH1_BLOCK: > - if (enable) { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg |= CH1_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } else { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg &= ~CH1_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } > + mask = CH1_PD; > + reg = readl(dp->reg_base + phy_pd_addr); > + > + if (enable) > + reg |= mask; > + else > + reg &= ~mask; > + writel(reg, dp->reg_base + phy_pd_addr); > break; > case CH2_BLOCK: > - if (enable) { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg |= CH2_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } else { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg &= ~CH2_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } > + mask = CH2_PD; > + reg = readl(dp->reg_base + phy_pd_addr); > + > + if (enable) > + reg |= mask; > + else > + reg &= ~mask; > + writel(reg, dp->reg_base + phy_pd_addr); > break; > case CH3_BLOCK: > - if (enable) { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg |= CH3_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } else { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg &= ~CH3_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } > + mask = CH3_PD; > + reg = readl(dp->reg_base + phy_pd_addr); > + > + if (enable) > + reg |= mask; > + else > + reg &= ~mask; > + writel(reg, dp->reg_base + phy_pd_addr); > break; > case ANALOG_TOTAL: > - if (enable) { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg |= DP_PHY_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } else { > - reg = readl(dp->reg_base + phy_pd_addr); > - reg &= ~DP_PHY_PD; > - writel(reg, dp->reg_base + phy_pd_addr); > - } > + /* > + * There is no bit named DP_PHY_PD, so We used DP_INC_BG > + * to power off everything instead of DP_PHY_PD in > + * Rockchip > + */ > + if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) > + mask = DP_INC_BG; > + else > + mask = DP_PHY_PD; > + > + reg = readl(dp->reg_base + phy_pd_addr); > + if (enable) > + reg |= mask; > + else > + reg &= ~mask; > + > + writel(reg, dp->reg_base + phy_pd_addr); > + if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) > + usleep_range(10, 15); > break; > case POWER_ALL: > if (enable) { > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > index 9602668669f4..b633a4a5082a 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > @@ -345,7 +345,9 @@ > #define DP_INC_BG (0x1 << 7) > #define DP_EXP_BG (0x1 << 6) > #define DP_PHY_PD (0x1 << 5) > +#define RK_AUX_PD (0x1 << 5) > #define AUX_PD (0x1 << 4) > +#define RK_PLL_PD (0x1 << 4) > #define CH3_PD (0x1 << 3) > #define CH2_PD (0x1 << 2) > #define CH1_PD (0x1 << 1) >