From: Tony Luck <tony.luck@intel.com>
To: linux-kernel@vger.kernel.org
Cc: Ingo Molnar <mingo@elte.hu>, Borislav Petkov <bp@amd64.org>,
Chen Gong <gong.chen@linux.intel.com>,
"Huang, Ying" <ying.huang@intel.com>,
Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Subject: [PATCH 1/2] x86/mce: Move MCACOD defines from mce-severity.c to <asm/mce.h>
Date: Thu, 19 Jul 2012 11:21:53 -0700 [thread overview]
Message-ID: <0ccfb1af5fe35e537b7cd8e4d448bf7d851dbfb9.1342723082.git.tony.luck@intel.com> (raw)
In-Reply-To: <cover.1342723082.git.tony.luck@intel.com>
We will need some of these values in mce.c. Move them to the
appropriate header file so they are available.
Signed-off-by: Tony Luck <tony.luck@intel.com>
---
arch/x86/include/asm/mce.h | 8 ++++++++
arch/x86/kernel/cpu/mcheck/mce-severity.c | 7 -------
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 441520e..a3ac52b 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -33,6 +33,14 @@
#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
#define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
#define MCI_STATUS_AR (1ULL<<55) /* Action required */
+#define MCACOD 0xffff /* MCA Error Code */
+
+/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
+#define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
+#define MCACOD_SCRUBMSK 0xfff0
+#define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
+#define MCACOD_DATA 0x0134 /* Data Load */
+#define MCACOD_INSTR 0x0150 /* Instruction Fetch */
/* MCi_MISC register defines */
#define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f)
diff --git a/arch/x86/kernel/cpu/mcheck/mce-severity.c b/arch/x86/kernel/cpu/mcheck/mce-severity.c
index 413c2ce..1301762 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-severity.c
+++ b/arch/x86/kernel/cpu/mcheck/mce-severity.c
@@ -55,13 +55,6 @@ static struct severity {
#define MCI_UC_S (MCI_STATUS_UC|MCI_STATUS_S)
#define MCI_UC_SAR (MCI_STATUS_UC|MCI_STATUS_S|MCI_STATUS_AR)
#define MCI_ADDR (MCI_STATUS_ADDRV|MCI_STATUS_MISCV)
-#define MCACOD 0xffff
-/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
-#define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */
-#define MCACOD_SCRUBMSK 0xfff0
-#define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */
-#define MCACOD_DATA 0x0134 /* Data Load */
-#define MCACOD_INSTR 0x0150 /* Instruction Fetch */
MCESEV(
NO, "Invalid",
--
1.7.10.2.552.gaa3bb87
next prev parent reply other threads:[~2012-07-19 19:02 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-07-19 18:38 [PATCH 0/2] Fix machine check recovery for instruction fault on Sandy Bridge Tony Luck
2012-07-19 18:21 ` Tony Luck [this message]
2012-07-19 18:28 ` [PATCH 2/2] x86/mce: Add quirk for instruction recovery on Sandy Bridge processors Tony Luck
2012-07-20 12:18 ` Borislav Petkov
2012-07-20 16:33 ` Tony Luck
2012-07-21 12:45 ` Borislav Petkov
2012-07-23 16:11 ` Luck, Tony
2012-07-23 21:21 [PATCH 0/2] Fix machine check recovery for instruction fault on Sandy Bridge Tony Luck
2012-07-19 18:21 ` [PATCH 1/2] x86/mce: Move MCACOD defines from mce-severity.c to <asm/mce.h> Tony Luck
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