From: Ding Tianhong <dingtianhong@huawei.com>
To: Casey Leedom <leedom@chelsio.com>,
Alexander Duyck <alexander.duyck@gmail.com>
Cc: "ashok.raj@intel.com" <ashok.raj@intel.com>,
"helgaas@kernel.org" <helgaas@kernel.org>,
Michael Werner <werner@chelsio.com>,
Ganesh GR <ganeshgr@chelsio.com>,
"asit.k.mallick@intel.com" <asit.k.mallick@intel.com>,
"patrick.j.cramer@intel.com" <patrick.j.cramer@intel.com>,
"Suravee.Suthikulpanit@amd.com" <Suravee.Suthikulpanit@amd.com>,
"Bob.Shaw@amd.com" <Bob.Shaw@amd.com>,
"l.stach@pengutronix.de" <l.stach@pengutronix.de>,
"amira@mellanox.com" <amira@mellanox.com>,
"gabriele.paoloni@huawei.com" <gabriele.paoloni@huawei.com>,
"David.Laight@aculab.com" <David.Laight@aculab.com>,
"jeffrey.t.kirsher@intel.com" <jeffrey.t.kirsher@intel.com>,
"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
"will.deacon@arm.com" <will.deacon@arm.com>,
"mark.rutland@arm.com" <mark.rutland@arm.com>,
"robin.murphy@arm.com" <robin.murphy@arm.com>,
"davem@davemloft.net" <davem@davemloft.net>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v6 0/3] Add new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag
Date: Mon, 10 Jul 2017 18:49:02 +0800 [thread overview]
Message-ID: <0df11d6f-c9cb-3c6b-ba08-d5e5c45754ae@huawei.com> (raw)
In-Reply-To: <MWHPR12MB1600AECAE619EAA97E6B15D5C8AB0@MWHPR12MB1600.namprd12.prod.outlook.com>
Hi Casey:
On 2017/7/8 10:04, Casey Leedom wrote:
> Okay, thanks for the note Alexander. I'll have to look more closely at
> the patch on Monday and try it out on one of the targeted systems to verify
> the semantics you describe.
>
All the modification is only clearing the device's Device Control{Relaxed Ordering
Enable]bit when distinguish that the platform should not support RO and did nothing
to the RC configuration, so I don't think it will break anything compare to the
first version from yours.
> However, that said, there is no way to tell a priori where a device will
> send TLPs. To simply assume that all TLPs will be directed towards the Root
> Complex is a big assumption. Only the device and the code controlling it
> know where the TLPs will be directed. That's why there are changes required
> in the cxgb4 driver. For instance, the code in
> drivers/net/ethernet/chelsio./cxgb4/sge.c: t4_sge_alloc_rxq() knows that
> it's allocating Free List Buffers in Host Memory and that the RX Queues that
> it's allocating in the Hardware will eventually send Ingress Data to those
> Free List Buffers. (And similarly for the Free List Buffer Pointer Queue
> with respect to DMA Reads from the host.) In that routine we explicitly
> configure the Hardware to use/not-use the Relaxed Ordering Attribute via the
> FW_IQ_CMD_FL0FETCHRO and FW_IQ_CMD_FL0DATARO flags. Basically we're
> conditionally setting them based on the desirability of sending Relaxed
> Ordering TLPs to the Root Complex. (And we would perform the same kind of
> check for an nVME application ... which brings us to ...)
>
> And what would be the code using these patch APIs to set up a Peer-to-Peer
> nVME-style application? In that case we'd need the Chelsio adapter's PCIe
> Capability Device Control[Relaxed Ordering Enable] set for the nVME
> application ... and we would avoid programming the Chelsio Hardware to use
> Relaxed Ordering for TLPs directed at the Root Complex. Thus we would be in
> a position where some TLPs being emitted by the device to Peer devices would
> have Relaxed Ordering set and some directed at the Root Complex would not.
> And the only way for that to work is if the source device's Device
> Control[Relaxed Ordering Enable] is set ...
>
> Finally, setting aside my disagreements with the patch, we still have the
> code in the cxgb4 driver which explicitly turns on its own Device
> Control[Relaxed Ordering Enable] in cxgb4_main.c:
> enable_pcie_relaxed_ordering(). So the patch is something of a loop if all
> we're doing is testing our own Relaxed Ordering Enable state ...
>
> Casey
>
> .
>
prev parent reply other threads:[~2017-07-10 10:50 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-22 12:15 [PATCH v6 0/3] Add new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag Ding Tianhong
2017-06-22 12:15 ` [PATCH v6 1/3] PCI: Add new PCIe Fabric End Node flag, PCI_DEV_FLAGS_NO_RELAXED_ORDERING Ding Tianhong
2017-06-22 12:15 ` [PATCH v6 2/3] PCI: Enable PCIe Relaxed Ordering if supported Ding Tianhong
2017-06-22 12:15 ` [PATCH v6 3/3] net/cxgb4: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag Ding Tianhong
2017-06-29 5:47 ` [PATCH v6 0/3] Add " Ding Tianhong
2017-07-06 12:58 ` Ding Tianhong
2017-07-06 17:17 ` Bjorn Helgaas
2017-07-07 1:03 ` Ding Tianhong
2017-07-07 21:48 ` Casey Leedom
2017-07-08 0:30 ` Casey Leedom
2017-07-08 0:47 ` Alexander Duyck
2017-07-08 2:04 ` Casey Leedom
2017-07-08 3:37 ` Alexander Duyck
2017-07-11 0:01 ` Casey Leedom
2017-07-11 20:33 ` Alexander Duyck
2017-07-12 9:46 ` Ding Tianhong
2017-07-13 0:52 ` Casey Leedom
2017-07-13 1:18 ` Ding Tianhong
2017-07-13 2:28 ` Casey Leedom
2017-07-10 10:49 ` Ding Tianhong [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=0df11d6f-c9cb-3c6b-ba08-d5e5c45754ae@huawei.com \
--to=dingtianhong@huawei.com \
--cc=Bob.Shaw@amd.com \
--cc=David.Laight@aculab.com \
--cc=Suravee.Suthikulpanit@amd.com \
--cc=alexander.duyck@gmail.com \
--cc=amira@mellanox.com \
--cc=ashok.raj@intel.com \
--cc=asit.k.mallick@intel.com \
--cc=catalin.marinas@arm.com \
--cc=davem@davemloft.net \
--cc=gabriele.paoloni@huawei.com \
--cc=ganeshgr@chelsio.com \
--cc=helgaas@kernel.org \
--cc=jeffrey.t.kirsher@intel.com \
--cc=l.stach@pengutronix.de \
--cc=leedom@chelsio.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=netdev@vger.kernel.org \
--cc=patrick.j.cramer@intel.com \
--cc=robin.murphy@arm.com \
--cc=werner@chelsio.com \
--cc=will.deacon@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).