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client-ip=162.221.158.21; receiver=esa1.hc3370-68.iphmx.com; envelope-from="Andrew.Cooper3@citrix.com"; x-sender="postmaster@mail.citrix.com"; x-conformance=sidf_compatible IronPort-SDR: vf0TS8brxPg6yQ9/ypXeP+lUogYWU2PI36PXrTN20HLfvdTVmSgQ6lTpKaZEHUP91EIDdB4JgI 7oXWx40UocYS8MGhxSMDybWJsYu9Eoyop5SVkabn0kX1hxVP1Jdv79cBb9GPhcVn2inKQktu8z qWSOCaZSnRwugkR0HUrR/b6PpIPvu+NuN7xrEvaxZ0QKbchFa2wKh5hwdHoe1r15LbraHK6lnX 6MY9E69N0CNtOsKSr45Wv/5Ip1gjGVN7cZDq89dvZfDLRJLLQDp8o16VBBhElHKOKjbqg7N4US 3IU= X-SBRS: 2.7 X-MesageID: 2990353 X-Ironport-Server: esa1.hc3370-68.iphmx.com X-Remote-IP: 162.221.158.21 X-Policy: $RELAYED X-IronPort-AV: E=Sophos;i="5.63,493,1557201600"; d="scan'208";a="2990353" Subject: Re: [PATCH] x86/apic: Initialize TPR to block interrupts 16-31 To: Nadav Amit , Andy Lutomirski CC: LKML , "x86@kernel.org" , Borislav Petkov , Peter Zijlstra , Stephane Eranian , Feng Tang References: From: Andrew Cooper Openpgp: preference=signencrypt Autocrypt: addr=andrew.cooper3@citrix.com; prefer-encrypt=mutual; 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Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.2 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Content-Language: en-GB X-ClientProxiedBy: AMSPEX02CAS02.citrite.net (10.69.22.113) To AMSPEX02CL02.citrite.net (10.69.22.126) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 14/07/2019 18:21, Nadav Amit wrote: >> On Jul 14, 2019, at 8:23 AM, Andy Lutomirski wrote: >> >> The APIC, per spec, is fundamentally confused and thinks that >> interrupt vectors 16-31 are valid. This makes no sense -- the CPU >> reserves vectors 0-31 for exceptions (faults, traps, etc). >> Obviously, no device should actually produce an interrupt with >> vector 16-31, but we can improve robustness by setting the APIC TPR >> class to 1, which will prevent delivery of an interrupt with a >> vector below 32. >> >> Note: this is *not* intended as a security measure against attackers >> who control malicious hardware. Any PCI or similar hardware that >> can be controlled by an attacker MUST be behind a functional IOMMU >> that remaps interrupts. The purpose of this patch is to reduce the >> chance that a certain class of device malfunctions crashes the >> kernel in hard-to-debug ways. >> >> Cc: Nadav Amit >> Cc: Stephane Eranian >> Cc: Feng Tang >> Suggested-by: Andrew Cooper >> Signed-off-by: Andy Lutomirski >> --- >> arch/x86/kernel/apic/apic.c | 7 +++++-- >> 1 file changed, 5 insertions(+), 2 deletions(-) >> >> diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c >> index 177aa8ef2afa..ff31322f8839 100644 >> --- a/arch/x86/kernel/apic/apic.c >> +++ b/arch/x86/kernel/apic/apic.c >> @@ -1531,11 +1531,14 @@ static void setup_local_APIC(void) >> #endif >> >> /* >> - * Set Task Priority to 'accept all'. We never change this >> - * later on. >> + * Set Task Priority to 'accept all except vectors 0-31'. An APIC >> + * vector in the 16-31 range could be delivered if TPR == 0, but we >> + * would think it's an exception and terrible things will happen. We >> + * never change this later on. >> */ >> value = apic_read(APIC_TASKPRI); >> value &= ~APIC_TPRI_MASK; >> + value |= 0x10; >> apic_write(APIC_TASKPRI, value); >> >> apic_pending_intr_clear(); > It looks fine, and indeed it seems that writes to APIC_TASKPRI and CR8 are > not overwriting this value. Writes to these two registers should overwrite this value. > Yet, the fact that if someone overwrites with zero (or does not restore) the > TPR will not produce any warning is not that great. Not that I know what the > right course of action is (adding checks in write_cr8()? but then what about > if APIC_TASKPRI is not restored after some APIC reset?) TPR is only written during boot and resume. cr8 is only read and written during suspend/resume, which is redundant with the TPR save/restore.  Dropping that would drop two PVops, and the final trace of the kernel using cr8 itself. All cr8 and TPR accesses in KVM look to be on virtual state, rather than the real registers (as expected). ~Andrew