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Fri, 09 Oct 2020 05:34:57 -0700 (PDT) Subject: Re: [PATCH v7 2/2] soc: mediatek: add mt6779 devapc driver To: Neal Liu Cc: Rob Herring , Chun-Kuang Hu , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, lkml , wsd_upstream@mediatek.com References: <1598497593-15781-1-git-send-email-neal.liu@mediatek.com> <1598497593-15781-3-git-send-email-neal.liu@mediatek.com> <1602124514.28301.17.camel@mtkswgap22> <1602149965.8784.6.camel@mtkswgap22> From: Matthias Brugger Message-ID: <0ece983b-2e55-cf06-aca8-02a014fce090@gmail.com> Date: Fri, 9 Oct 2020 14:34:56 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.12.0 MIME-Version: 1.0 In-Reply-To: <1602149965.8784.6.camel@mtkswgap22> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 08/10/2020 11:39, Neal Liu wrote: > On Thu, 2020-10-08 at 10:45 +0200, Matthias Brugger wrote: >> >> On 08/10/2020 04:35, Neal Liu wrote: >>> On Wed, 2020-10-07 at 12:44 +0200, Matthias Brugger wrote: >>>> >>>> On 27/08/2020 05:06, Neal Liu wrote: [...] >>>>> +static int mtk_devapc_probe(struct platform_device *pdev) >>>>> +{ >>>>> + struct device_node *node = pdev->dev.of_node; >>>>> + struct mtk_devapc_context *ctx; >>>>> + u32 devapc_irq; >>>>> + int ret; >>>>> + >>>>> + if (IS_ERR(node)) >>>>> + return -ENODEV; >>>>> + >>>>> + ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); >>>>> + if (!ctx) >>>>> + return -ENOMEM; >>>>> + >>>>> + ctx->data = of_device_get_match_data(&pdev->dev); >>>>> + ctx->dev = &pdev->dev; >>>>> + >>>>> + ctx->infra_base = of_iomap(node, 0); >>>> >>>> Does this mean the device is part of the infracfg block? >>>> I wasn't able to find any information about it. >>> >>> I'm not sure why you would ask infracfg block. devapc is parts of our >>> SoC infra, it's different with infracfg. >>> >> >> I'm asking because I want to understand the HW better. I'm not able to find any >> information in the datasheets. I want to avoid a situation as we had with the >> MMSYS where a clock driver was submitted first and later on we realized that >> MMSYS is much more then that and we had to work hard to get the driver right. >> >> Now it's happening with SCPSYS, where a driver with the scpsys compatible was >> send years ago. But SCPSYS is much more then the driver submitted. In this case >> we opted to write a new driver, but moving from one driver to another one is >> painfull and full of problems. For that I want to make sure we fully understand >> Device APC (by the way, what does APC stands for?). Is it a totally independent >> HW block or is it part of a subsystem, like for example SCP? >> >> Regards, >> Matthias > > It's a totally independent HW block instead of a subsystem. > I think it's more simple than MMSYS or SCPSYS. But if you would like to > understand more about this HW, we could find another way/channel to > introduce it. > If it's a independent HW block, then we are good. No further information needed by me. I'd just advise to rename the infra_base to something like base, as it made me confuse. Thanks! Matthias