From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
To: andy@infradead.org, qipeng.zha@intel.com, dvhart@infradead.org,
linux@roeck-us.net
Cc: wim@iguana.be, sathyaosid@gmail.com, david.e.box@linux.intel.com,
rajneesh.bhardwaj@intel.com,
sathyanarayanan.kuppuswamy@linux.intel.com,
platform-driver-x86@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org
Subject: [PATCH v6 3/6] watchdog: iTCO_wdt: cleanup set/unset no_reboot_bit functions
Date: Wed, 5 Apr 2017 15:54:21 -0700 [thread overview]
Message-ID: <0ed5bde48b478d1d8e285f1a203f2d424c5b66c1.1491428146.git.sathyanarayanan.kuppuswamy@linux.intel.com> (raw)
In-Reply-To: <3e7ca77c-2be5-5f89-f51f-faaca9f2d9ac@linux.intel.com>
In-Reply-To: <463a23bb1f44098dd0fe506346bae71282009e05.1491428146.git.sathyanarayanan.kuppuswamy@linux.intel.com>
iTCO_wdt no_reboot_bit set/unset functions has lot of common code between
them. So merging these two functions into a single update function would
remove these unnecessary code duplications. This patch fixes this issue
by creating a no_reboot_bit update function to handle both set/unset
functions.
Also checking for iTCO version every time you make no_reboot_bit set/unset
call is inefficient and makes the code look complex. This can be improved
by performing this check once during device probe and selecting the
appropriate no_reboot_bit update function. This patch fixes this issue
by splitting the update function into multiple helper functions.
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
---
drivers/watchdog/iTCO_wdt.c | 83 +++++++++++++++++++++++++++------------------
1 file changed, 50 insertions(+), 33 deletions(-)
Changes since v5:
* Changed update function argument name from "status" to "set".
* Fixed commit history.
* Changed update function name to use "bit" instead of "flag"
* Addressed Andy's comment on creating multiple helper functions.
diff --git a/drivers/watchdog/iTCO_wdt.c b/drivers/watchdog/iTCO_wdt.c
index 3d0abc0..d8768a2 100644
--- a/drivers/watchdog/iTCO_wdt.c
+++ b/drivers/watchdog/iTCO_wdt.c
@@ -106,6 +106,8 @@ struct iTCO_wdt_private {
struct pci_dev *pci_dev;
/* whether or not the watchdog has been suspended */
bool suspended;
+ /* no reboot update function pointer */
+ int (*update_no_reboot_bit)(void *p, bool set);
};
/* module parameters */
@@ -170,48 +172,61 @@ static inline u32 no_reboot_bit(struct iTCO_wdt_private *p)
return enable_bit;
}
-static void iTCO_wdt_set_NO_REBOOT_bit(struct iTCO_wdt_private *p)
+static int inline update_no_reboot_bit_def(void *priv, bool set)
{
- u32 val32;
-
- /* Set the NO_REBOOT bit: this disables reboots */
- if (p->iTCO_version >= 2) {
- val32 = readl(p->gcs_pmc);
- val32 |= no_reboot_bit(p);
- writel(val32, p->gcs_pmc);
- } else if (p->iTCO_version == 1) {
- pci_read_config_dword(p->pci_dev, 0xd4, &val32);
- val32 |= no_reboot_bit(p);
- pci_write_config_dword(p->pci_dev, 0xd4, val32);
- }
+ return 0;
}
-static int iTCO_wdt_unset_NO_REBOOT_bit(struct iTCO_wdt_private *p)
+static int inline update_no_reboot_bit_pci(void *priv, bool set)
{
- u32 enable_bit = no_reboot_bit(p);
- u32 val32 = 0;
+ struct iTCO_wdt_private *p = priv;
+ u32 val32 = 0, newval32 = 0;
- /* Unset the NO_REBOOT bit: this enables reboots */
- if (p->iTCO_version >= 2) {
- val32 = readl(p->gcs_pmc);
- val32 &= ~enable_bit;
- writel(val32, p->gcs_pmc);
+ pci_read_config_dword(p->pci_dev, 0xd4, &val32);
+ if (set)
+ val32 |= no_reboot_bit(p);
+ else
+ val32 &= ~no_reboot_bit(p);
+ pci_write_config_dword(p->pci_dev, 0xd4, val32);
+ pci_read_config_dword(p->pci_dev, 0xd4, &newval32);
- val32 = readl(p->gcs_pmc);
- } else if (p->iTCO_version == 1) {
- pci_read_config_dword(p->pci_dev, 0xd4, &val32);
- val32 &= ~enable_bit;
- pci_write_config_dword(p->pci_dev, 0xd4, val32);
+ /* make sure the update is successful */
+ if (val32 != newval32)
+ return -EIO;
- pci_read_config_dword(p->pci_dev, 0xd4, &val32);
- }
+ return 0;
+}
+
+static int inline update_no_reboot_bit_mem(void *priv, bool set)
+{
+ struct iTCO_wdt_private *p = priv;
+ u32 val32 = 0, newval32 = 0;
+
+ val32 = readl(p->gcs_pmc);
+ if (set)
+ val32 |= no_reboot_bit(p);
+ else
+ val32 &= ~no_reboot_bit(p);
+ writel(val32, p->gcs_pmc);
+ newval32 = readl(p->gcs_pmc);
- if (val32 & enable_bit)
+ /* make sure the update is successful */
+ if (val32 != newval32)
return -EIO;
return 0;
}
+void iTCO_wdt_no_reboot_bit_setup(struct iTCO_wdt_private *p)
+{
+ if (p->iTCO_version >= 2)
+ p->update_no_reboot_bit = update_no_reboot_bit_mem;
+ else if (p->iTCO_version == 1)
+ p->update_no_reboot_bit = update_no_reboot_bit_pci;
+ else
+ p->update_no_reboot_bit = update_no_reboot_bit_def;
+}
+
static int iTCO_wdt_start(struct watchdog_device *wd_dev)
{
struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
@@ -222,7 +237,7 @@ static int iTCO_wdt_start(struct watchdog_device *wd_dev)
iTCO_vendor_pre_start(p->smi_res, wd_dev->timeout);
/* disable chipset's NO_REBOOT bit */
- if (iTCO_wdt_unset_NO_REBOOT_bit(p)) {
+ if (p->update_no_reboot_bit(p, false)) {
spin_unlock(&p->io_lock);
pr_err("failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
return -EIO;
@@ -263,7 +278,7 @@ static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
val = inw(TCO1_CNT(p));
/* Set the NO_REBOOT bit to prevent later reboots, just for sure */
- iTCO_wdt_set_NO_REBOOT_bit(p);
+ p->update_no_reboot_bit(p, true);
spin_unlock(&p->io_lock);
@@ -428,6 +443,8 @@ static int iTCO_wdt_probe(struct platform_device *pdev)
p->iTCO_version = pdata->version;
p->pci_dev = to_pci_dev(dev->parent);
+ iTCO_wdt_no_reboot_bit_setup(p);
+
/*
* Get the Memory-Mapped GCS or PMC register, we need it for the
* NO_REBOOT flag (TCO v2 and v3).
@@ -442,14 +459,14 @@ static int iTCO_wdt_probe(struct platform_device *pdev)
}
/* Check chipset's NO_REBOOT bit */
- if (iTCO_wdt_unset_NO_REBOOT_bit(p) &&
+ if (p->update_no_reboot_bit(p, false) &&
iTCO_vendor_check_noreboot_on()) {
pr_info("unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
return -ENODEV; /* Cannot reset NO_REBOOT bit */
}
/* Set the NO_REBOOT bit to prevent later reboots, just for sure */
- iTCO_wdt_set_NO_REBOOT_bit(p);
+ p->update_no_reboot_bit(p, true);
/* The TCO logic uses the TCO_EN bit in the SMI_EN register */
if (!devm_request_region(dev, p->smi_res->start,
--
2.7.4
next prev parent reply other threads:[~2017-04-05 22:58 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-18 2:06 [PATCH v3 1/5] platform/x86: intel_pmc_ipc: fix gcr offset Kuppuswamy Sathyanarayanan
2017-03-18 2:06 ` [PATCH v3 2/5] platform/x86: intel_pmc_ipc: Add pmc gcr read/write/update api's Kuppuswamy Sathyanarayanan
2017-03-31 13:47 ` Rajneesh Bhardwaj
2017-03-18 2:06 ` [PATCH v3 3/5] watchdog: iTCO_wdt: Add PMC specific noreboot update api Kuppuswamy Sathyanarayanan
2017-03-28 9:12 ` [v3,3/5] " Guenter Roeck
2017-03-18 2:06 ` [PATCH v3 4/5] platform/x86: intel_pmc_ipc: Fix iTCO GCS memory mapping failure Kuppuswamy Sathyanarayanan
2017-03-31 14:01 ` Rajneesh Bhardwaj
2017-03-31 17:22 ` sathyanarayanan kuppuswamy
2017-03-18 2:06 ` [PATCH v3 5/5] platform/x86: intel_pmc_ipc: use gcr mem base for S0ix counter read Kuppuswamy Sathyanarayanan
2017-03-31 13:54 ` Rajneesh Bhardwaj
2017-03-31 15:08 ` Shanth Murthy
2017-03-31 13:37 ` [PATCH v3 1/5] platform/x86: intel_pmc_ipc: fix gcr offset Rajneesh Bhardwaj
2017-03-31 23:27 ` [PATCH v4 " Kuppuswamy Sathyanarayanan
2017-03-31 23:27 ` [PATCH v4 2/5] platform/x86: intel_pmc_ipc: Add pmc gcr read/write/update api's Kuppuswamy Sathyanarayanan
2017-04-02 13:58 ` Andy Shevchenko
2017-04-03 1:51 ` Sathyanarayanan Kuppuswamy Natarajan
2017-04-04 13:23 ` Andy Shevchenko
2017-04-04 20:14 ` sathyanarayanan kuppuswamy
2017-03-31 23:27 ` [PATCH v4 3/5] watchdog: iTCO_wdt: Add PMC specific noreboot update api Kuppuswamy Sathyanarayanan
2017-04-02 14:04 ` Andy Shevchenko
2017-04-03 1:55 ` Sathyanarayanan Kuppuswamy Natarajan
2017-03-31 23:27 ` [PATCH v4 4/5] platform/x86: intel_pmc_ipc: Fix iTCO GCS memory mapping failure Kuppuswamy Sathyanarayanan
2017-04-02 14:10 ` Andy Shevchenko
2017-04-03 1:53 ` Sathyanarayanan Kuppuswamy Natarajan
2017-03-31 23:27 ` [PATCH v4 5/5] platform/x86: intel_pmc_ipc: use gcr mem base for S0ix counter read Kuppuswamy Sathyanarayanan
2017-04-02 14:11 ` [PATCH v4 1/5] platform/x86: intel_pmc_ipc: fix gcr offset Andy Shevchenko
2017-04-03 1:51 ` Sathyanarayanan Kuppuswamy Natarajan
2017-04-04 0:24 ` [PATCH v5 1/6] " Kuppuswamy Sathyanarayanan
2017-04-04 0:24 ` [PATCH v5 2/6] platform/x86: intel_pmc_ipc: Add pmc gcr read/write/update api's Kuppuswamy Sathyanarayanan
2017-04-04 13:53 ` Andy Shevchenko
2017-04-04 22:07 ` sathyanarayanan kuppuswamy
2017-04-04 0:24 ` [PATCH v5 3/6] watchdog: iTCO_wdt: Add PMC specific noreboot update api Kuppuswamy Sathyanarayanan
2017-04-04 13:48 ` Andy Shevchenko
2017-04-04 0:24 ` [PATCH v5 4/6] watchdog: iTCO_wdt: cleanup set/unset no_reboot calls Kuppuswamy Sathyanarayanan
2017-04-04 3:22 ` Guenter Roeck
2017-04-04 13:49 ` Andy Shevchenko
2017-04-04 0:24 ` [PATCH v5 5/6] platform/x86: intel_pmc_ipc: Fix iTCO_wdt GCS memory mapping failure Kuppuswamy Sathyanarayanan
2017-04-04 13:53 ` Andy Shevchenko
2017-04-04 0:24 ` [PATCH v5 6/6] platform/x86: intel_pmc_ipc: use gcr mem base for S0ix counter read Kuppuswamy Sathyanarayanan
2017-04-04 13:51 ` Andy Shevchenko
2017-04-04 22:15 ` sathyanarayanan kuppuswamy
2017-04-04 13:25 ` [PATCH v4 1/5] platform/x86: intel_pmc_ipc: fix gcr offset Andy Shevchenko
2017-04-04 21:32 ` sathyanarayanan kuppuswamy
2017-04-05 22:54 ` [PATCH v6 1/6] " Kuppuswamy Sathyanarayanan
2017-04-05 22:54 ` [PATCH v6 2/6] platform/x86: intel_pmc_ipc: Add pmc gcr read/write/update api's Kuppuswamy Sathyanarayanan
2017-04-05 22:54 ` Kuppuswamy Sathyanarayanan [this message]
2017-04-05 22:54 ` [PATCH v6 4/6] watchdog: iTCO_wdt: Add PMC specific noreboot update api Kuppuswamy Sathyanarayanan
2017-04-06 11:42 ` Guenter Roeck
2017-04-05 22:54 ` [PATCH v6 5/6] platform/x86: intel_pmc_ipc: Fix iTCO_wdt GCS memory mapping failure Kuppuswamy Sathyanarayanan
2017-04-06 21:37 ` Andy Shevchenko
2017-04-05 22:54 ` [PATCH v6 6/6] platform/x86: intel_pmc_ipc: use gcr mem base for S0ix counter read Kuppuswamy Sathyanarayanan
2017-04-06 15:16 ` [PATCH v6 1/6] platform/x86: intel_pmc_ipc: fix gcr offset Rajneesh Bhardwaj
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=0ed5bde48b478d1d8e285f1a203f2d424c5b66c1.1491428146.git.sathyanarayanan.kuppuswamy@linux.intel.com \
--to=sathyanarayanan.kuppuswamy@linux.intel.com \
--cc=andy@infradead.org \
--cc=david.e.box@linux.intel.com \
--cc=dvhart@infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-watchdog@vger.kernel.org \
--cc=linux@roeck-us.net \
--cc=platform-driver-x86@vger.kernel.org \
--cc=qipeng.zha@intel.com \
--cc=rajneesh.bhardwaj@intel.com \
--cc=sathyaosid@gmail.com \
--cc=wim@iguana.be \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).