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* PCI cache line messages 2.4/2.5
@ 2003-06-02  6:59 Margit Schubert-While
  2003-06-04 22:39 ` Jeff Garzik
  0 siblings, 1 reply; 14+ messages in thread
From: Margit Schubert-While @ 2003-06-02  6:59 UTC (permalink / raw)
  To: linux-kernel

[-- Attachment #1: Type: text/plain, Size: 341 bytes --]

Getting this with 2.5.70(-bk)  :
PCI: cache line size of 128 is not supported by device 00:1d.7

and this with 2.4.2(0,1,pre,rc) :
PCI: 00:1d.7 PCI cache line size set incorrectly (0 bytes) by BIOS/FW.
PCI: 00:1d.7 PCI cache line size corrected to 128.

This is the onboard USB EHCI (Intel D845 PESV).
lspci below.

What's going on ?

Margit

[-- Attachment #2: lspci --]
[-- Type: application/octet-stream, Size: 10055 bytes --]

00:00.0 Host bridge: Intel Corp. 82845G/GL [Brookdale-G] Chipset Host Bridge (rev 02)
	Subsystem: Intel Corp. 82845G/GL [Brookdale-G] Chipset Host Bridge
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort+ >SERR- <PERR-
	Latency: 0
	Region 0: Memory at f8000000 (32-bit, prefetchable) [size=64M]
	Capabilities: [e4] #09 [6105]
	Capabilities: [a0] AGP version 2.0
		Status: RQ=31 SBA+ 64bit- FW+ Rate=x1,x2,x4
		Command: RQ=0 SBA+ AGP+ 64bit- FW- Rate=x4

00:01.0 PCI bridge: Intel Corp. 82845G/GL [Brookdale-G] Chipset AGP Bridge (rev 02) (prog-if 00 [Normal decode])
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap- 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 32
	Bus: primary=00, secondary=01, subordinate=01, sec-latency=32
	I/O behind bridge: 0000c000-0000cfff
	Memory behind bridge: ff800000-ff8fffff
	Prefetchable memory behind bridge: d6900000-f69fffff
	BridgeCtl: Parity- SERR- NoISA- VGA+ MAbort- >Reset- FastB2B-

00:1d.0 USB Controller: Intel Corp. 82801DB USB (Hub #1) (rev 02) (prog-if 00 [UHCI])
	Subsystem: Intel Corp.: Unknown device 5356
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0
	Interrupt: pin A routed to IRQ 16
	Region 4: I/O ports at e800 [size=32]

00:1d.1 USB Controller: Intel Corp. 82801DB USB (Hub #2) (rev 02) (prog-if 00 [UHCI])
	Subsystem: Intel Corp.: Unknown device 5356
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0
	Interrupt: pin B routed to IRQ 19
	Region 4: I/O ports at e880 [size=32]

00:1d.2 USB Controller: Intel Corp. 82801DB USB (Hub #3) (rev 02) (prog-if 00 [UHCI])
	Subsystem: Intel Corp.: Unknown device 5356
	Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0
	Interrupt: pin C routed to IRQ 18
	Region 4: I/O ports at ec00 [size=32]

00:1d.7 USB Controller: Intel Corp. 82801DB USB EHCI Controller (rev 02) (prog-if 20 [EHCI])
	Subsystem: Intel Corp.: Unknown device 5356
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0
	Interrupt: pin D routed to IRQ 23
	Region 0: Memory at ffaffc00 (32-bit, non-prefetchable) [size=1K]
	Capabilities: [50] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [58] #0a [2080]

00:1e.0 PCI bridge: Intel Corp. 82801BA/CA/DB PCI Bridge (rev 82) (prog-if 00 [Normal decode])
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR+
	Latency: 0
	Bus: primary=00, secondary=02, subordinate=02, sec-latency=32
	I/O behind bridge: 0000d000-0000dfff
	Memory behind bridge: ff900000-ff9fffff
	Prefetchable memory behind bridge: f6a00000-f6afffff
	BridgeCtl: Parity- SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-

00:1f.0 ISA bridge: Intel Corp. 82801DB ISA Bridge (LPC) (rev 02)
	Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0

00:1f.1 IDE interface: Intel Corp. 82801DB ICH4 IDE (rev 02) (prog-if 8a [Master SecP PriP])
	Subsystem: Intel Corp.: Unknown device 5356
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Interrupt: pin A routed to IRQ 18
	Region 0: I/O ports at <unassigned> [disabled]
	Region 1: I/O ports at <unassigned> [disabled]
	Region 2: I/O ports at <unassigned> [disabled]
	Region 3: I/O ports at <unassigned> [disabled]
	Region 4: I/O ports at ffa0 [disabled] [size=16]
	Region 5: Memory at 20000000 (32-bit, non-prefetchable) [disabled] [size=1K]

00:1f.3 SMBus: Intel Corp. 82801DB SMBus (rev 02)
	Subsystem: Intel Corp.: Unknown device 5356
	Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Interrupt: pin B routed to IRQ 17
	Region 4: I/O ports at e000 [size=32]

00:1f.5 Multimedia audio controller: Intel Corp. 82801DB AC'97 Audio (rev 02)
	Subsystem: Intel Corp.: Unknown device 0106
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 0
	Interrupt: pin B routed to IRQ 17
	Region 0: I/O ports at e400 [size=256]
	Region 1: I/O ports at e080 [size=64]
	Region 2: Memory at ffaff800 (32-bit, non-prefetchable) [size=512]
	Region 3: Memory at ffaff400 (32-bit, non-prefetchable) [size=256]
	Capabilities: [50] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=375mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-

01:00.0 VGA compatible controller: ATI Technologies Inc Radeon RV200 QW [Radeon 7500] (prog-if 00 [VGA])
	Subsystem: Unknown device 17af:2002
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR+ FastB2B-
	Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 32 (2000ns min), cache line size 08
	Interrupt: pin A routed to IRQ 16
	Region 0: Memory at e0000000 (32-bit, prefetchable) [size=256M]
	Region 1: I/O ports at c800 [size=256]
	Region 2: Memory at ff8f0000 (32-bit, non-prefetchable) [size=64K]
	Expansion ROM at ff8c0000 [disabled] [size=128K]
	Capabilities: [58] AGP version 2.0
		Status: RQ=47 SBA+ 64bit- FW- Rate=x1,x2,x4
		Command: RQ=31 SBA+ AGP+ 64bit- FW- Rate=x4
	Capabilities: [50] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-

02:01.0 SCSI storage controller: Adaptec AHA-3960D / AIC-7899A U160/m (rev 01)
	Subsystem: Adaptec AHA-3960D U160/m
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 32 (10000ns min, 6250ns max), cache line size 08
	Interrupt: pin A routed to IRQ 22
	BIST result: 00
	Region 0: I/O ports at d400 [disabled] [size=256]
	Region 1: Memory at ff9fe000 (64-bit, non-prefetchable) [size=4K]
	Expansion ROM at ff9a0000 [disabled] [size=128K]
	Capabilities: [dc] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-

02:01.1 SCSI storage controller: Adaptec AHA-3960D / AIC-7899A U160/m (rev 01)
	Subsystem: Adaptec AHA-3960D U160/m
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66Mhz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 32 (10000ns min, 6250ns max), cache line size 08
	Interrupt: pin B routed to IRQ 21
	BIST result: 00
	Region 0: I/O ports at d800 [disabled] [size=256]
	Region 1: Memory at ff9ff000 (64-bit, non-prefetchable) [size=4K]
	Expansion ROM at ff9c0000 [disabled] [size=128K]
	Capabilities: [dc] Power Management version 2
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-

02:04.0 Network controller: AVM Audiovisuelles MKTG & Computer System GmbH A1 ISDN [Fritz] (rev 02)
	Subsystem: AVM Audiovisuelles MKTG & Computer System GmbH FRITZ!Card ISDN Controller
	Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Interrupt: pin A routed to IRQ 17
	Region 0: Memory at ff9fdc00 (32-bit, non-prefetchable) [size=32]
	Region 1: I/O ports at dc00 [size=32]

02:05.0 SCSI storage controller: Adaptec AIC-7861 (rev 03)
	Subsystem: Adaptec AHA-2940AU Single
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 32 (1000ns min, 1000ns max), cache line size 08
	Interrupt: pin A routed to IRQ 18
	Region 0: I/O ports at d000 [disabled] [size=256]
	Region 1: Memory at ff9fc000 (32-bit, non-prefetchable) [size=4K]
	Expansion ROM at ff9e0000 [disabled] [size=64K]
	Capabilities: [dc] Power Management version 1
		Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 PME-Enable- DSel=0 DScale=0 PME-

02:08.0 Ethernet controller: Intel Corp. 82801BD PRO/100 VE (LOM) Ethernet Controller (rev 82)
	Subsystem: Intel Corp.: Unknown device 3015
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR+ FastB2B-
	Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
	Latency: 32 (2000ns min, 14000ns max), cache line size 08
	Interrupt: pin A routed to IRQ 20
	Region 0: Memory at ff9fb000 (32-bit, non-prefetchable) [size=4K]
	Region 1: I/O ports at df00 [size=64]
	Capabilities: [dc] Power Management version 2
		Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+)
		Status: D0 PME-Enable- DSel=0 DScale=2 PME-


^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: PCI cache line messages 2.4/2.5
  2003-06-02  6:59 PCI cache line messages 2.4/2.5 Margit Schubert-While
@ 2003-06-04 22:39 ` Jeff Garzik
  2003-06-05 10:39   ` Alan Cox
  0 siblings, 1 reply; 14+ messages in thread
From: Jeff Garzik @ 2003-06-04 22:39 UTC (permalink / raw)
  To: Margit Schubert-While; +Cc: linux-kernel

Margit Schubert-While wrote:
> Getting this with 2.5.70(-bk)  :
> PCI: cache line size of 128 is not supported by device 00:1d.7
> 
> and this with 2.4.2(0,1,pre,rc) :
> PCI: 00:1d.7 PCI cache line size set incorrectly (0 bytes) by BIOS/FW.
> PCI: 00:1d.7 PCI cache line size corrected to 128.
> 
> This is the onboard USB EHCI (Intel D845 PESV).
> lspci below.
> 
> What's going on ?


Pretty much exactly what the message says :)

Your BIOS did not set the PCI cache line size correctly.  The kernel 
caught that mistake, and fixed it.

	Jeff




^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: PCI cache line messages 2.4/2.5
  2003-06-04 22:39 ` Jeff Garzik
@ 2003-06-05 10:39   ` Alan Cox
  2003-06-05 11:05     ` David S. Miller
  0 siblings, 1 reply; 14+ messages in thread
From: Alan Cox @ 2003-06-05 10:39 UTC (permalink / raw)
  To: Jeff Garzik; +Cc: Margit Schubert-While, Linux Kernel Mailing List

On Mer, 2003-06-04 at 23:39, Jeff Garzik wrote:
> > PCI: 00:1d.7 PCI cache line size set incorrectly (0 bytes) by BIOS/FW.
> > PCI: 00:1d.7 PCI cache line size corrected to 128.
> > 
> > This is the onboard USB EHCI (Intel D845 PESV).
> > lspci below.
> > 
> > What's going on ?
> 
> 
> Pretty much exactly what the message says :)
> 
> Your BIOS did not set the PCI cache line size correctly.  The kernel 
> caught that mistake, and fixed it.

I can't find anywhere the BIOS is obliged to set it for you if a PnP OS
is installed, ditto in the presence of any form of hotplug the test is
wrong.

As far as I can see you can only warn if MWI is already set in the
control word, and (I'd have to check the spec) possibly if the
cache line size is non zero.

(simple hotplug thought experiment to prove the point

	Soft boot a thinkpad 600
	As the bios transfers to grub insert in docking station
	
explain how the bios sets the cache line size..)


^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: PCI cache line messages 2.4/2.5
  2003-06-05 10:39   ` Alan Cox
@ 2003-06-05 11:05     ` David S. Miller
  2003-06-05 11:20       ` Alan Cox
  0 siblings, 1 reply; 14+ messages in thread
From: David S. Miller @ 2003-06-05 11:05 UTC (permalink / raw)
  To: Alan Cox; +Cc: Jeff Garzik, Margit Schubert-While, Linux Kernel Mailing List

On Thu, 2003-06-05 at 03:39, Alan Cox wrote:
> > Your BIOS did not set the PCI cache line size correctly.  The kernel 
> > caught that mistake, and fixed it.
> 
> I can't find anywhere the BIOS is obliged to set it for you if a PnP OS
> is installed, ditto in the presence of any form of hotplug the test is
> wrong.
> 
> As far as I can see you can only warn if MWI is already set in the
> control word, and (I'd have to check the spec) possibly if the
> cache line size is non zero.

I don't know how PnP OS plays into it, but the last time I dug into this
deep dark area, the BIOS was expected to setup the cache line size for
all PCI devices in the system.

I do specifically remember situations, involving Acenic cards, where
one Acenic card would have things setup correctly but for whatever
reason the BIOS decided not to init the other Acenic cards.

-- 
David S. Miller <davem@redhat.com>

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: PCI cache line messages 2.4/2.5
  2003-06-05 11:05     ` David S. Miller
@ 2003-06-05 11:20       ` Alan Cox
  2003-06-05 11:25         ` David S. Miller
  0 siblings, 1 reply; 14+ messages in thread
From: Alan Cox @ 2003-06-05 11:20 UTC (permalink / raw)
  To: David S. Miller
  Cc: Jeff Garzik, Margit Schubert-While, Linux Kernel Mailing List

On Iau, 2003-06-05 at 12:05, David S. Miller wrote:
> I don't know how PnP OS plays into it, but the last time I dug into this
> deep dark area, the BIOS was expected to setup the cache line size for
> all PCI devices in the system.

With a non PnP OS the BIOS is supposed to have done a lot of the setup
for things like IRQ routing. With a PnP OS (and nowdays thats often not
even a selectable but a wired in property) the OS has to do a lot of
the work.

And then there is hotplug


^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: PCI cache line messages 2.4/2.5
  2003-06-05 11:20       ` Alan Cox
@ 2003-06-05 11:25         ` David S. Miller
  2003-06-05 19:48           ` Alan Cox
  0 siblings, 1 reply; 14+ messages in thread
From: David S. Miller @ 2003-06-05 11:25 UTC (permalink / raw)
  To: alan; +Cc: jgarzik, margitsw, linux-kernel

   From: Alan Cox <alan@lxorguk.ukuu.org.uk>
   Date: 05 Jun 2003 12:20:12 +0100
   
   And then there is hotplug
   
My understanding is that the bioses do the cacheline, irq,
etc. assignment via BIOS callbacks done by the PCI controller hotplug
driver.


^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: PCI cache line messages 2.4/2.5
  2003-06-05 11:25         ` David S. Miller
@ 2003-06-05 19:48           ` Alan Cox
  2003-06-06  5:11             ` David S. Miller
  0 siblings, 1 reply; 14+ messages in thread
From: Alan Cox @ 2003-06-05 19:48 UTC (permalink / raw)
  To: David S. Miller; +Cc: jgarzik, margitsw, Linux Kernel Mailing List

On Iau, 2003-06-05 at 12:25, David S. Miller wrote:
>    From: Alan Cox <alan@lxorguk.ukuu.org.uk>
>    Date: 05 Jun 2003 12:20:12 +0100
>    
>    And then there is hotplug
>    
> My understanding is that the bioses do the cacheline, irq,
> etc. assignment via BIOS callbacks done by the PCI controller hotplug
> driver.

Ah cloud cuckoo land 8)

Come on down Dave ;)


^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: PCI cache line messages 2.4/2.5
  2003-06-05 19:48           ` Alan Cox
@ 2003-06-06  5:11             ` David S. Miller
  2003-06-06 15:27               ` Alan Cox
  0 siblings, 1 reply; 14+ messages in thread
From: David S. Miller @ 2003-06-06  5:11 UTC (permalink / raw)
  To: alan; +Cc: jgarzik, margitsw, linux-kernel

   From: Alan Cox <alan@lxorguk.ukuu.org.uk>
   Date: 05 Jun 2003 20:48:42 +0100

   On Iau, 2003-06-05 at 12:25, David S. Miller wrote:
   > My understanding is that the bioses do the cacheline, irq,
   > etc. assignment via BIOS callbacks done by the PCI controller hotplug
   > driver.
   
   Ah cloud cuckoo land 8)
   
First, can I get some english without the welsh grammar? :-)
Second, BIOS callbacks are exactly what I see the compaq hotplug
PCI driver doing.

   Come on down Dave ;)
   
:)

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: PCI cache line messages 2.4/2.5
  2003-06-06  5:11             ` David S. Miller
@ 2003-06-06 15:27               ` Alan Cox
  2003-06-06 15:30                 ` David S. Miller
  0 siblings, 1 reply; 14+ messages in thread
From: Alan Cox @ 2003-06-06 15:27 UTC (permalink / raw)
  To: David S. Miller; +Cc: jgarzik, margitsw, Linux Kernel Mailing List

On Gwe, 2003-06-06 at 06:11, David S. Miller wrote:
> First, can I get some english without the welsh grammar? :-)
> Second, BIOS callbacks are exactly what I see the compaq hotplug
> PCI driver doing.

The compaq driver isnt loaded at this point. There is a window of
opportunity


^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: PCI cache line messages 2.4/2.5
  2003-06-06 15:27               ` Alan Cox
@ 2003-06-06 15:30                 ` David S. Miller
  0 siblings, 0 replies; 14+ messages in thread
From: David S. Miller @ 2003-06-06 15:30 UTC (permalink / raw)
  To: alan; +Cc: jgarzik, margitsw, linux-kernel

   From: Alan Cox <alan@lxorguk.ukuu.org.uk>
   Date: 06 Jun 2003 16:27:48 +0100
   
   The compaq driver isnt loaded at this point. There is a window of
   opportunity
   
Point.  But %99 of the time it's the dang BIOS doing something wrong.
We SHOULD take care of that case, and whether it's nice to log a
message about it or not is a seperate matter.

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: PCI cache line messages 2.4/2.5
  2003-06-05 15:23 Margit Schubert-While
@ 2003-06-06 12:06 ` Ivan Kokshaysky
  0 siblings, 0 replies; 14+ messages in thread
From: Ivan Kokshaysky @ 2003-06-06 12:06 UTC (permalink / raw)
  To: Margit Schubert-While; +Cc: linux-kernel

On Thu, Jun 05, 2003 at 05:23:54PM +0200, Margit Schubert-While wrote:
> With what (if any) consequences under 2.4 ?
> Shouldn't it be fixed for 2.4.21 ?

More likely for early 2.4.22-pre. In the worst case you'd
end up enabling MWI with cacheline size = 0, which
should be a no-op on any sane hardware.

Ivan.

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: PCI cache line messages 2.4/2.5
@ 2003-06-05 15:23 Margit Schubert-While
  2003-06-06 12:06 ` Ivan Kokshaysky
  0 siblings, 1 reply; 14+ messages in thread
From: Margit Schubert-While @ 2003-06-05 15:23 UTC (permalink / raw)
  To: linux-kernel

 > Ivan wrote :
 > 2.5 and BIOS are correct, 2.4 is not.

With what (if any) consequences under 2.4 ?
Shouldn't it be fixed for 2.4.21 ?

Margit


^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: PCI cache line messages 2.4/2.5
  2003-06-05  6:12 Margit Schubert-While
@ 2003-06-05 11:58 ` Ivan Kokshaysky
  0 siblings, 0 replies; 14+ messages in thread
From: Ivan Kokshaysky @ 2003-06-05 11:58 UTC (permalink / raw)
  To: Margit Schubert-While; +Cc: linux-kernel, Jeff Garzik

On Thu, Jun 05, 2003 at 08:12:05AM +0200, Margit Schubert-While wrote:
> 2.4 gets 0 and sets 128. 2.5 gets 128 and reports it wrong.

2.4 writes 128 without reading it back; 2.5 writes 128, read it back
and gets 0. Thus "not supported" message, which means that you
cannot use MWI on this device.

2.5 and BIOS are correct, 2.4 is not.

Ivan.

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: PCI cache line messages 2.4/2.5
@ 2003-06-05  6:12 Margit Schubert-While
  2003-06-05 11:58 ` Ivan Kokshaysky
  0 siblings, 1 reply; 14+ messages in thread
From: Margit Schubert-While @ 2003-06-05  6:12 UTC (permalink / raw)
  To: linux-kernel; +Cc: Jeff Garzik

 > Jeff Garzik wrote :
 > Your BIOS did not set the PCI cache line size correctly.

Well, 2 questions :
2.4 gets 0 and sets 128. 2.5 gets 128 and reports it wrong.
This seems a contradiction. Which is right ?
Why only this port on the (onboard) USB hub ?

Margit


^ permalink raw reply	[flat|nested] 14+ messages in thread

end of thread, other threads:[~2003-06-06 15:19 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2003-06-02  6:59 PCI cache line messages 2.4/2.5 Margit Schubert-While
2003-06-04 22:39 ` Jeff Garzik
2003-06-05 10:39   ` Alan Cox
2003-06-05 11:05     ` David S. Miller
2003-06-05 11:20       ` Alan Cox
2003-06-05 11:25         ` David S. Miller
2003-06-05 19:48           ` Alan Cox
2003-06-06  5:11             ` David S. Miller
2003-06-06 15:27               ` Alan Cox
2003-06-06 15:30                 ` David S. Miller
2003-06-05  6:12 Margit Schubert-While
2003-06-05 11:58 ` Ivan Kokshaysky
2003-06-05 15:23 Margit Schubert-While
2003-06-06 12:06 ` Ivan Kokshaysky

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