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Date: Mon, 05 Sep 2016 12:24:18 -0700
From: Stefan Agner <stefan@agner.ch>
To: Meng Yi <meng.yi@nxp.com>
Cc: dri-devel@lists.freedesktop.org, alison.wang@freescale.com,
        jianwei.wang.chn@gmail.com, linux-kernel@vger.kernel.org,
        stable@vger.kernel.org
Subject: RE: [PATCH] drm/fsl-dcu: fix endian issue when using
 clk_register_divider
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References: <20160902190753.27736-1-stefan@agner.ch>
 <DB6PR0401MB2631D676D8D91B9E71566911ECE60@DB6PR0401MB2631.eurprd04.prod.outlook.com>
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On 2016-09-05 01:46, Meng Yi wrote:
>> Subject: [PATCH] drm/fsl-dcu: fix endian issue when using clk_register_divider
>>
>> Since using clk_register_divider to setup the pixel clock, regmap is no longer
>> used. Regmap did take care of DCU using different endianness. Check
>> endianness using the device-tree property "big-endian" to determine the
>> location of DIV_RATIO.
>>
>> Cc: stable@vger.kernel.org
>> Fixes: 2d701449bce1 ("drm/fsl-dcu: use common clock framework for pixel
>> clock divider")
>> Reported-by: Meng Yi <meng.yi@nxp.com>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>

<snip>

> 
> Tested-by: Meng Yi <meng.yi@nxp.com>
> On LS1021A-TWR board.

Thanks, applied!

--
Stefan