From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AF64C10F11 for ; Wed, 24 Apr 2019 10:19:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0205C20878 for ; Wed, 24 Apr 2019 10:19:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728218AbfDXKTR (ORCPT ); Wed, 24 Apr 2019 06:19:17 -0400 Received: from gecko.sbs.de ([194.138.37.40]:58231 "EHLO gecko.sbs.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726039AbfDXKTR (ORCPT ); Wed, 24 Apr 2019 06:19:17 -0400 Received: from mail2.sbs.de (mail2.sbs.de [192.129.41.66]) by gecko.sbs.de (8.15.2/8.15.2) with ESMTPS id x3OAJ379014948 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 24 Apr 2019 12:19:03 +0200 Received: from [139.22.114.195] ([139.22.114.195]) by mail2.sbs.de (8.15.2/8.15.2) with ESMTP id x3OAJ2vF026053; Wed, 24 Apr 2019 12:19:02 +0200 Subject: Re: [PATCH 2/2] gpio: sch: Add interrupt support To: Mika Westerberg Cc: Andy Shevchenko , Linus Walleij , Bartosz Golaszewski , Linux Kernel Mailing List , linux-gpio@vger.kernel.org, linux-acpi@vger.kernel.org, "Rafael J. Wysocki" References: <20190424075816.GU2654@lahna.fi.intel.com> <8999d3f8-d169-eb85-bd2f-08c99d184ea2@siemens.com> <20190424081802.GV2654@lahna.fi.intel.com> <5a28f22c-22f7-760a-d076-68ff19800d44@siemens.com> <20190424084259.GW2654@lahna.fi.intel.com> <7e328b7e-f4f0-851a-4152-a9ffd058201c@siemens.com> <20190424094506.GA2654@lahna.fi.intel.com> <292e6eff-82cc-6e4d-925b-77a60399e2e0@siemens.com> <20190424100130.GB2654@lahna.fi.intel.com> From: Jan Kiszka Message-ID: <1200464b-f969-ebc2-ae82-1f8ca98aaca1@siemens.com> Date: Wed, 24 Apr 2019 12:19:02 +0200 User-Agent: Mozilla/5.0 (X11; U; Linux i686 (x86_64); de; rv:1.8.1.12) Gecko/20080226 SUSE/2.0.0.12-1.1 Thunderbird/2.0.0.12 Mnenhy/0.7.5.666 MIME-Version: 1.0 In-Reply-To: <20190424100130.GB2654@lahna.fi.intel.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 24.04.19 12:01, Mika Westerberg wrote: > On Wed, Apr 24, 2019 at 11:48:09AM +0200, Jan Kiszka wrote: >> On 24.04.19 11:45, Mika Westerberg wrote: >>> On Wed, Apr 24, 2019 at 11:36:58AM +0200, Jan Kiszka wrote: >>>> OK, there is that table, but what is it supposed to tell me about the >>>> event and where to hook into it better? >>> ... >>>> [02Eh 0046 2] SCI Interrupt : 0009 >>> >>> This is the SCI interrupt GSI number. IIRC it maps 1:1 to Linux >>> interrupt number so you should see it in /proc/interrupts. When a GPE >>> event is triggered it should be handled in the ACPI core. >>> >> >> Yes, clear, all this happens already. But I need to link the core with the >> sch gpio handler so that the gpio event is filtered out and the right >> virtual gpio interrupt is triggered. So, other than >> acpi_install_sci_handler, how should I establish that link? > > I think what you want is "GPIO signaled ACPI event". It works so that > you declare _AEI method below the GPIO controller listing the GPIOs you > want to trigger events for and then either _Lxx, _Exx or _EVT method for > each of them under the same controller. GPIO core then handles it > automatically when you register the GPIO chip. See also > acpi_gpiochip_request_interrupts(). > Right, that is was I read as well. Let's assume I would be able to patch the tables: Would I describe all the logic of this patch in ACPI terms? Where to enable interrupts, how to dispatch the SCI event, how to acknowledge it etc.? Will it also take care of locking? (BTW, my locking seems to have some remaining inconsistency, on second look.) And even if that were possible, we would be back to the square of existing devices without those definitions. If this were a recent chipset, I would say, "go, fix future firmware versions". But this one is legacy. Jan -- Siemens AG, Corporate Technology, CT RDA IOT SES-DE Corporate Competence Center Embedded Linux