[PATCH v4 0/6] arm64: dts: ti: Add USB support for J7200 EVM

[PATCH v4 0/6] arm64: dts: ti: Add USB support for J7200 EVM

[Roger Quadros]

Hi Tero/Nishanth,

This series adds USB2.0 support for the J7200 EVM.

Series is based on top of:

    Faiz's MMC/SD support series
    https://lore.kernel.org/lkml/20200907090520.25313-1-faiz_abbas@ti.com/
    Lokesh's initial support series
    https://patchwork.kernel.org/cover/11740039/
    Vignesh's I2C support series
    https://lore.kernel.org/patchwork/cover/1282152/
    Vignesh's Hyperflash series
    https://lore.kernel.org/patchwork/cover/1285326/
    MUX binding cleanup
    https://lore.kernel.org/lkml/20200918165930.2031-1-rogerq@ti.com/

cheers,
-roger

Changelog:
v4:
- use single header file for MUX defines. drop WIZ from macro names.

v3:
- use 0x00 instead of 0x0 in device tree for consistency.
- update commit log for USB support patch.

v2:
- fixed warnings when built with W=2. Still one warning is present
as property name "dr_mode" by USB core contains underscore.

Kishon Vijay Abraham I (1):
  arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane
    function

Roger Quadros (5):
  dt-bindings: ti-serdes-mux: Add defines for J7200 SoC
  arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux
  arm64: dts: ti: k3-j7200-main.dtsi: Add USB to SERDES lane MUX
  arm64: dts: ti: k3-j7200-main: Add USB controller
  arm64: dts: ti: k3-j7200-common-proc-board: Add USB support

 .../dts/ti/k3-j7200-common-proc-board.dts     | 28 ++++++++++
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi     | 51 +++++++++++++++++++
 include/dt-bindings/mux/ti-serdes.h           | 22 ++++++++
 3 files changed, 101 insertions(+)

-- 
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH v4 1/6] dt-bindings: ti-serdes-mux: Add defines for J7200 SoC

[Roger Quadros]

There are 4 lanes in each J7200 SERDES. Each SERDES lane mux can
select upto 4 different IPs. Define all the possible functions.

Cc: Peter Rosin <peda@axentia.se>
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 include/dt-bindings/mux/ti-serdes.h | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h
index 146d0685a925..9047ec6bd3cf 100644
--- a/include/dt-bindings/mux/ti-serdes.h
+++ b/include/dt-bindings/mux/ti-serdes.h
@@ -68,4 +68,26 @@
 #define J721E_SERDES4_LANE3_QSGMII_LANE8	0x2
 #define J721E_SERDES4_LANE3_IP4_UNUSED		0x3
 
+/* J7200 */
+
+#define J7200_SERDES0_LANE0_QSGMII_LANE3	0x0
+#define J7200_SERDES0_LANE0_PCIE1_LANE0		0x1
+#define J7200_SERDES0_LANE0_IP3_UNUSED		0x2
+#define J7200_SERDES0_LANE0_IP4_UNUSED		0x3
+
+#define J7200_SERDES0_LANE1_QSGMII_LANE4	0x0
+#define J7200_SERDES0_LANE1_PCIE1_LANE1		0x1
+#define J7200_SERDES0_LANE1_IP3_UNUSED		0x2
+#define J7200_SERDES0_LANE1_IP4_UNUSED		0x3
+
+#define J7200_SERDES0_LANE2_QSGMII_LANE1	0x0
+#define J7200_SERDES0_LANE2_PCIE1_LANE2		0x1
+#define J7200_SERDES0_LANE2_IP3_UNUSED		0x2
+#define J7200_SERDES0_LANE2_IP4_UNUSED		0x3
+
+#define J7200_SERDES0_LANE3_QSGMII_LANE2	0x0
+#define J7200_SERDES0_LANE3_PCIE1_LANE3		0x1
+#define J7200_SERDES0_LANE3_USB			0x2
+#define J7200_SERDES0_LANE3_IP4_UNUSED		0x3
+
 #endif /* _DT_BINDINGS_MUX_TI_SERDES */
-- 
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH v4 2/6] arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux

[Roger Quadros]

The SERDES lane control mux registers are present in the
CTRLMMR space.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 1702ac0bbf40..d6d688efc32a 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -18,6 +18,21 @@
 		};
 	};
 
+	scm_conf: scm-conf@100000 {
+		compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+		reg = <0x00 0x00100000 0x00 0x1c000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x00 0x00 0x00100000 0x1c000>;
+
+		serdes_ln_ctrl: serdes-ln-ctrl@4080 {
+			compatible = "mmio-mux";
+			#mux-control-cells = <1>;
+			mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
+					<0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
+		};
+	};
+
 	gic500: interrupt-controller@1800000 {
 		compatible = "arm,gic-v3";
 		#address-cells = <2>;
-- 
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH v4 3/6] arm64: dts: ti: k3-j7200-main.dtsi: Add USB to SERDES lane MUX

[Roger Quadros]

The USB controller can be connected to one of the 2 lanes
of SERDES0 using a MUX. Add a MUX controller node for that.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index d6d688efc32a..42f66b8dffa7 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -31,6 +31,12 @@
 			mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
 					<0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
 		};
+
+		usb_serdes_mux: mux-controller@4000 {
+			compatible = "mmio-mux";
+			#mux-control-cells = <1>;
+			mux-reg-masks = <0x4000 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
+		};
 	};
 
 	gic500: interrupt-controller@1800000 {
-- 
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH v4 4/6] arm64: dts: ti: k3-j7200-main: Add USB controller

[Roger Quadros]

j7200 has on USB controller instance. Add that.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 30 +++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 42f66b8dffa7..519e6f718363 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -331,4 +331,34 @@
 		no-1-8-v;
 		dma-coherent;
 	};
+
+	usbss0: cdns-usb@4104000 {
+		compatible = "ti,j721e-usb";
+		reg = <0x00 0x4104000 0x00 0x100>;
+		dma-coherent;
+		power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 288 12>, <&k3_clks 288 3>;
+		clock-names = "ref", "lpm";
+		assigned-clocks = <&k3_clks 288 12>;	/* USB2_REFCLK */
+		assigned-clock-parents = <&k3_clks 288 13>; /* HFOSC0 */
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		usb0: usb@6000000 {
+			compatible = "cdns,usb3";
+			reg = <0x00 0x6000000 0x00 0x10000>,
+			      <0x00 0x6010000 0x00 0x10000>,
+			      <0x00 0x6020000 0x00 0x10000>;
+			reg-names = "otg", "xhci", "dev";
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,	/* irq.0 */
+				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,	/* irq.6 */
+				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;	/* otgirq.0 */
+			interrupt-names = "host",
+					  "peripheral",
+					  "otg";
+			maximum-speed = "super-speed";
+			dr_mode = "otg";
+		};
+	};
 };
-- 
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH v4 5/6] arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function

[Roger Quadros]

From: Kishon Vijay Abraham I <kishon@ti.com>

First two lanes of SERDES is connected to PCIe, third lane is
connected to QSGMII and the last lane is connected to USB. However,
Cadence torrent SERDES doesn't support more than 2 protocols
at the same time. Configure it only for PCIe and QSGMII.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 8e534ef8a3f5..6ab9d5d33a72 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include "k3-j7200-som-p0.dtsi"
+#include <dt-bindings/mux/ti-serdes.h>
 
 / {
 	chosen {
@@ -139,3 +140,8 @@
 	ti,driver-strength-ohm = <50>;
 	disable-wp;
 };
+
+&serdes_ln_ctrl {
+	idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
+		      <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
+};
-- 
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

[PATCH v4 6/6] arm64: dts: ti: k3-j7200-common-proc-board: Add USB support

[Roger Quadros]

The board uses lane 3 of SERDES for USB. Set the mux
accordingly.

The USB controller and EVM supports super-speed for USB0
on the Type-C port. However, the SERDES has a limitation
that upto 2 protocols can be used at a time. The SERDES is
wired for PCIe, QSGMII and USB super-speed. It has been
chosen to use PCI2 and QSGMII as default. So restrict
USB0 to high-speed mode.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 .../dts/ti/k3-j7200-common-proc-board.dts     | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 6ab9d5d33a72..5c945f4ffec1 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -42,6 +42,12 @@
 			J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
 		>;
 	};
+
+	main_usbss0_pins_default: main-usbss0-pins-default {
+		pinctrl-single,pins = <
+			J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
+		>;
+	};
 };
 
 &wkup_uart0 {
@@ -145,3 +151,19 @@
 	idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
 		      <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
 };
+
+&usb_serdes_mux {
+	idle-states = <1>; /* USB0 to SERDES lane 3 */
+};
+
+&usbss0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_usbss0_pins_default>;
+	ti,vbus-divider;
+	ti,usb2-only;
+};
+
+&usb0 {
+	dr_mode = "otg";
+	maximum-speed = "high-speed";
+};
-- 
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

Re: [PATCH v4 0/6] arm64: dts: ti: Add USB support for J7200 EVM

[Vignesh Raghavendra]

On 9/21/20 8:09 PM, Roger Quadros wrote:
> Hi Tero/Nishanth,
> 
> This series adds USB2.0 support for the J7200 EVM.

[...]


> Kishon Vijay Abraham I (1):
>   arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane
>     function
> 
> Roger Quadros (5):
>   dt-bindings: ti-serdes-mux: Add defines for J7200 SoC
>   arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux
>   arm64: dts: ti: k3-j7200-main.dtsi: Add USB to SERDES lane MUX
>   arm64: dts: ti: k3-j7200-main: Add USB controller
>   arm64: dts: ti: k3-j7200-common-proc-board: Add USB support
> 
>  .../dts/ti/k3-j7200-common-proc-board.dts     | 28 ++++++++++
>  arch/arm64/boot/dts/ti/k3-j7200-main.dtsi     | 51 +++++++++++++++++++
>  include/dt-bindings/mux/ti-serdes.h           | 22 ++++++++
>  3 files changed, 101 insertions(+)
> 

For the series:

Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>

Re: [PATCH v4 1/6] dt-bindings: ti-serdes-mux: Add defines for J7200 SoC

[Nishanth Menon]

On 17:39-20200921, Roger Quadros wrote:
> There are 4 lanes in each J7200 SERDES. Each SERDES lane mux can
> select upto 4 different IPs. Define all the possible functions.
> 
> Cc: Peter Rosin <peda@axentia.se>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---
>  include/dt-bindings/mux/ti-serdes.h | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h
> index 146d0685a925..9047ec6bd3cf 100644
> --- a/include/dt-bindings/mux/ti-serdes.h
> +++ b/include/dt-bindings/mux/ti-serdes.h
> @@ -68,4 +68,26 @@
>  #define J721E_SERDES4_LANE3_QSGMII_LANE8	0x2
>  #define J721E_SERDES4_LANE3_IP4_UNUSED		0x3
>  
> +/* J7200 */
> +
> +#define J7200_SERDES0_LANE0_QSGMII_LANE3	0x0
> +#define J7200_SERDES0_LANE0_PCIE1_LANE0		0x1
> +#define J7200_SERDES0_LANE0_IP3_UNUSED		0x2
> +#define J7200_SERDES0_LANE0_IP4_UNUSED		0x3
> +
> +#define J7200_SERDES0_LANE1_QSGMII_LANE4	0x0
> +#define J7200_SERDES0_LANE1_PCIE1_LANE1		0x1
> +#define J7200_SERDES0_LANE1_IP3_UNUSED		0x2
> +#define J7200_SERDES0_LANE1_IP4_UNUSED		0x3
> +
> +#define J7200_SERDES0_LANE2_QSGMII_LANE1	0x0
> +#define J7200_SERDES0_LANE2_PCIE1_LANE2		0x1
> +#define J7200_SERDES0_LANE2_IP3_UNUSED		0x2
> +#define J7200_SERDES0_LANE2_IP4_UNUSED		0x3
> +
> +#define J7200_SERDES0_LANE3_QSGMII_LANE2	0x0
> +#define J7200_SERDES0_LANE3_PCIE1_LANE3		0x1
> +#define J7200_SERDES0_LANE3_USB			0x2
> +#define J7200_SERDES0_LANE3_IP4_UNUSED		0x3
> +
>  #endif /* _DT_BINDINGS_MUX_TI_SERDES */
> -- 
> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
> Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
> 

I recommend Peter's ack before we take this series in.

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH v4 1/6] dt-bindings: ti-serdes-mux: Add defines for J7200 SoC

[Rob Herring]

On Mon, 21 Sep 2020 17:39:36 +0300, Roger Quadros wrote:
> There are 4 lanes in each J7200 SERDES. Each SERDES lane mux can
> select upto 4 different IPs. Define all the possible functions.
> 
> Cc: Peter Rosin <peda@axentia.se>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---
>  include/dt-bindings/mux/ti-serdes.h | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v4 1/6] dt-bindings: ti-serdes-mux: Add defines for J7200 SoC

[Peter Rosin]

Hi!

On 2020-09-21 16:39, Roger Quadros wrote:
> There are 4 lanes in each J7200 SERDES. Each SERDES lane mux can
> select upto 4 different IPs. Define all the possible functions.
> 
> Cc: Peter Rosin <peda@axentia.se>
> Signed-off-by: Roger Quadros <rogerq@ti.com>

Acked-by: Peter Rosin <peda@axentia.se>

Thanks for taking care of this!

Cheers,
Peter

> ---
>  include/dt-bindings/mux/ti-serdes.h | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h
> index 146d0685a925..9047ec6bd3cf 100644
> --- a/include/dt-bindings/mux/ti-serdes.h
> +++ b/include/dt-bindings/mux/ti-serdes.h
> @@ -68,4 +68,26 @@
>  #define J721E_SERDES4_LANE3_QSGMII_LANE8	0x2
>  #define J721E_SERDES4_LANE3_IP4_UNUSED		0x3
>  
> +/* J7200 */
> +
> +#define J7200_SERDES0_LANE0_QSGMII_LANE3	0x0
> +#define J7200_SERDES0_LANE0_PCIE1_LANE0		0x1
> +#define J7200_SERDES0_LANE0_IP3_UNUSED		0x2
> +#define J7200_SERDES0_LANE0_IP4_UNUSED		0x3
> +
> +#define J7200_SERDES0_LANE1_QSGMII_LANE4	0x0
> +#define J7200_SERDES0_LANE1_PCIE1_LANE1		0x1
> +#define J7200_SERDES0_LANE1_IP3_UNUSED		0x2
> +#define J7200_SERDES0_LANE1_IP4_UNUSED		0x3
> +
> +#define J7200_SERDES0_LANE2_QSGMII_LANE1	0x0
> +#define J7200_SERDES0_LANE2_PCIE1_LANE2		0x1
> +#define J7200_SERDES0_LANE2_IP3_UNUSED		0x2
> +#define J7200_SERDES0_LANE2_IP4_UNUSED		0x3
> +
> +#define J7200_SERDES0_LANE3_QSGMII_LANE2	0x0
> +#define J7200_SERDES0_LANE3_PCIE1_LANE3		0x1
> +#define J7200_SERDES0_LANE3_USB			0x2
> +#define J7200_SERDES0_LANE3_IP4_UNUSED		0x3
> +
>  #endif /* _DT_BINDINGS_MUX_TI_SERDES */
> 

Re: [PATCH v4 0/6] arm64: dts: ti: Add USB support for J7200 EVM

[Nishanth Menon]

On 17:39-20200921, Roger Quadros wrote:
> Hi Tero/Nishanth,
> 
> This series adds USB2.0 support for the J7200 EVM.
> 
> Series is based on top of:
> 
>     Faiz's MMC/SD support series
>     https://lore.kernel.org/lkml/20200907090520.25313-1-faiz_abbas@ti.com/
>     Lokesh's initial support series
>     https://patchwork.kernel.org/cover/11740039/
>     Vignesh's I2C support series
>     https://lore.kernel.org/patchwork/cover/1282152/
>     Vignesh's Hyperflash series
>     https://lore.kernel.org/patchwork/cover/1285326/
>     MUX binding cleanup
>     https://lore.kernel.org/lkml/20200918165930.2031-1-rogerq@ti.com/
> 
> cheers,
> -roger


Your series does'nt apply on my tree anymore - even after merging
ti-k3-dt-fixes-for-v5.9 . Could you rebase your patches on top of
next-20200930 ?
-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D