Re: [PATCH 1/1] perf tools: Add missing user space support for config1/config2

From: Peter Zijlstra <peterz@infradead.org>
To: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@elte.hu>,
	Arnaldo Carvalho de Melo <acme@infradead.org>,
	linux-kernel@vger.kernel.org,
	Stephane Eranian <eranian@gmail.com>,
	Lin Ming <ming.m.lin@intel.com>,
	Arnaldo Carvalho de Melo <acme@redhat.com>,
	Thomas Gleixner <tglx@linutronix.de>
Subject: Re: [PATCH 1/1] perf tools: Add missing user space support for config1/config2
Date: Sat, 23 Apr 2011 09:50:07 +0200	[thread overview]
Message-ID: <1303545007.2298.43.camel@twins> (raw)
In-Reply-To: <20110423000010.GB9328@tassilo.jf.intel.com>

On Fri, 2011-04-22 at 17:00 -0700, Andi Kleen wrote:
> On Sat, Apr 23, 2011 at 12:57:42AM +0200, Peter Zijlstra wrote:
> > On Fri, 2011-04-22 at 23:54 +0200, Peter Zijlstra wrote:
> > > On Fri, 2011-04-22 at 23:37 +0200, Peter Zijlstra wrote:
> > > > The below needs filling out for !x86 (which I filled out with
> > > > unsupported events) and x86 needs the offcore bits fixed to auto select
> > > > between the two offcore events.
> > > 
> > > Urgh, so SNB has different MSR_OFFCORE_RESPONSE bits and needs another table.
> > 
> > Also, NHM offcore bits were wrong... it implemented _ACCESS as _HIT and
> 
> What is ACCESS if not a HIT?

An ACCESS is all requests for data that comes in, after which you either
HIT or MISS in which case you have to ask someone else down the line.

> > counted OTHER_CORE_HIT* as MISS even though its clearly documented as an
> > L3 hit.
> 
> When the other core owns the cache line it has to be fetched from there.
> That's not a LLC hit.

Then _why_ are they described in 30.6.1.3, table 30-15, as:

OTHER_CORE_HIT_SNP	 9	(R/W). L3 Hit: ....
OTHER_CORE_HITM		10	(R/W). L3 Hit: ...