From: Jiang Liu <liuj97@gmail.com>
To: Bjorn Helgaas <bhelgaas@google.com>, Don Dutile <ddutile@redhat.com>
Cc: Jiang Liu <jiang.liu@huawei.com>, Yinghai Lu <yinghai@kernel.org>,
Taku Izumi <izumi.taku@jp.fujitsu.com>,
"Rafael J . Wysocki" <rjw@sisk.pl>,
Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>,
Yijing Wang <wangyijing@huawei.com>,
Keping Chen <chenkeping@huawei.com>,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
Jiang Liu <liuj97@gmail.com>
Subject: [RFC PATCH 14/14] qib/PCI: use PCIe cap access functions to simplify implementation
Date: Tue, 10 Jul 2012 23:54:15 +0800 [thread overview]
Message-ID: <1341935655-5381-15-git-send-email-jiang.liu@huawei.com> (raw)
In-Reply-To: <1341935655-5381-1-git-send-email-jiang.liu@huawei.com>
In-Reply-To: <CAErSpo70NtEJFaQmDtdTLkSB3fQRNy78juAQO-KbXeceZkunkw@mail.gmail.com>
From: Jiang Liu <jiang.liu@huawei.com>
Use PCIe cap access functions to simplify qib implementation.
Signed-off-by: Jiang Liu <liuj97@gmail.com>
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
---
drivers/infiniband/hw/qib/qib_pcie.c | 34 ++++++++++++++--------------------
1 file changed, 14 insertions(+), 20 deletions(-)
diff --git a/drivers/infiniband/hw/qib/qib_pcie.c b/drivers/infiniband/hw/qib/qib_pcie.c
index 790646e..3c30249 100644
--- a/drivers/infiniband/hw/qib/qib_pcie.c
+++ b/drivers/infiniband/hw/qib/qib_pcie.c
@@ -271,10 +271,9 @@ int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent,
struct qib_msix_entry *entry)
{
u16 linkstat, speed;
- int pos = 0, pose, ret = 1;
+ int pos = 0, ret = 1;
- pose = pci_pcie_cap(dd->pcidev);
- if (!pose) {
+ if (!pci_is_pcie(dd->pcidev)) {
qib_dev_err(dd, "Can't find PCI Express capability!\n");
/* set up something... */
dd->lbus_width = 1;
@@ -296,7 +295,7 @@ int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent,
if (!pos)
qib_enable_intx(dd->pcidev);
- pci_read_config_word(dd->pcidev, pose + PCI_EXP_LNKSTA, &linkstat);
+ pci_pcie_cap_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat);
/*
* speed is bits 0-3, linkwidth is bits 4-8
* no defines for them in headers
@@ -514,7 +513,6 @@ static int qib_tune_pcie_coalesce(struct qib_devdata *dd)
{
int r;
struct pci_dev *parent;
- int ppos;
u16 devid;
u32 mask, bits, val;
@@ -527,8 +525,7 @@ static int qib_tune_pcie_coalesce(struct qib_devdata *dd)
qib_devinfo(dd->pcidev, "Parent not root\n");
return 1;
}
- ppos = pci_pcie_cap(parent);
- if (!ppos)
+ if (!pci_is_pcie(parent))
return 1;
if (parent->vendor != 0x8086)
return 1;
@@ -585,7 +582,6 @@ static int qib_tune_pcie_caps(struct qib_devdata *dd)
{
int ret = 1; /* Assume the worst */
struct pci_dev *parent;
- int ppos, epos;
u16 pcaps, pctl, ecaps, ectl;
int rc_sup, ep_sup;
int rc_cur, ep_cur;
@@ -596,17 +592,15 @@ static int qib_tune_pcie_caps(struct qib_devdata *dd)
qib_devinfo(dd->pcidev, "Parent not root\n");
goto bail;
}
- ppos = pci_pcie_cap(parent);
- if (ppos) {
- pci_read_config_word(parent, ppos + PCI_EXP_DEVCAP, &pcaps);
- pci_read_config_word(parent, ppos + PCI_EXP_DEVCTL, &pctl);
+ if (pci_is_pcie(parent)) {
+ pci_pcie_cap_read_word(parent, PCI_EXP_DEVCAP, &pcaps);
+ pci_pcie_cap_read_word(parent, PCI_EXP_DEVCTL, &pctl);
} else
goto bail;
/* Find out supported and configured values for endpoint (us) */
- epos = pci_pcie_cap(dd->pcidev);
- if (epos) {
- pci_read_config_word(dd->pcidev, epos + PCI_EXP_DEVCAP, &ecaps);
- pci_read_config_word(dd->pcidev, epos + PCI_EXP_DEVCTL, &ectl);
+ if (pci_is_pcie(dd->pcidev)) {
+ pci_pcie_cap_read_word(dd->pcidev, PCI_EXP_DEVCAP, &ecaps);
+ pci_pcie_cap_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl);
} else
goto bail;
ret = 0;
@@ -627,14 +621,14 @@ static int qib_tune_pcie_caps(struct qib_devdata *dd)
rc_cur = rc_sup;
pctl = (pctl & ~PCI_EXP_DEVCTL_PAYLOAD) |
val2fld(rc_cur, PCI_EXP_DEVCTL_PAYLOAD);
- pci_write_config_word(parent, ppos + PCI_EXP_DEVCTL, pctl);
+ pci_pcie_cap_write_word(parent, PCI_EXP_DEVCTL, pctl);
}
/* If less than (allowed, supported), bump endpoint payload */
if (rc_sup > ep_cur) {
ep_cur = rc_sup;
ectl = (ectl & ~PCI_EXP_DEVCTL_PAYLOAD) |
val2fld(ep_cur, PCI_EXP_DEVCTL_PAYLOAD);
- pci_write_config_word(dd->pcidev, epos + PCI_EXP_DEVCTL, ectl);
+ pci_pcie_cap_write_word(dd->pcidev, PCI_EXP_DEVCTL, ectl);
}
/*
@@ -652,13 +646,13 @@ static int qib_tune_pcie_caps(struct qib_devdata *dd)
rc_cur = rc_sup;
pctl = (pctl & ~PCI_EXP_DEVCTL_READRQ) |
val2fld(rc_cur, PCI_EXP_DEVCTL_READRQ);
- pci_write_config_word(parent, ppos + PCI_EXP_DEVCTL, pctl);
+ pci_pcie_cap_write_word(parent, PCI_EXP_DEVCTL, pctl);
}
if (rc_sup > ep_cur) {
ep_cur = rc_sup;
ectl = (ectl & ~PCI_EXP_DEVCTL_READRQ) |
val2fld(ep_cur, PCI_EXP_DEVCTL_READRQ);
- pci_write_config_word(dd->pcidev, epos + PCI_EXP_DEVCTL, ectl);
+ pci_pcie_cap_write_word(dd->pcidev, PCI_EXP_DEVCTL, ectl);
}
bail:
return ret;
--
1.7.9.5
next prev parent reply other threads:[~2012-07-10 15:57 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-06-04 7:44 [Resend with Ack][PATCH v1] PCI: allow acpiphp to handle PCIe ports without native PCIe hotplug capability Jiang Liu
2012-06-04 8:23 ` Kenji Kaneshige
2012-07-03 4:16 ` Bjorn Helgaas
2012-07-03 15:59 ` Bjorn Helgaas
2012-07-03 19:50 ` Don Dutile
2012-07-04 18:07 ` Bjorn Helgaas
2012-07-09 10:05 ` Jiang Liu
2012-07-09 17:05 ` Bjorn Helgaas
2012-07-04 2:52 ` Jiang Liu
2012-07-10 15:54 ` [RFC PATCH 00/14] improve PCIe capabilities registers handling Jiang Liu
2012-07-10 18:44 ` Bjorn Helgaas
2012-07-10 15:54 ` [RFC PATCH 01/14] PCI: add pcie_flags into struct pci_dev to cache PCIe capabilities register Jiang Liu
2012-07-11 9:01 ` Taku Izumi
2012-07-11 14:27 ` Jiang Liu
2012-07-10 15:54 ` [RFC PATCH 02/14] PCI: introduce pci_pcie_type(dev) to replace pci_dev->pcie_type Jiang Liu
2012-07-10 15:54 ` [RFC PATCH 03/14] PCI: remove unused field pcie_type from struct pci_dev Jiang Liu
2012-07-10 15:54 ` [RFC PATCH 04/14] PCI: refine and move pcie_cap_has_*() macros to include/linux/pci.h Jiang Liu
2012-07-10 18:49 ` Bjorn Helgaas
2012-07-10 15:54 ` [RFC PATCH 05/14] PCI: add access functions for PCIe capabilities to hide PCIe spec differences Jiang Liu
2012-07-10 18:35 ` Bjorn Helgaas
2012-07-11 3:07 ` Jiang Liu
2012-07-11 3:40 ` Bjorn Helgaas
2012-07-11 6:40 ` Jiang Liu
2012-07-11 17:52 ` Bjorn Helgaas
2012-07-12 2:56 ` Jiang Liu
2012-07-12 20:49 ` Bjorn Helgaas
2012-07-15 16:47 ` Jiang Liu
2012-07-16 17:29 ` Bjorn Helgaas
2012-07-16 18:57 ` Don Dutile
2012-07-17 0:09 ` Jiang Liu
2012-07-17 0:14 ` Bjorn Helgaas
2012-07-10 15:54 ` [RFC PATCH 06/14] PCI: use PCIe cap access functions to simplify PCI core implementation Jiang Liu
2012-07-10 18:35 ` Bjorn Helgaas
2012-07-11 2:49 ` Jiang Liu
2012-07-10 15:54 ` [RFC PATCH 07/14] hotplug/PCI: use PCIe cap access functions to simplify implementation Jiang Liu
2012-07-10 18:35 ` Bjorn Helgaas
2012-07-10 15:54 ` [RFC PATCH 08/14] portdrv/PCI: " Jiang Liu
2012-07-10 15:54 ` [RFC PATCH 09/14] pciehp/PCI: " Jiang Liu
2012-07-10 15:54 ` [RFC PATCH 10/14] PME/PCI: " Jiang Liu
2012-07-10 15:54 ` [RFC PATCH 11/14] AER/PCI: " Jiang Liu
2012-07-10 15:54 ` [RFC PATCH 12/14] ASPM/PCI: " Jiang Liu
2012-07-10 15:54 ` [RFC PATCH 13/14] r8169/PCI: " Jiang Liu
2012-07-10 15:54 ` Jiang Liu [this message]
2012-08-15 19:12 ` [Resend with Ack][PATCH v1] PCI: allow acpiphp to handle PCIe ports without native PCIe hotplug capability Bjorn Helgaas
2012-08-16 15:15 ` Jiang Liu
2012-08-22 15:16 ` [PATCH v2] PCI: allow acpiphp to handle PCIe ports w/o " Jiang Liu
2012-09-24 22:10 ` Bjorn Helgaas
2012-09-25 15:16 ` Jiang Liu
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