From: Huacai Chen <chenhuacai@gmail.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org,
Fuxin Zhang <zhangfx@lemote.com>,
Zhangjin Wu <wuzhangjin@gmail.com>,
Huacai Chen <chenhc@lemote.com>, Hongliang Tao <taohl@lemote.com>,
Hua Yan <yanh@lemote.com>
Subject: [PATCH V5 01/18] MIPS: Loongson: Add basic Loongson-3 definition.
Date: Sat, 11 Aug 2012 17:32:06 +0800 [thread overview]
Message-ID: <1344677543-22591-2-git-send-email-chenhc@lemote.com> (raw)
In-Reply-To: <1344677543-22591-1-git-send-email-chenhc@lemote.com>
Loongson-3 is a multi-core MIPS family CPU, it support MIPS64R2
fully. Loongson-3 has the same IMP field (0x6300) as Loongson-2.
Loongson-3 has a hardware-maintained cache, system software doesn't
need to maintain coherency.
Loongson-3A is the first revision of Loongson-3, and it is the quad-
core version of Loongson-2G. Loongson-3A has a simplified version named
Loongson-2Gq, the main difference between Loongson-3A/2Gq is 3A has two
HyperTransport controller but 2Gq has only one. HT0 is used for cross-
chip interconnection and HT1 is used to link PCI bus. Therefore, 2Gq
cannot support NUMA but 3A can. For software, Loongson-2Gq is simply
identified as Loongson-3A.
Exsisting Loongson family CPUs:
Loongson-1: Loongson-1A, Loongson-1B, they are 32-bit MIPS CPUs.
Loongson-2: Loongson-2E, Loongson-2F, Loongson-2G, they are 64-bit
single-core MIPS CPUs.
Loongson-3: Loongson-3A(including so-called Loongson-2Gq), they are
64-bit multi-core MIPS CPUs.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Hongliang Tao <taohl@lemote.com>
Signed-off-by: Hua Yan <yanh@lemote.com>
---
arch/mips/include/asm/addrspace.h | 6 ++++++
arch/mips/include/asm/cpu.h | 6 ++++--
arch/mips/include/asm/mach-loongson/spaces.h | 15 +++++++++++++++
arch/mips/include/asm/module.h | 2 ++
arch/mips/include/asm/pgtable-bits.h | 7 +++++++
arch/mips/loongson/Platform | 1 +
6 files changed, 35 insertions(+), 2 deletions(-)
create mode 100644 arch/mips/include/asm/mach-loongson/spaces.h
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
index 569f80a..cf62bfb 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -116,7 +116,13 @@
#define K_CALG_UNCACHED 2
#define K_CALG_NONCOHERENT 3
#define K_CALG_COH_EXCL 4
+
+#ifdef CONFIG_CPU_LOONGSON3
+#define K_CALG_COH_SHAREABLE 3
+#else
#define K_CALG_COH_SHAREABLE 5
+#endif
+
#define K_CALG_NOTUSED 6
#define K_CALG_UNCACHED_ACCEL 7
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index f21b7c0..75b6127 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -72,6 +72,7 @@
#define PRID_IMP_R5432 0x5400
#define PRID_IMP_R5500 0x5500
#define PRID_IMP_LOONGSON2 0x6300
+#define PRID_IMP_LOONGSON3 0x6300
#define PRID_IMP_UNKNOWN 0xff00
@@ -200,6 +201,7 @@
#define PRID_REV_LOONGSON1B 0x0020
#define PRID_REV_LOONGSON2E 0x0002
#define PRID_REV_LOONGSON2F 0x0003
+#define PRID_REV_LOONGSON3A 0x0005
/*
* Older processors used to encode processor version and revision in two
@@ -268,8 +270,8 @@ enum cpu_type_enum {
* MIPS64 class processors
*/
CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
- CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
- CPU_XLR, CPU_XLP,
+ CPU_LOONGSON3, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
+ CPU_CAVIUM_OCTEON2, CPU_XLR, CPU_XLP,
CPU_LAST
};
diff --git a/arch/mips/include/asm/mach-loongson/spaces.h b/arch/mips/include/asm/mach-loongson/spaces.h
new file mode 100644
index 0000000..1e82804
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson/spaces.h
@@ -0,0 +1,15 @@
+#ifndef __ASM_MACH_LOONGSON_SPACES_H_
+#define __ASM_MACH_LOONGSON_SPACES_H_
+
+#ifndef CAC_BASE
+#if defined(CONFIG_64BIT)
+#if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_CPU_LOONGSON3)
+#define CAC_BASE _AC(0x9800000000000000, UL)
+#else
+#define CAC_BASE _AC(0xa800000000000000, UL)
+#endif /* CONFIG_DMA_NONCOHERENT || CONFIG_CPU_LOONGSON3 */
+#endif /* CONFIG_64BIT */
+#endif /* CONFIG_CAC_BASE */
+
+#include <asm/mach-generic/spaces.h>
+#endif
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index dca8bce..523600f 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -122,6 +122,8 @@ search_module_dbetables(unsigned long addr)
#define MODULE_PROC_FAMILY "LOONGSON1 "
#elif defined CONFIG_CPU_LOONGSON2
#define MODULE_PROC_FAMILY "LOONGSON2 "
+#elif defined CONFIG_CPU_LOONGSON3
+#define MODULE_PROC_FAMILY "LOONGSON3 "
#elif defined CONFIG_CPU_CAVIUM_OCTEON
#define MODULE_PROC_FAMILY "OCTEON "
#elif defined CONFIG_CPU_XLR
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index e9fe7e9..1afd39a 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -206,6 +206,13 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
#define _CACHE_UNCACHED _CACHE_UC_B
#define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB
+#elif defined(CONFIG_CPU_LOONGSON3)
+
+#define _CACHE_UNCACHED (2<<_CACHE_SHIFT) /* LOONGSON */
+#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */
+#define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */
+#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) /* LOONGSON */
+
#else
#define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT) /* R4600 only */
diff --git a/arch/mips/loongson/Platform b/arch/mips/loongson/Platform
index 29692e5..6205372 100644
--- a/arch/mips/loongson/Platform
+++ b/arch/mips/loongson/Platform
@@ -30,3 +30,4 @@ platform-$(CONFIG_MACH_LOONGSON) += loongson/
cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson -mno-branch-likely
load-$(CONFIG_LEMOTE_FULOONG2E) += 0xffffffff80100000
load-$(CONFIG_LEMOTE_MACH2F) += 0xffffffff80200000
+load-$(CONFIG_CPU_LOONGSON3) += 0xffffffff80200000
--
1.7.7.3
next prev parent reply other threads:[~2012-08-11 9:33 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-08-11 9:32 [PATCH V5 00/16] MIPS: Add Loongson-3 based machines support Huacai Chen
2012-08-11 9:32 ` Huacai Chen [this message]
2012-08-11 9:32 ` [PATCH V5 02/18] MIPS: Loongson: Add basic Loongson-3 CPU support Huacai Chen
2012-08-11 9:32 ` [PATCH V5 03/18] MIPS: Loongson 3: Add Lemote-3A machtypes definition Huacai Chen
2012-08-11 9:32 ` [PATCH V5 04/18] MIPS: Loongson: Make Loongson-3 to use BCD format for RTC Huacai Chen
2012-08-11 9:32 ` [PATCH V5 05/18] MIPS: Loongson: Add UEFI-like firmware interface support Huacai Chen
2012-08-11 9:32 ` [PATCH V5 06/18] MIPS: Loongson 3: Add HT-linked PCI support Huacai Chen
2012-08-11 9:32 ` [PATCH V5 07/18] MIPS: Loongson 3: Add IRQ init and dispatch support Huacai Chen
2012-08-11 9:32 ` [PATCH V5 08/18] MIPS: Loongson 3: Add serial port support Huacai Chen
2012-08-11 9:32 ` [PATCH V5 09/18] MIPS: Loongson: Add swiotlb to support big memory (>4GB) Huacai Chen
2012-08-13 17:54 ` Konrad Rzeszutek Wilk
2012-08-14 2:29 ` Huacai Chen
2012-08-14 5:57 ` Huacai Chen
2012-08-14 16:26 ` David Daney
2012-08-15 2:18 ` Huacai Chen
2012-08-15 20:24 ` Ralf Baechle
2012-08-16 3:19 ` Huacai Chen
2012-08-11 9:32 ` [PATCH V5 10/18] MIPS: Loongson: Add Loongson-3 Kconfig options Huacai Chen
2012-08-11 9:32 ` [PATCH V5 11/18] drm/radeon: Include swiotlb.h if SWIOTLB configured Huacai Chen
2012-08-11 9:32 ` [PATCH V5 12/18] drm: Handle io prot correctly for MIPS Huacai Chen
2012-08-11 9:32 ` [PATCH V5 13/18] drm: Define SAREA_MAX for Loongson (PageSize = 16KB) Huacai Chen
2012-08-15 21:31 ` Ralf Baechle
2012-08-16 0:43 ` Huacai Chen
2012-08-16 1:58 ` Matt Turner
2012-08-16 3:20 ` Huacai Chen
2012-08-11 9:32 ` [PATCH V5 14/18] ALSA: HDA: Make hda sound card usable for Loongson Huacai Chen
2012-08-13 8:00 ` [alsa-devel] " Takashi Iwai
2012-08-13 8:22 ` Huacai Chen
2012-08-11 9:32 ` [PATCH V5 15/18] MIPS: Loongson 3: Add Loongson-3 SMP support Huacai Chen
2012-08-11 9:32 ` [PATCH V5 16/18] MIPS: Loongson 3: Add CPU hotplug support Huacai Chen
2012-08-11 9:32 ` [PATCH V5 17/18] MIPS: Fix poweroff failure when HOTPLUG_CPU configured Huacai Chen
2012-08-11 9:32 ` [PATCH V5 18/18] MIPS: Loongson: Add a Loongson-3 default config file Huacai Chen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1344677543-22591-2-git-send-email-chenhc@lemote.com \
--to=chenhuacai@gmail.com \
--cc=chenhc@lemote.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mips@linux-mips.org \
--cc=ralf@linux-mips.org \
--cc=taohl@lemote.com \
--cc=wuzhangjin@gmail.com \
--cc=yanh@lemote.com \
--cc=zhangfx@lemote.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).