* [PATCH v5 1/4] mfd: add syscon driver based on regmap
2012-09-04 3:20 [PATCH v5 0/4] add syscon driver based on regmap for general registers access Dong Aisheng
@ 2012-09-04 3:20 ` Dong Aisheng
2012-09-04 11:35 ` Andi Shyti
2012-09-04 3:20 ` [PATCH v5 2/4] ARM: imx6q: add iomuxc gpr support into syscon Dong Aisheng
` (2 subsequent siblings)
3 siblings, 1 reply; 11+ messages in thread
From: Dong Aisheng @ 2012-09-04 3:20 UTC (permalink / raw)
To: linux-kernel
Cc: linux-arm-kernel, linus.walleij, s.hauer, shawn.guo, kernel,
grant.likely, rob.herring, sameo, lrg, broonie, richard.zhao,
devicetree-discuss, swarren
From: Dong Aisheng <dong.aisheng@linaro.org>
Add regmap based syscon driver.
This is usually used for access misc bits in registers which does not belong
to a specific module, for example, IMX IOMUXC GPR and ANATOP.
With this driver, client can use generic regmap API to access registers
which are registered into syscon.
Reviewed-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
---
ChangeLog:
v4->v5:
* depends on OF
* do not call of_node_put in syscon_node_to_regmap
v3->v4:
* add more description about syscon(provided by Stephen Warren) in binding doc.
* fix a minor code indent error and remove set cache type code since the cache
is disabled by default.
v2->v3:
* export regmap lookup APIs including syscon_node_to_regmap
* fix a few typo
v1->v2:
* provide a way of retrieving the regmap, suggested by Mark Brown.
* delete imx-syscon io accessors and using generic regmap API for client drivers.
* change to a more generic name for other SoCs to use.
---
Documentation/devicetree/bindings/mfd/syscon.txt | 20 +++
drivers/mfd/Kconfig | 8 +
drivers/mfd/Makefile | 1 +
drivers/mfd/syscon.c | 176 ++++++++++++++++++++++
include/linux/mfd/syscon.h | 23 +++
5 files changed, 228 insertions(+), 0 deletions(-)
diff --git a/Documentation/devicetree/bindings/mfd/syscon.txt b/Documentation/devicetree/bindings/mfd/syscon.txt
new file mode 100644
index 0000000..fe8150b
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/syscon.txt
@@ -0,0 +1,20 @@
+* System Controller Registers R/W driver
+
+System controller node represents a register region containing a set
+of miscellaneous registers. The registers are not cohesive enough to
+represent as any specific type of device. The typical use-case is for
+some other node's driver, or platform-specific code, to acquire a
+reference to the syscon node (e.g. by phandle, node path, or search
+using a specific compatible value), interrogate the node (or associated
+OS driver) to determine the location of the registers, and access the
+registers directly.
+
+Required properties:
+- compatible: Should contain "syscon".
+- reg: the register region can be accessed from syscon
+
+Examples:
+gpr: iomuxc-gpr@020e0000 {
+ compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
+ reg = <0x020e0000 0x38>;
+};
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index b1a1462..82247b7 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -993,6 +993,14 @@ config MFD_ANATOP
MFD controller. This controller embeds regulator and
thermal devices for Freescale i.MX platforms.
+config MFD_SYSCON
+ bool "System Controller Register R/W Based on Regmap"
+ depends on OF
+ select REGMAP_MMIO
+ help
+ Select this option to enable accessing system control registers
+ via regmap.
+
config MFD_PALMAS
bool "Support for the TI Palmas series chips"
select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 79dd22d..8384bc9 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -131,4 +131,5 @@ obj-$(CONFIG_MFD_PALMAS) += palmas.o
obj-$(CONFIG_MFD_RC5T583) += rc5t583.o rc5t583-irq.o
obj-$(CONFIG_MFD_SEC_CORE) += sec-core.o sec-irq.o
obj-$(CONFIG_MFD_ANATOP) += anatop-mfd.o
+obj-$(CONFIG_MFD_SYSCON) += syscon.o
obj-$(CONFIG_MFD_LM3533) += lm3533-core.o lm3533-ctrlbank.o
diff --git a/drivers/mfd/syscon.c b/drivers/mfd/syscon.c
new file mode 100644
index 0000000..661a7dc
--- /dev/null
+++ b/drivers/mfd/syscon.c
@@ -0,0 +1,176 @@
+/*
+ * System Control Driver
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * Author: Dong Aisheng <dong.aisheng@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+static struct platform_driver syscon_driver;
+
+struct syscon {
+ struct device *dev;
+ void __iomem *base;
+ struct regmap *regmap;
+};
+
+static int syscon_match(struct device *dev, void *data)
+{
+ struct syscon *syscon = dev_get_drvdata(dev);
+ struct device_node *dn = data;
+
+ return (syscon->dev->of_node == dn) ? 1 : 0;
+}
+
+struct regmap *syscon_node_to_regmap(struct device_node *np)
+{
+ struct syscon *syscon;
+ struct device *dev;
+
+ dev = driver_find_device(&syscon_driver.driver, NULL, np,
+ syscon_match);
+ if (!dev)
+ return ERR_PTR(-EPROBE_DEFER);
+
+ syscon = dev_get_drvdata(dev);
+
+ return syscon->regmap;
+}
+EXPORT_SYMBOL_GPL(syscon_node_to_regmap);
+
+struct regmap *syscon_regmap_lookup_by_compatible(const char *s)
+{
+ struct device_node *syscon_np;
+ struct regmap *regmap;
+
+ syscon_np = of_find_compatible_node(NULL, NULL, s);
+ if (!syscon_np)
+ return ERR_PTR(-ENODEV);
+
+ regmap = syscon_node_to_regmap(syscon_np);
+ of_node_put(syscon_np);
+
+ return regmap;
+}
+EXPORT_SYMBOL_GPL(syscon_regmap_lookup_by_compatible);
+
+struct regmap *syscon_regmap_lookup_by_phandle(struct device_node *np,
+ const char *property)
+{
+ struct device_node *syscon_np;
+ struct regmap *regmap;
+
+ syscon_np = of_parse_phandle(np, property, 0);
+ if (!syscon_np)
+ return ERR_PTR(-ENODEV);
+
+ regmap = syscon_node_to_regmap(syscon_np);
+ of_node_put(syscon_np);
+
+ return regmap;
+}
+EXPORT_SYMBOL_GPL(syscon_regmap_lookup_by_phandle);
+
+static const struct of_device_id of_syscon_match[] = {
+ { .compatible = "syscon", },
+ { },
+};
+
+static struct regmap_config syscon_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
+
+static int __devinit syscon_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct syscon *syscon;
+ struct resource res;
+ int ret;
+
+ if (!np)
+ return -ENOENT;
+
+ syscon = devm_kzalloc(&pdev->dev, sizeof(struct syscon),
+ GFP_KERNEL);
+ if (!syscon)
+ return -ENOMEM;
+
+ syscon->base = of_iomap(np, 0);
+ if (!syscon->base)
+ return -EADDRNOTAVAIL;
+
+ ret = of_address_to_resource(np, 0, &res);
+ if (ret)
+ return ret;
+
+ syscon_regmap_config.max_register = res.end - res.start - 3;
+ syscon->regmap = devm_regmap_init_mmio(&pdev->dev, syscon->base,
+ &syscon_regmap_config);
+ if (IS_ERR(syscon->regmap)) {
+ dev_err(&pdev->dev, "regmap init failed\n");
+ return PTR_ERR(syscon->regmap);
+ }
+
+ syscon->dev = &pdev->dev;
+ platform_set_drvdata(pdev, syscon);
+
+ dev_info(dev, "syscon regmap start 0x%x end 0x%x registered\n",
+ res.start, res.end);
+
+ return 0;
+}
+
+static int __devexit syscon_remove(struct platform_device *pdev)
+{
+ struct syscon *syscon;
+
+ syscon = platform_get_drvdata(pdev);
+ iounmap(syscon->base);
+ platform_set_drvdata(pdev, NULL);
+
+ return 0;
+}
+
+static struct platform_driver syscon_driver = {
+ .driver = {
+ .name = "syscon",
+ .owner = THIS_MODULE,
+ .of_match_table = of_syscon_match,
+ },
+ .probe = syscon_probe,
+ .remove = __devexit_p(syscon_remove),
+};
+
+static int __init syscon_init(void)
+{
+ return platform_driver_register(&syscon_driver);
+}
+postcore_initcall(syscon_init);
+
+static void __exit syscon_exit(void)
+{
+ platform_driver_unregister(&syscon_driver);
+}
+module_exit(syscon_exit);
+
+MODULE_AUTHOR("Dong Aisheng <dong.aisheng@linaro.org>");
+MODULE_DESCRIPTION("System Control driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/syscon.h b/include/linux/mfd/syscon.h
new file mode 100644
index 0000000..6aeb6b8
--- /dev/null
+++ b/include/linux/mfd/syscon.h
@@ -0,0 +1,23 @@
+/*
+ * System Control Driver
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * Author: Dong Aisheng <dong.aisheng@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __LINUX_MFD_SYSCON_H__
+#define __LINUX_MFD_SYSCON_H__
+
+extern struct regmap *syscon_node_to_regmap(struct device_node *np);
+extern struct regmap *syscon_regmap_lookup_by_compatible(const char *s);
+extern struct regmap *syscon_regmap_lookup_by_phandle(
+ struct device_node *np,
+ const char *property);
+#endif /* __LINUX_MFD_SYSCON_H__ */
--
1.7.0.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v5 1/4] mfd: add syscon driver based on regmap
2012-09-04 3:20 ` [PATCH v5 1/4] mfd: add syscon driver based on regmap Dong Aisheng
@ 2012-09-04 11:35 ` Andi Shyti
2012-09-04 11:46 ` Dong Aisheng
2012-09-04 12:16 ` Sergei Shtylyov
0 siblings, 2 replies; 11+ messages in thread
From: Andi Shyti @ 2012-09-04 11:35 UTC (permalink / raw)
To: Dong Aisheng
Cc: linux-kernel, linux-arm-kernel, linus.walleij, s.hauer,
shawn.guo, kernel, grant.likely, rob.herring, sameo, lrg,
broonie, richard.zhao, devicetree-discuss, swarren
Hi Dong,
On Tue, Sep 04, 2012 at 11:20:08AM +0800, Dong Aisheng wrote:
> +static int __devinit syscon_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
Do we really need this variable? Anyway you are using it only
once in the dev_info.
> + struct device_node *np = dev->of_node;
> + struct syscon *syscon;
> + struct resource res;
> + int ret;
> +
> + if (!np)
> + return -ENOENT;
> +
> + syscon = devm_kzalloc(&pdev->dev, sizeof(struct syscon),
> + GFP_KERNEL);
> + if (!syscon)
> + return -ENOMEM;
> +
> + syscon->base = of_iomap(np, 0);
> + if (!syscon->base)
> + return -EADDRNOTAVAIL;
> +
> + ret = of_address_to_resource(np, 0, &res);
> + if (ret)
> + return ret;
> +
> + syscon_regmap_config.max_register = res.end - res.start - 3;
> + syscon->regmap = devm_regmap_init_mmio(&pdev->dev, syscon->base,
> + &syscon_regmap_config);
> + if (IS_ERR(syscon->regmap)) {
> + dev_err(&pdev->dev, "regmap init failed\n");
> + return PTR_ERR(syscon->regmap);
> + }
> +
> + syscon->dev = &pdev->dev;
> + platform_set_drvdata(pdev, syscon);
> +
> + dev_info(dev, "syscon regmap start 0x%x end 0x%x registered\n",
> + res.start, res.end);
> +
> + return 0;
in case of error you are not freeing syscon.
Moreover, in my opinion, some dev_err more should not heart
Andi
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v5 1/4] mfd: add syscon driver based on regmap
2012-09-04 11:35 ` Andi Shyti
@ 2012-09-04 11:46 ` Dong Aisheng
2012-09-04 15:44 ` Andi Shyti
2012-09-04 12:16 ` Sergei Shtylyov
1 sibling, 1 reply; 11+ messages in thread
From: Dong Aisheng @ 2012-09-04 11:46 UTC (permalink / raw)
To: Andi Shyti
Cc: linux-kernel, linux-arm-kernel, linus.walleij, s.hauer,
shawn.guo, kernel, grant.likely, rob.herring, sameo, lrg,
broonie, Zhao Richard-B20223, devicetree-discuss, swarren
On Tue, Sep 04, 2012 at 07:35:45PM +0800, Andi Shyti wrote:
> Hi Dong,
>
> On Tue, Sep 04, 2012 at 11:20:08AM +0800, Dong Aisheng wrote:
> > +static int __devinit syscon_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
>
> Do we really need this variable? Anyway you are using it only
> once in the dev_info.
>
Okay, i can remove it.
> > + struct device_node *np = dev->of_node;
> > + struct syscon *syscon;
> > + struct resource res;
> > + int ret;
> > +
> > + if (!np)
> > + return -ENOENT;
> > +
> > + syscon = devm_kzalloc(&pdev->dev, sizeof(struct syscon),
> > + GFP_KERNEL);
> > + if (!syscon)
> > + return -ENOMEM;
> > +
> > + syscon->base = of_iomap(np, 0);
> > + if (!syscon->base)
> > + return -EADDRNOTAVAIL;
> > +
> > + ret = of_address_to_resource(np, 0, &res);
> > + if (ret)
> > + return ret;
> > +
> > + syscon_regmap_config.max_register = res.end - res.start - 3;
> > + syscon->regmap = devm_regmap_init_mmio(&pdev->dev, syscon->base,
> > + &syscon_regmap_config);
> > + if (IS_ERR(syscon->regmap)) {
> > + dev_err(&pdev->dev, "regmap init failed\n");
> > + return PTR_ERR(syscon->regmap);
> > + }
> > +
> > + syscon->dev = &pdev->dev;
> > + platform_set_drvdata(pdev, syscon);
> > +
> > + dev_info(dev, "syscon regmap start 0x%x end 0x%x registered\n",
> > + res.start, res.end);
> > +
> > + return 0;
>
> in case of error you are not freeing syscon.
Do we need it for managed resource of syscon?
> Moreover, in my opinion, some dev_err more should not heart
>
There's no much error cases here, most of them rarely fails and i don't feel
we really need add.
I don't know what dev_err you suggested to add?
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v5 1/4] mfd: add syscon driver based on regmap
2012-09-04 11:46 ` Dong Aisheng
@ 2012-09-04 15:44 ` Andi Shyti
0 siblings, 0 replies; 11+ messages in thread
From: Andi Shyti @ 2012-09-04 15:44 UTC (permalink / raw)
To: Dong Aisheng, Sergei Shtylyov
Cc: Andi Shyti, linux-kernel, linux-arm-kernel, linus.walleij,
s.hauer, shawn.guo, kernel, grant.likely, rob.herring, sameo,
lrg, broonie, Zhao Richard-B20223, devicetree-discuss, swarren
On Tue, Sep 04, 2012 at 07:46:02PM +0800, Dong Aisheng wrote:
> On Tue, Sep 04, 2012 at 07:35:45PM +0800, Andi Shyti wrote:
> > Hi Dong,
> >
> > On Tue, Sep 04, 2012 at 11:20:08AM +0800, Dong Aisheng wrote:
> > > +static int __devinit syscon_probe(struct platform_device *pdev)
> > > +{
> > > + struct device *dev = &pdev->dev;
> >
> > Do we really need this variable? Anyway you are using it only
> > once in the dev_info.
> >
> Okay, i can remove it.
On Tue, Sep 04, 2012 at 04:16:59PM +0400, Sergei Shtylyov wrote:
> But Dong definitely could use it more than once, so it seems useful.
[sorry for pasting your e-mail here]
yes, but he is using it only once and, it's easily
reachable with pdev->dev and anyway Dong is using &pdev->dev.
> > > +
> > > + syscon = devm_kzalloc(&pdev->dev, sizeof(struct syscon),
> > > + GFP_KERNEL);
> >
> > in case of error you are not freeing syscon.
> Do we need it for managed resource of syscon?
Yes, you're right :)
> > Moreover, in my opinion, some dev_err more should not heart
^^
as Sergei points out is 'hurt'... mistype :)
> There's no much error cases here, most of them rarely fails and i don't feel
> we really need add.
> I don't know what dev_err you suggested to add?
For example some failure cases, anyway i read quickly the code
and I don't big see issues.
Andi
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v5 1/4] mfd: add syscon driver based on regmap
2012-09-04 11:35 ` Andi Shyti
2012-09-04 11:46 ` Dong Aisheng
@ 2012-09-04 12:16 ` Sergei Shtylyov
1 sibling, 0 replies; 11+ messages in thread
From: Sergei Shtylyov @ 2012-09-04 12:16 UTC (permalink / raw)
To: Andi Shyti
Cc: Dong Aisheng, linus.walleij, swarren, devicetree-discuss,
s.hauer, broonie, linux-kernel, rob.herring, grant.likely,
richard.zhao, kernel, shawn.guo, lrg, linux-arm-kernel, sameo
Hello.
On 04-09-2012 15:35, Andi Shyti wrote:
>> +static int __devinit syscon_probe(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
> Do we really need this variable? Anyway you are using it only
> once in the dev_info.
But Dong definitely could use it more than once, so it seems useful.
>> + struct device_node *np = dev->of_node;
>> + struct syscon *syscon;
>> + struct resource res;
>> + int ret;
>> +
>> + if (!np)
>> + return -ENOENT;
>> +
>> + syscon = devm_kzalloc(&pdev->dev, sizeof(struct syscon),
>> + GFP_KERNEL);
>> + if (!syscon)
>> + return -ENOMEM;
>> +
>> + syscon->base = of_iomap(np, 0);
>> + if (!syscon->base)
>> + return -EADDRNOTAVAIL;
>> +
>> + ret = of_address_to_resource(np, 0, &res);
>> + if (ret)
>> + return ret;
>> +
>> + syscon_regmap_config.max_register = res.end - res.start - 3;
>> + syscon->regmap = devm_regmap_init_mmio(&pdev->dev, syscon->base,
>> + &syscon_regmap_config);
>> + if (IS_ERR(syscon->regmap)) {
>> + dev_err(&pdev->dev, "regmap init failed\n");
>> + return PTR_ERR(syscon->regmap);
>> + }
>> +
>> + syscon->dev = &pdev->dev;
>> + platform_set_drvdata(pdev, syscon);
>> +
>> + dev_info(dev, "syscon regmap start 0x%x end 0x%x registered\n",
>> + res.start, res.end);
>> +
>> + return 0;
> in case of error you are not freeing syscon.
It's allocated using devm_kzalloc(), so is freed automaticelly upon probe
error.
> Moreover, in my opinion, some dev_err more should not heart
Hurt, you mean?
> Andi
WBR, Sergei
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v5 2/4] ARM: imx6q: add iomuxc gpr support into syscon
2012-09-04 3:20 [PATCH v5 0/4] add syscon driver based on regmap for general registers access Dong Aisheng
2012-09-04 3:20 ` [PATCH v5 1/4] mfd: add syscon driver based on regmap Dong Aisheng
@ 2012-09-04 3:20 ` Dong Aisheng
2012-09-04 3:20 ` [PATCH v5 3/4] regulator: anatop-regulator: convert to use syscon to access anatop register Dong Aisheng
2012-09-04 3:20 ` [PATCH v5 4/4] mfd: anatop-mfd: remove anatop driver Dong Aisheng
3 siblings, 0 replies; 11+ messages in thread
From: Dong Aisheng @ 2012-09-04 3:20 UTC (permalink / raw)
To: linux-kernel
Cc: linux-arm-kernel, linus.walleij, s.hauer, shawn.guo, kernel,
grant.likely, rob.herring, sameo, lrg, broonie, richard.zhao,
devicetree-discuss, swarren
From: Dong Aisheng <dong.aisheng@linaro.org>
Include headfile for easy using.
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
---
ChangeLog v4-v5:
* renamed: include/linux/fsl/imx6q-iomuxc-gpr.h ->
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
* a minor typo fix
---
arch/arm/boot/dts/imx6q.dtsi | 5 +
include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 319 +++++++++++++++++++++++++++
2 files changed, 324 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index fd57079..bea21bc 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -507,6 +507,11 @@
interrupts = <0 89 0x04 0 90 0x04>;
};
+ gpr: iomuxc-gpr@020e0000 {
+ compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
+ reg = <0x020e0000 0x38>;
+ };
+
iomuxc@020e0000 {
compatible = "fsl,imx6q-iomuxc";
reg = <0x020e0000 0x4000>;
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
new file mode 100644
index 0000000..dab34a1
--- /dev/null
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -0,0 +1,319 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_IMX6Q_IOMUXC_GPR_H
+#define __LINUX_IMX6Q_IOMUXC_GPR_H
+
+#include <linux/bitops.h>
+
+#define IOMUXC_GPR0 0x00
+#define IOMUXC_GPR1 0x04
+#define IOMUXC_GPR2 0x08
+#define IOMUXC_GPR3 0x0c
+#define IOMUXC_GPR4 0x10
+#define IOMUXC_GPR5 0x14
+#define IOMUXC_GPR6 0x18
+#define IOMUXC_GPR7 0x1c
+#define IOMUXC_GPR8 0x20
+#define IOMUXC_GPR9 0x24
+#define IOMUXC_GPR10 0x28
+#define IOMUXC_GPR11 0x2c
+#define IOMUXC_GPR12 0x30
+#define IOMUXC_GPR13 0x34
+
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_MASK (0x3 << 30)
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7_MUXED (0x0 << 30)
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7 (0x1 << 30)
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_SSI_SRCK (0x2 << 30)
+#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_RX_BIT_CLK (0x3 << 30)
+#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_MASK (0x3 << 28)
+#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR_MUXED (0x0 << 28)
+#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR (0x1 << 28)
+#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_DO_SCKR (0x2 << 28)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_MASK (0x3 << 26)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7_MUXED (0x0 << 26)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7 (0x1 << 26)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_SSI_STCK (0x2 << 26)
+#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_TX_BIT_CLK (0x3 << 26)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_MASK (0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7_MUXED (0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7 (0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_SSI_SRCK (0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_RX_BIT_CLK (0x3 << 24)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_MASK (0x3 << 22)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2_MUXED (0x0 << 22)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2 (0x1 << 22)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_SSI_STCK (0x2 << 22)
+#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_TX_BIT_CLK (0x3 << 22)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_MASK (0x3 << 20)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2_MUXED (0x0 << 20)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2 (0x1 << 20)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_SSI_SRCK (0x2 << 20)
+#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_RX_BIT_CLK (0x3 << 20)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_MASK (0x3 << 18)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1_MUXED (0x0 << 18)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1 (0x1 << 18)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_STCK (0x2 << 18)
+#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_TX_BIT_CLK (0x3 << 18)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_MASK (0x3 << 16)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1_MUXED (0x0 << 16)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1 (0x1 << 16)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_SRCK (0x2 << 16)
+#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_RX_BIT_CLK (0x3 << 16)
+#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_MASK (0x3 << 14)
+#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK1 (0x0 << 14)
+#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK2 (0x1 << 14)
+#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK3 (0x2 << 14)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK BIT(7)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_SPDIF 0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX BIT(7)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK BIT(6)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_ESAI 0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3 BIT(6)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_MASK BIT(5)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_ECSPI4 0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_EPIT2 BIT(5)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_MASK BIT(4)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_ECSPI4 0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_I2C1 BIT(4)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_MASK BIT(3)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_ECSPI2 0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_I2C1 BIT(3)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_MASK BIT(2)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_ECSPI1 0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_I2C2 BIT(2)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_MASK BIT(1)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_ECSPI1 0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_I2C3 BIT(1)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_MASK BIT(0)
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IPU1 0x0
+#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IOMUX BIT(0)
+
+#define IMX6Q_GPR1_PCIE_REQ_MASK (0x3 << 30)
+#define IMX6Q_GPR1_PCIE_EXIT_L1 BIT(28)
+#define IMX6Q_GPR1_PCIE_RDY_L23 BIT(27)
+#define IMX6Q_GPR1_PCIE_ENTER_L1 BIT(26)
+#define IMX6Q_GPR1_MIPI_COLOR_SW BIT(25)
+#define IMX6Q_GPR1_DPI_OFF BIT(24)
+#define IMX6Q_GPR1_EXC_MON_MASK BIT(22)
+#define IMX6Q_GPR1_EXC_MON_OKAY 0x0
+#define IMX6Q_GPR1_EXC_MON_SLVE BIT(22)
+#define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK BIT(21)
+#define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET 0x0
+#define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX BIT(21)
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(20)
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0
+#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(20)
+#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(19)
+#define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET 0x0
+#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(19)
+#define IMX6Q_GPR1_PCIE_TEST_PD BIT(18)
+#define IMX6Q_GPR1_IPU_VPU_MUX_MASK BIT(17)
+#define IMX6Q_GPR1_IPU_VPU_MUX_IPU1 0x0
+#define IMX6Q_GPR1_IPU_VPU_MUX_IPU2 BIT(17)
+#define IMX6Q_GPR1_PCIE_REF_CLK_EN BIT(16)
+#define IMX6Q_GPR1_USB_EXP_MODE BIT(15)
+#define IMX6Q_GPR1_PCIE_INT BIT(14)
+#define IMX6Q_GPR1_USB_OTG_ID_SEL_MASK BIT(13)
+#define IMX6Q_GPR1_USB_OTG_ID_SEL_ENET_RX_ER 0x0
+#define IMX6Q_GPR1_USB_OTG_ID_SEL_GPIO_1 BIT(13)
+#define IMX6Q_GPR1_GINT BIT(12)
+#define IMX6Q_GPR1_ADDRS3_MASK (0x3 << 10)
+#define IMX6Q_GPR1_ADDRS3_32MB (0x0 << 10)
+#define IMX6Q_GPR1_ADDRS3_64MB (0x1 << 10)
+#define IMX6Q_GPR1_ADDRS3_128MB (0x2 << 10)
+#define IMX6Q_GPR1_ACT_CS3 BIT(9)
+#define IMX6Q_GPR1_ADDRS2_MASK (0x3 << 7)
+#define IMX6Q_GPR1_ACT_CS2 BIT(6)
+#define IMX6Q_GPR1_ADDRS1_MASK (0x3 << 4)
+#define IMX6Q_GPR1_ACT_CS1 BIT(3)
+#define IMX6Q_GPR1_ADDRS0_MASK (0x3 << 1)
+#define IMX6Q_GPR1_ACT_CS0 BIT(0)
+
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_MASK (0x3 << 20)
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_5 (0x0 << 20)
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_3 (0x1 << 20)
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_4 (0x2 << 20)
+#define IMX6Q_GPR2_COUNTER_RESET_VAL_6 (0x3 << 20)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_MASK (0x7 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_0 (0x0 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_1 (0x1 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_2 (0x2 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_3 (0x3 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_4 (0x4 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_5 (0x5 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_6 (0x6 << 16)
+#define IMX6Q_GPR2_LVDS_CLK_SHIFT_7 (0x7 << 16)
+#define IMX6Q_GPR2_BGREF_RRMODE_MASK BIT(15)
+#define IMX6Q_GPR2_BGREF_RRMODE_EXT_RESISTOR 0x0
+#define IMX6Q_GPR2_BGREF_RRMODE_INT_RESISTOR BIT(15)
+#define IMX6Q_GPR2_DI1_VS_POLARITY_MASK BIT(10)
+#define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_H 0x0
+#define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_L BIT(10)
+#define IMX6Q_GPR2_DI0_VS_POLARITY_MASK BIT(9)
+#define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_H 0x0
+#define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_L BIT(9)
+#define IMX6Q_GPR2_BIT_MAPPING_CH1_MASK BIT(8)
+#define IMX6Q_GPR2_BIT_MAPPING_CH1_SPWG 0x0
+#define IMX6Q_GPR2_BIT_MAPPING_CH1_JEIDA BIT(8)
+#define IMX6Q_GPR2_DATA_WIDTH_CH1_MASK BIT(7)
+#define IMX6Q_GPR2_DATA_WIDTH_CH1_18BIT 0x0
+#define IMX6Q_GPR2_DATA_WIDTH_CH1_24BIT BIT(7)
+#define IMX6Q_GPR2_BIT_MAPPING_CH0_MASK BIT(6)
+#define IMX6Q_GPR2_BIT_MAPPING_CH0_SPWG 0x0
+#define IMX6Q_GPR2_BIT_MAPPING_CH0_JEIDA BIT(6)
+#define IMX6Q_GPR2_DATA_WIDTH_CH0_MASK BIT(5)
+#define IMX6Q_GPR2_DATA_WIDTH_CH0_18BIT 0x0
+#define IMX6Q_GPR2_DATA_WIDTH_CH0_24BIT BIT(5)
+#define IMX6Q_GPR2_SPLIT_MODE_EN BIT(4)
+#define IMX6Q_GPR2_CH1_MODE_MASK (0x3 << 2)
+#define IMX6Q_GPR2_CH1_MODE_DISABLE (0x0 << 2)
+#define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI0 (0x1 << 2)
+#define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI1 (0x3 << 2)
+#define IMX6Q_GPR2_CH0_MODE_MASK (0x3 << 0)
+#define IMX6Q_GPR2_CH0_MODE_DISABLE (0x0 << 0)
+#define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI0 (0x1 << 0)
+#define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI1 (0x3 << 0)
+
+#define IMX6Q_GPR3_GPU_DBG_MASK (0x3 << 29)
+#define IMX6Q_GPR3_GPU_DBG_GPU3D (0x0 << 29)
+#define IMX6Q_GPR3_GPU_DBG_GPU2D (0x1 << 29)
+#define IMX6Q_GPR3_GPU_DBG_OPENVG (0x2 << 29)
+#define IMX6Q_GPR3_BCH_WR_CACHE_CTL BIT(28)
+#define IMX6Q_GPR3_BCH_RD_CACHE_CTL BIT(27)
+#define IMX6Q_GPR3_USDHCX_WR_CACHE_CTL BIT(26)
+#define IMX6Q_GPR3_USDHCX_RD_CACHE_CTL BIT(25)
+#define IMX6Q_GPR3_OCRAM_CTL_MASK (0xf << 21)
+#define IMX6Q_GPR3_OCRAM_STATUS_MASK (0xf << 17)
+#define IMX6Q_GPR3_CORE3_DBG_ACK_EN BIT(16)
+#define IMX6Q_GPR3_CORE2_DBG_ACK_EN BIT(15)
+#define IMX6Q_GPR3_CORE1_DBG_ACK_EN BIT(14)
+#define IMX6Q_GPR3_CORE0_DBG_ACK_EN BIT(13)
+#define IMX6Q_GPR3_TZASC2_BOOT_LOCK BIT(12)
+#define IMX6Q_GPR3_TZASC1_BOOT_LOCK BIT(11)
+#define IMX6Q_GPR3_IPU_DIAG_MASK BIT(10)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_MASK (0x3 << 8)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI0 (0x0 << 8)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI1 (0x1 << 8)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI0 (0x2 << 8)
+#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI1 (0x3 << 8)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_MASK (0x3 << 6)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI0 (0x0 << 6)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI1 (0x1 << 6)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0 (0x2 << 6)
+#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI1 (0x3 << 6)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_MASK (0x3 << 4)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI0 (0x0 << 4)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1 (0x1 << 4)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI0 (0x2 << 4)
+#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI1 (0x3 << 4)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_MASK (0x3 << 2)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI0 (0x0 << 2)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI1 (0x1 << 2)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI0 (0x2 << 2)
+#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI1 (0x3 << 2)
+
+#define IMX6Q_GPR4_VDOA_WR_CACHE_SEL BIT(31)
+#define IMX6Q_GPR4_VDOA_RD_CACHE_SEL BIT(30)
+#define IMX6Q_GPR4_VDOA_WR_CACHE_VAL BIT(29)
+#define IMX6Q_GPR4_VDOA_RD_CACHE_VAL BIT(28)
+#define IMX6Q_GPR4_PCIE_WR_CACHE_SEL BIT(27)
+#define IMX6Q_GPR4_PCIE_RD_CACHE_SEL BIT(26)
+#define IMX6Q_GPR4_PCIE_WR_CACHE_VAL BIT(25)
+#define IMX6Q_GPR4_PCIE_RD_CACHE_VAL BIT(24)
+#define IMX6Q_GPR4_SDMA_STOP_ACK BIT(19)
+#define IMX6Q_GPR4_CAN2_STOP_ACK BIT(18)
+#define IMX6Q_GPR4_CAN1_STOP_ACK BIT(17)
+#define IMX6Q_GPR4_ENET_STOP_ACK BIT(16)
+#define IMX6Q_GPR4_SOC_VERSION_MASK (0xff << 8)
+#define IMX6Q_GPR4_SOC_VERSION_OFF 0x8
+#define IMX6Q_GPR4_VPU_WR_CACHE_SEL BIT(7)
+#define IMX6Q_GPR4_VPU_RD_CACHE_SEL BIT(6)
+#define IMX6Q_GPR4_VPU_P_WR_CACHE_VAL BIT(3)
+#define IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK BIT(2)
+#define IMX6Q_GPR4_IPU_WR_CACHE_CTL BIT(1)
+#define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0)
+
+#define IMX6Q_GPR5_L2_CLK_STOP BIT(8)
+
+#define IMX6Q_GPR9_TZASC2_BYP BIT(1)
+#define IMX6Q_GPR9_TZASC1_BYP BIT(0)
+
+#define IMX6Q_GPR10_LOCK_DBG_EN BIT(29)
+#define IMX6Q_GPR10_LOCK_DBG_CLK_EN BIT(28)
+#define IMX6Q_GPR10_LOCK_SEC_ERR_RESP BIT(27)
+#define IMX6Q_GPR10_LOCK_OCRAM_TZ_ADDR (0x3f << 21)
+#define IMX6Q_GPR10_LOCK_OCRAM_TZ_EN BIT(20)
+#define IMX6Q_GPR10_LOCK_DCIC2_MUX_MASK (0x3 << 18)
+#define IMX6Q_GPR10_LOCK_DCIC1_MUX_MASK (0x3 << 16)
+#define IMX6Q_GPR10_DBG_EN BIT(13)
+#define IMX6Q_GPR10_DBG_CLK_EN BIT(12)
+#define IMX6Q_GPR10_SEC_ERR_RESP_MASK BIT(11)
+#define IMX6Q_GPR10_SEC_ERR_RESP_OKEY 0x0
+#define IMX6Q_GPR10_SEC_ERR_RESP_SLVE BIT(11)
+#define IMX6Q_GPR10_OCRAM_TZ_ADDR_MASK (0x3f << 5)
+#define IMX6Q_GPR10_OCRAM_TZ_EN_MASK BIT(4)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_MASK (0x3 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI0 (0x0 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1 (0x1 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI0 (0x2 << 2)
+#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI1 (0x3 << 2)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_MASK (0x3 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI0 (0x0 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI1 (0x1 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI0 (0x2 << 0)
+#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI1 (0x3 << 0)
+
+#define IMX6Q_GPR12_ARMP_IPG_CLK_EN BIT(27)
+#define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26)
+#define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25)
+#define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24)
+#define IMX6Q_GPR12_PCIE_CTL_2 BIT(10)
+
+#define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30)
+#define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29)
+#define IMX6Q_GPR13_CAN1_STOP_REQ BIT(28)
+#define IMX6Q_GPR13_ENET_STOP_REQ BIT(27)
+#define IMX6Q_GPR13_SATA_PHY_8_MASK (0x7 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_0_5_DB (0x0 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_1_0_DB (0x1 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_1_5_DB (0x2 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_2_0_DB (0x3 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_2_5_DB (0x4 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_3_0_DB (0x5 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_3_5_DB (0x6 << 24)
+#define IMX6Q_GPR13_SATA_PHY_8_4_0_DB (0x7 << 24)
+#define IMX6Q_GPR13_SATA_PHY_7_MASK (0x1f << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA1I (0x10 << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA1M (0x10 << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA1X (0x1a << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA2I (0x12 << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA2M (0x12 << 19)
+#define IMX6Q_GPR13_SATA_PHY_7_SATA2X (0x1a << 19)
+#define IMX6Q_GPR13_SATA_PHY_6_MASK (0x7 << 16)
+#define IMX6Q_GPR13_SATA_SPEED_MASK BIT(15)
+#define IMX6Q_GPR13_SATA_SPEED_1P5G 0x0
+#define IMX6Q_GPR13_SATA_SPEED_3P0G BIT(15)
+#define IMX6Q_GPR13_SATA_PHY_5 BIT(14)
+#define IMX6Q_GPR13_SATA_PHY_4_MASK (0x7 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_16_16 (0x0 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_14_16 (0x1 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_12_16 (0x2 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_10_16 (0x3 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_9_16 (0x4 << 11)
+#define IMX6Q_GPR13_SATA_PHY_4_8_16 (0x5 << 11)
+#define IMX6Q_GPR13_SATA_PHY_3_MASK (0xf << 7)
+#define IMX6Q_GPR13_SATA_PHY_3_OFF 0x7
+#define IMX6Q_GPR13_SATA_PHY_2_MASK (0x1f << 2)
+#define IMX6Q_GPR13_SATA_PHY_2_OFF 0x2
+#define IMX6Q_GPR13_SATA_PHY_1_MASK (0x3 << 0)
+#define IMX6Q_GPR13_SATA_PHY_1_FAST (0x0 << 0)
+#define IMX6Q_GPR13_SATA_PHY_1_MED (0x1 << 0)
+#define IMX6Q_GPR13_SATA_PHY_1_SLOW (0x2 << 0)
+
+#endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
--
1.7.0.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v5 3/4] regulator: anatop-regulator: convert to use syscon to access anatop register
2012-09-04 3:20 [PATCH v5 0/4] add syscon driver based on regmap for general registers access Dong Aisheng
2012-09-04 3:20 ` [PATCH v5 1/4] mfd: add syscon driver based on regmap Dong Aisheng
2012-09-04 3:20 ` [PATCH v5 2/4] ARM: imx6q: add iomuxc gpr support into syscon Dong Aisheng
@ 2012-09-04 3:20 ` Dong Aisheng
2012-09-04 11:34 ` Shawn Guo
2012-09-04 3:20 ` [PATCH v5 4/4] mfd: anatop-mfd: remove anatop driver Dong Aisheng
3 siblings, 1 reply; 11+ messages in thread
From: Dong Aisheng @ 2012-09-04 3:20 UTC (permalink / raw)
To: linux-kernel
Cc: linux-arm-kernel, linus.walleij, s.hauer, shawn.guo, kernel,
grant.likely, rob.herring, sameo, lrg, broonie, richard.zhao,
devicetree-discuss, swarren
From: Dong Aisheng <dong.aisheng@linaro.org>
Using syscon to access anatop register.
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
---
ChangeLog v4->v5:
* merge patch 3,4,5,6 to avoid break bisect.
ChangeLog v2->v3:
* update to use syscon_node_to_regmap and use of_get_parent to get anatop node.
ChangeLog v1-v2:
* update to use generic regmap api
---
arch/arm/boot/dts/imx6q.dtsi | 4 +-
arch/arm/mach-imx/Kconfig | 2 +-
arch/arm/mach-imx/mach-imx6q.c | 47 +++++++++++++---------------------
drivers/regulator/Kconfig | 2 +-
drivers/regulator/anatop-regulator.c | 30 ++++++++++++++-------
5 files changed, 42 insertions(+), 43 deletions(-)
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index bea21bc..52ed4d1 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -378,8 +378,8 @@
interrupts = <0 87 0x04 0 88 0x04>;
};
- anatop@020c8000 {
- compatible = "fsl,imx6q-anatop";
+ anatop: anatop@020c8000 {
+ compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
reg = <0x020c8000 0x1000>;
interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index afd542a..7bba253 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -839,7 +839,7 @@ config SOC_IMX6Q
select HAVE_IMX_MMDC
select HAVE_IMX_SRC
select HAVE_SMP
- select MFD_ANATOP
+ select MFD_SYSCON
select PINCTRL
select PINCTRL_IMX6Q
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 045b3f6..eaf56b4 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -24,8 +24,9 @@
#include <linux/of_platform.h>
#include <linux/pinctrl/machine.h>
#include <linux/phy.h>
+#include <linux/regmap.h>
#include <linux/micrel_phy.h>
-#include <linux/mfd/anatop.h>
+#include <linux/mfd/syscon.h>
#include <asm/cpuidle.h>
#include <asm/smp_twd.h>
#include <asm/hardware/cache-l2x0.h>
@@ -120,20 +121,7 @@ static void __init imx6q_sabrelite_init(void)
static void __init imx6q_usb_init(void)
{
- struct device_node *np;
- struct platform_device *pdev = NULL;
- struct anatop *adata = NULL;
-
- np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
- if (np)
- pdev = of_find_device_by_node(np);
- if (pdev)
- adata = platform_get_drvdata(pdev);
- if (!adata) {
- if (np)
- of_node_put(np);
- return;
- }
+ struct regmap *anatop;
#define HW_ANADIG_USB1_CHRG_DETECT 0x000001b0
#define HW_ANADIG_USB2_CHRG_DETECT 0x00000210
@@ -141,20 +129,21 @@ static void __init imx6q_usb_init(void)
#define BM_ANADIG_USB_CHRG_DETECT_EN_B 0x00100000
#define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B 0x00080000
- /*
- * The external charger detector needs to be disabled,
- * or the signal at DP will be poor
- */
- anatop_write_reg(adata, HW_ANADIG_USB1_CHRG_DETECT,
- BM_ANADIG_USB_CHRG_DETECT_EN_B
- | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B,
- ~0);
- anatop_write_reg(adata, HW_ANADIG_USB2_CHRG_DETECT,
- BM_ANADIG_USB_CHRG_DETECT_EN_B |
- BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B,
- ~0);
-
- of_node_put(np);
+ anatop = syscon_regmap_lookup_by_compatible("fsl,imx6q-anatop");
+ if (!IS_ERR(anatop)) {
+ /*
+ * The external charger detector needs to be disabled,
+ * or the signal at DP will be poor
+ */
+ regmap_write(anatop, HW_ANADIG_USB1_CHRG_DETECT,
+ BM_ANADIG_USB_CHRG_DETECT_EN_B
+ | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
+ regmap_write(anatop, HW_ANADIG_USB2_CHRG_DETECT,
+ BM_ANADIG_USB_CHRG_DETECT_EN_B |
+ BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B);
+ } else {
+ pr_warn("failed to find fsl,imx6q-anatop regmap\n");
+ }
}
static void __init imx6q_init_machine(void)
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 4e932cc..2ae1d97 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -112,7 +112,7 @@ config REGULATOR_DA9052
config REGULATOR_ANATOP
tristate "Freescale i.MX on-chip ANATOP LDO regulators"
- depends on MFD_ANATOP
+ depends on MFD_SYSCON
help
Say y here to support Freescale i.MX on-chip ANATOP LDOs
regulators. It is recommended that this option be
diff --git a/drivers/regulator/anatop-regulator.c b/drivers/regulator/anatop-regulator.c
index ce0fe72..346e5f6 100644
--- a/drivers/regulator/anatop-regulator.c
+++ b/drivers/regulator/anatop-regulator.c
@@ -21,19 +21,20 @@
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/module.h>
+#include <linux/mfd/syscon.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/mfd/anatop.h>
+#include <linux/regmap.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/of_regulator.h>
struct anatop_regulator {
const char *name;
u32 control_reg;
- struct anatop *mfd;
+ struct regmap *anatop;
int vol_bit_shift;
int vol_bit_width;
int min_bit_val;
@@ -43,7 +44,8 @@ struct anatop_regulator {
struct regulator_init_data *initdata;
};
-static int anatop_set_voltage_sel(struct regulator_dev *reg, unsigned selector)
+static int anatop_regmap_set_voltage_sel(struct regulator_dev *reg,
+ unsigned selector)
{
struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
u32 val, mask;
@@ -56,12 +58,13 @@ static int anatop_set_voltage_sel(struct regulator_dev *reg, unsigned selector)
mask = ((1 << anatop_reg->vol_bit_width) - 1) <<
anatop_reg->vol_bit_shift;
val <<= anatop_reg->vol_bit_shift;
- anatop_write_reg(anatop_reg->mfd, anatop_reg->control_reg, val, mask);
+ regmap_update_bits(anatop_reg->anatop, anatop_reg->control_reg,
+ mask, val);
return 0;
}
-static int anatop_get_voltage_sel(struct regulator_dev *reg)
+static int anatop_regmap_get_voltage_sel(struct regulator_dev *reg)
{
struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
u32 val, mask;
@@ -69,7 +72,7 @@ static int anatop_get_voltage_sel(struct regulator_dev *reg)
if (!anatop_reg->control_reg)
return -ENOTSUPP;
- val = anatop_read_reg(anatop_reg->mfd, anatop_reg->control_reg);
+ regmap_read(anatop_reg->anatop, anatop_reg->control_reg, &val);
mask = ((1 << anatop_reg->vol_bit_width) - 1) <<
anatop_reg->vol_bit_shift;
val = (val & mask) >> anatop_reg->vol_bit_shift;
@@ -78,8 +81,8 @@ static int anatop_get_voltage_sel(struct regulator_dev *reg)
}
static struct regulator_ops anatop_rops = {
- .set_voltage_sel = anatop_set_voltage_sel,
- .get_voltage_sel = anatop_get_voltage_sel,
+ .set_voltage_sel = anatop_regmap_set_voltage_sel,
+ .get_voltage_sel = anatop_regmap_get_voltage_sel,
.list_voltage = regulator_list_voltage_linear,
.map_voltage = regulator_map_voltage_linear,
};
@@ -88,11 +91,11 @@ static int __devinit anatop_regulator_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
+ struct device_node *anatop_np;
struct regulator_desc *rdesc;
struct regulator_dev *rdev;
struct anatop_regulator *sreg;
struct regulator_init_data *initdata;
- struct anatop *anatopmfd = dev_get_drvdata(pdev->dev.parent);
struct regulator_config config = { };
int ret = 0;
@@ -109,7 +112,14 @@ static int __devinit anatop_regulator_probe(struct platform_device *pdev)
rdesc->ops = &anatop_rops;
rdesc->type = REGULATOR_VOLTAGE;
rdesc->owner = THIS_MODULE;
- sreg->mfd = anatopmfd;
+
+ anatop_np = of_get_parent(np);
+ if (!anatop_np)
+ return -ENODEV;
+ sreg->anatop = syscon_node_to_regmap(anatop_np);
+ if (IS_ERR(sreg->anatop))
+ return PTR_ERR(sreg->anatop);
+
ret = of_property_read_u32(np, "anatop-reg-offset",
&sreg->control_reg);
if (ret) {
--
1.7.0.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v5 3/4] regulator: anatop-regulator: convert to use syscon to access anatop register
2012-09-04 3:20 ` [PATCH v5 3/4] regulator: anatop-regulator: convert to use syscon to access anatop register Dong Aisheng
@ 2012-09-04 11:34 ` Shawn Guo
2012-09-04 11:27 ` Dong Aisheng
0 siblings, 1 reply; 11+ messages in thread
From: Shawn Guo @ 2012-09-04 11:34 UTC (permalink / raw)
To: Dong Aisheng
Cc: linux-kernel, linux-arm-kernel, linus.walleij, s.hauer, kernel,
grant.likely, rob.herring, sameo, lrg, broonie, richard.zhao,
devicetree-discuss, swarren
On Tue, Sep 04, 2012 at 11:20:10AM +0800, Dong Aisheng wrote:
> +
> + anatop_np = of_get_parent(np);
> + if (!anatop_np)
> + return -ENODEV;
> + sreg->anatop = syscon_node_to_regmap(anatop_np);
> + if (IS_ERR(sreg->anatop))
> + return PTR_ERR(sreg->anatop);
> +
With of_node_put moved out from syscon_node_to_regmap, shouldn't
we put anatop_np here then?
--
Regards,
Shawn
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v5 3/4] regulator: anatop-regulator: convert to use syscon to access anatop register
2012-09-04 11:34 ` Shawn Guo
@ 2012-09-04 11:27 ` Dong Aisheng
0 siblings, 0 replies; 11+ messages in thread
From: Dong Aisheng @ 2012-09-04 11:27 UTC (permalink / raw)
To: Shawn Guo
Cc: linux-kernel, linux-arm-kernel, linus.walleij, s.hauer, kernel,
grant.likely, rob.herring, sameo, lrg, broonie,
Zhao Richard-B20223, devicetree-discuss, swarren
On Tue, Sep 04, 2012 at 07:34:32PM +0800, Shawn Guo wrote:
> On Tue, Sep 04, 2012 at 11:20:10AM +0800, Dong Aisheng wrote:
> > +
> > + anatop_np = of_get_parent(np);
> > + if (!anatop_np)
> > + return -ENODEV;
> > + sreg->anatop = syscon_node_to_regmap(anatop_np);
> > + if (IS_ERR(sreg->anatop))
> > + return PTR_ERR(sreg->anatop);
> > +
> With of_node_put moved out from syscon_node_to_regmap, shouldn't
> we put anatop_np here then?
>
When i sent it out, i found i missed it...
Should be more care...
Regards
Dong Aisheng
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v5 4/4] mfd: anatop-mfd: remove anatop driver
2012-09-04 3:20 [PATCH v5 0/4] add syscon driver based on regmap for general registers access Dong Aisheng
` (2 preceding siblings ...)
2012-09-04 3:20 ` [PATCH v5 3/4] regulator: anatop-regulator: convert to use syscon to access anatop register Dong Aisheng
@ 2012-09-04 3:20 ` Dong Aisheng
3 siblings, 0 replies; 11+ messages in thread
From: Dong Aisheng @ 2012-09-04 3:20 UTC (permalink / raw)
To: linux-kernel
Cc: linux-arm-kernel, linus.walleij, s.hauer, shawn.guo, kernel,
grant.likely, rob.herring, sameo, lrg, broonie, richard.zhao,
devicetree-discuss, swarren
From: Dong Aisheng <dong.aisheng@linaro.org>
The anatop registers are accessed via syscon now, no one will use
mfd anatop driver anymore, remove it.
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
---
drivers/mfd/Kconfig | 8 ---
drivers/mfd/Makefile | 1 -
drivers/mfd/anatop-mfd.c | 124 --------------------------------------------
include/linux/mfd/anatop.h | 40 --------------
4 files changed, 0 insertions(+), 173 deletions(-)
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 82247b7..0b5c0cc 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -985,14 +985,6 @@ config MFD_STA2X11
depends on STA2X11
select MFD_CORE
-config MFD_ANATOP
- bool "Support for Freescale i.MX on-chip ANATOP controller"
- depends on SOC_IMX6Q
- help
- Select this option to enable Freescale i.MX on-chip ANATOP
- MFD controller. This controller embeds regulator and
- thermal devices for Freescale i.MX platforms.
-
config MFD_SYSCON
bool "System Controller Register R/W Based on Regmap"
depends on OF
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 8384bc9..0f10a95 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -130,6 +130,5 @@ obj-$(CONFIG_MFD_INTEL_MSIC) += intel_msic.o
obj-$(CONFIG_MFD_PALMAS) += palmas.o
obj-$(CONFIG_MFD_RC5T583) += rc5t583.o rc5t583-irq.o
obj-$(CONFIG_MFD_SEC_CORE) += sec-core.o sec-irq.o
-obj-$(CONFIG_MFD_ANATOP) += anatop-mfd.o
obj-$(CONFIG_MFD_SYSCON) += syscon.o
obj-$(CONFIG_MFD_LM3533) += lm3533-core.o lm3533-ctrlbank.o
diff --git a/drivers/mfd/anatop-mfd.c b/drivers/mfd/anatop-mfd.c
deleted file mode 100644
index 5576e07..0000000
--- a/drivers/mfd/anatop-mfd.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Anatop MFD driver
- *
- * Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
- * Copyright (C) 2012 Linaro
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- */
-
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/of.h>
-#include <linux/of_platform.h>
-#include <linux/of_address.h>
-#include <linux/mfd/anatop.h>
-
-u32 anatop_read_reg(struct anatop *adata, u32 addr)
-{
- return readl(adata->ioreg + addr);
-}
-EXPORT_SYMBOL_GPL(anatop_read_reg);
-
-void anatop_write_reg(struct anatop *adata, u32 addr, u32 data, u32 mask)
-{
- u32 val;
-
- data &= mask;
-
- spin_lock(&adata->reglock);
- val = readl(adata->ioreg + addr);
- val &= ~mask;
- val |= data;
- writel(val, adata->ioreg + addr);
- spin_unlock(&adata->reglock);
-}
-EXPORT_SYMBOL_GPL(anatop_write_reg);
-
-static const struct of_device_id of_anatop_match[] = {
- { .compatible = "fsl,imx6q-anatop", },
- { },
-};
-
-static int __devinit of_anatop_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct device_node *np = dev->of_node;
- void *ioreg;
- struct anatop *drvdata;
-
- ioreg = of_iomap(np, 0);
- if (!ioreg)
- return -EADDRNOTAVAIL;
- drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
- if (!drvdata)
- return -ENOMEM;
- drvdata->ioreg = ioreg;
- spin_lock_init(&drvdata->reglock);
- platform_set_drvdata(pdev, drvdata);
- of_platform_populate(np, NULL, NULL, dev);
-
- return 0;
-}
-
-static int __devexit of_anatop_remove(struct platform_device *pdev)
-{
- struct anatop *drvdata;
- drvdata = platform_get_drvdata(pdev);
- iounmap(drvdata->ioreg);
-
- return 0;
-}
-
-static struct platform_driver anatop_of_driver = {
- .driver = {
- .name = "anatop-mfd",
- .owner = THIS_MODULE,
- .of_match_table = of_anatop_match,
- },
- .probe = of_anatop_probe,
- .remove = of_anatop_remove,
-};
-
-static int __init anatop_init(void)
-{
- return platform_driver_register(&anatop_of_driver);
-}
-postcore_initcall(anatop_init);
-
-static void __exit anatop_exit(void)
-{
- platform_driver_unregister(&anatop_of_driver);
-}
-module_exit(anatop_exit);
-
-MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>");
-MODULE_DESCRIPTION("ANATOP MFD driver");
-MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/anatop.h b/include/linux/mfd/anatop.h
deleted file mode 100644
index 7f92acf..0000000
--- a/include/linux/mfd/anatop.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * anatop.h - Anatop MFD driver
- *
- * Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
- * Copyright (C) 2012 Linaro
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef __LINUX_MFD_ANATOP_H
-#define __LINUX_MFD_ANATOP_H
-
-#include <linux/spinlock.h>
-
-/**
- * anatop - MFD data
- * @ioreg: ioremap register
- * @reglock: spinlock for register read/write
- */
-struct anatop {
- void *ioreg;
- spinlock_t reglock;
-};
-
-extern u32 anatop_read_reg(struct anatop *, u32);
-extern void anatop_write_reg(struct anatop *, u32, u32, u32);
-
-#endif /* __LINUX_MFD_ANATOP_H */
--
1.7.0.4
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