From: Huacai Chen <chenhc@lemote.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org,
Fuxin Zhang <zhangfx@lemote.com>,
Zhangjin Wu <wuzhangjin@gmail.com>,
Huacai Chen <chenhc@lemote.com>, Hongliang Tao <taohl@lemote.com>,
Hua Yan <yanh@lemote.com>
Subject: [PATCH V7 03/15] MIPS: Loongson: Introduce and use cpu_has_coherent_cache feature
Date: Fri, 5 Oct 2012 21:25:00 +0800 [thread overview]
Message-ID: <1349443512-18340-4-git-send-email-chenhc@lemote.com> (raw)
In-Reply-To: <1349443512-18340-1-git-send-email-chenhc@lemote.com>
Loongson-3 maintains cache coherency by hardware. So we introduce a cpu
feature named cpu_has_coherent_cache and use it to modify MIPS's cache
flushing functions.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Hongliang Tao <taohl@lemote.com>
Signed-off-by: Hua Yan <yanh@lemote.com>
---
arch/mips/include/asm/cacheflush.h | 6 ++++++
arch/mips/include/asm/cpu-features.h | 6 ++++++
arch/mips/mm/c-r4k.c | 21 +++++++++++++++++++--
3 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/cacheflush.h b/arch/mips/include/asm/cacheflush.h
index 69468de..8c4fa0d 100644
--- a/arch/mips/include/asm/cacheflush.h
+++ b/arch/mips/include/asm/cacheflush.h
@@ -70,6 +70,9 @@ extern void (*__flush_cache_vmap)(void);
static inline void flush_cache_vmap(unsigned long start, unsigned long end)
{
+ if (cpu_has_coherent_cache)
+ return;
+
if (cpu_has_dc_aliases)
__flush_cache_vmap();
}
@@ -78,6 +81,9 @@ extern void (*__flush_cache_vunmap)(void);
static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
{
+ if (cpu_has_coherent_cache)
+ return;
+
if (cpu_has_dc_aliases)
__flush_cache_vunmap();
}
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index ca400f7..8523477 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -238,6 +238,12 @@
#define cpu_has_inclusive_pcaches (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
#endif
+#ifdef CONFIG_CPU_SUPPORTS_COHERENT_CACHE
+#define cpu_has_coherent_cache 1
+#else
+#define cpu_has_coherent_cache 0
+#endif
+
#ifndef cpu_dcache_line_size
#define cpu_dcache_line_size() cpu_data[0].dcache.linesz
#endif
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 5352387..e8ae44f 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -345,6 +345,10 @@ static inline void local_r4k___flush_cache_all(void * args)
r4k_blast_scache();
return;
#endif
+
+ if (cpu_has_coherent_cache)
+ return;
+
r4k_blast_dcache();
r4k_blast_icache();
@@ -406,8 +410,12 @@ static inline void local_r4k_flush_cache_range(void * args)
static void r4k_flush_cache_range(struct vm_area_struct *vma,
unsigned long start, unsigned long end)
{
- int exec = vma->vm_flags & VM_EXEC;
+ int exec __maybe_unused;
+
+ if (cpu_has_coherent_cache)
+ return;
+ exec = vma->vm_flags & VM_EXEC;
if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
r4k_on_each_cpu(local_r4k_flush_cache_range, vma);
}
@@ -527,7 +535,10 @@ static inline void local_r4k_flush_cache_page(void *args)
static void r4k_flush_cache_page(struct vm_area_struct *vma,
unsigned long addr, unsigned long pfn)
{
- struct flush_cache_page_args args;
+ struct flush_cache_page_args args __maybe_unused;
+
+ if (cpu_has_coherent_cache)
+ return;
args.vma = vma;
args.addr = addr;
@@ -543,6 +554,9 @@ static inline void local_r4k_flush_data_cache_page(void * addr)
static void r4k_flush_data_cache_page(unsigned long addr)
{
+ if (cpu_has_coherent_cache)
+ return;
+
if (in_atomic())
local_r4k_flush_data_cache_page((void *)addr);
else
@@ -701,6 +715,9 @@ static void local_r4k_flush_cache_sigtramp(void * arg)
static void r4k_flush_cache_sigtramp(unsigned long addr)
{
+ if (cpu_has_coherent_cache)
+ return;
+
r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr);
}
--
1.7.7.3
next prev parent reply other threads:[~2012-10-05 13:26 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-05 13:24 [PATCH V7 00/15] MIPS: Add Loongson-3 based machines support Huacai Chen
2012-10-05 13:24 ` [PATCH V7 01/15] MIPS: Loongson: Add basic Loongson-3 definition Huacai Chen
2012-10-05 13:24 ` [PATCH V7 02/15] MIPS: Loongson: Add basic Loongson-3 CPU support Huacai Chen
2012-10-05 13:25 ` Huacai Chen [this message]
2012-10-05 13:25 ` [PATCH V7 04/15] MIPS: Loongson 3: Add Lemote-3A machtypes definition Huacai Chen
2012-10-05 13:25 ` [PATCH V7 05/15] MIPS: Loongson: Add UEFI-like firmware interface support Huacai Chen
2012-10-05 13:25 ` [PATCH V7 06/15] MIPS: Loongson 3: Add HT-linked PCI support Huacai Chen
2012-10-05 13:25 ` [PATCH V7 07/15] MIPS: Loongson 3: Add IRQ init and dispatch support Huacai Chen
2012-10-05 13:25 ` [PATCH V7 08/15] MIPS: Loongson 3: Add serial port support Huacai Chen
2012-10-05 13:25 ` [PATCH V7 09/15] MIPS: Loongson: Add swiotlb to support big memory (>4GB) Huacai Chen
2012-10-05 13:25 ` [PATCH V7 10/15] MIPS: Loongson: Add Loongson-3 Kconfig options Huacai Chen
2012-10-05 13:25 ` [PATCH V7 11/15] drm: Handle io prot correctly for MIPS Huacai Chen
2012-10-05 13:25 ` [PATCH V7 12/15] ALSA: HDA: Make hda sound card usable for Loongson Huacai Chen
2012-10-08 8:22 ` [alsa-devel] " Takashi Iwai
2012-10-11 7:34 ` Huacai Chen
2012-10-05 13:25 ` [PATCH V7 13/15] MIPS: Loongson 3: Add Loongson-3 SMP support Huacai Chen
2012-10-05 13:25 ` [PATCH V7 14/15] MIPS: Loongson 3: Add CPU hotplug support Huacai Chen
2012-10-05 13:25 ` [PATCH V7 15/15] MIPS: Loongson: Add a Loongson-3 default config file Huacai Chen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1349443512-18340-4-git-send-email-chenhc@lemote.com \
--to=chenhc@lemote.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mips@linux-mips.org \
--cc=ralf@linux-mips.org \
--cc=taohl@lemote.com \
--cc=wuzhangjin@gmail.com \
--cc=yanh@lemote.com \
--cc=zhangfx@lemote.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).