From: Andi Kleen <andi@firstfloor.org>
To: mingo@kernel.org
Cc: linux-kernel@vger.kernel.org, a.p.zijlstra@chello.nl,
akpm@linux-foundation.org, acme@redhat.com, eranian@google.com,
jolsa@redhat.com, namhyung@kernel.org,
Andi Kleen <ak@linux.intel.com>
Subject: [PATCH 10/12] perf, x86: Support LBR filtering by INTX/NOTX/ABORT v2
Date: Fri, 25 Jan 2013 14:00:43 -0800 [thread overview]
Message-ID: <1359151245-13179-11-git-send-email-andi@firstfloor.org> (raw)
In-Reply-To: <1359151245-13179-1-git-send-email-andi@firstfloor.org>
From: Andi Kleen <ak@linux.intel.com>
Add LBR filtering for branch in transaction, branch not in transaction
or transaction abort. This is exposed as new sample types.
v2: Rename ABORT to ABORTTX
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/kernel/cpu/perf_event_intel_lbr.c | 31 +++++++++++++++++++++++++--
include/uapi/linux/perf_event.h | 5 +++-
2 files changed, 32 insertions(+), 4 deletions(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index ad5af13..5455a00 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -85,9 +85,13 @@ enum {
X86_BR_JMP = 1 << 9, /* jump */
X86_BR_IRQ = 1 << 10,/* hw interrupt or trap or fault */
X86_BR_IND_CALL = 1 << 11,/* indirect calls */
+ X86_BR_ABORT = 1 << 12,/* transaction abort */
+ X86_BR_INTX = 1 << 13,/* in transaction */
+ X86_BR_NOTX = 1 << 14,/* not in transaction */
};
#define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL)
+#define X86_BR_ANYTX (X86_BR_NOTX | X86_BR_INTX)
#define X86_BR_ANY \
(X86_BR_CALL |\
@@ -99,6 +103,7 @@ enum {
X86_BR_JCC |\
X86_BR_JMP |\
X86_BR_IRQ |\
+ X86_BR_ABORT |\
X86_BR_IND_CALL)
#define X86_BR_ALL (X86_BR_PLM | X86_BR_ANY)
@@ -347,6 +352,16 @@ static void intel_pmu_setup_sw_lbr_filter(struct perf_event *event)
if (br_type & PERF_SAMPLE_BRANCH_IND_CALL)
mask |= X86_BR_IND_CALL;
+
+ if (br_type & PERF_SAMPLE_BRANCH_ABORTTX)
+ mask |= X86_BR_ABORT;
+
+ if (br_type & PERF_SAMPLE_BRANCH_INTX)
+ mask |= X86_BR_INTX;
+
+ if (br_type & PERF_SAMPLE_BRANCH_NOTX)
+ mask |= X86_BR_NOTX;
+
/*
* stash actual user request into reg, it may
* be used by fixup code for some CPU
@@ -393,7 +408,8 @@ int intel_pmu_setup_lbr_filter(struct perf_event *event)
/*
* no LBR on this PMU
*/
- if (!x86_pmu.lbr_nr || x86_pmu.intel_cap.lbr_format > LBR_FORMAT_MAX_KNOWN)
+ if (!x86_pmu.lbr_nr ||
+ x86_pmu.intel_cap.lbr_format > LBR_FORMAT_MAX_KNOWN)
return -EOPNOTSUPP;
/*
@@ -421,7 +437,7 @@ int intel_pmu_setup_lbr_filter(struct perf_event *event)
* decoded (e.g., text page not present), then X86_BR_NONE is
* returned.
*/
-static int branch_type(unsigned long from, unsigned long to)
+static int branch_type(unsigned long from, unsigned long to, int abort)
{
struct insn insn;
void *addr;
@@ -441,6 +457,9 @@ static int branch_type(unsigned long from, unsigned long to)
if (from == 0 || to == 0)
return X86_BR_NONE;
+ if (abort)
+ return X86_BR_ABORT | to_plm;
+
if (from_plm == X86_BR_USER) {
/*
* can happen if measuring at the user level only
@@ -577,7 +596,13 @@ intel_pmu_lbr_filter(struct cpu_hw_events *cpuc)
from = cpuc->lbr_entries[i].from;
to = cpuc->lbr_entries[i].to;
- type = branch_type(from, to);
+ type = branch_type(from, to, cpuc->lbr_entries[i].abort);
+ if (type != X86_BR_NONE && (br_sel & X86_BR_ANYTX)) {
+ if (cpuc->lbr_entries[i].intx)
+ type |= X86_BR_INTX;
+ else
+ type |= X86_BR_NOTX;
+ }
/* if type does not correspond, then discard */
if (type == X86_BR_NONE || (br_sel & type) != type) {
diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index 9fa9c62..41b25f0 100644
--- a/include/uapi/linux/perf_event.h
+++ b/include/uapi/linux/perf_event.h
@@ -155,8 +155,11 @@ enum perf_branch_sample_type {
PERF_SAMPLE_BRANCH_ANY_CALL = 1U << 4, /* any call branch */
PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << 5, /* any return branch */
PERF_SAMPLE_BRANCH_IND_CALL = 1U << 6, /* indirect calls */
+ PERF_SAMPLE_BRANCH_ABORTTX = 1U << 7, /* transaction aborts */
+ PERF_SAMPLE_BRANCH_INTX = 1U << 8, /* in transaction (flag) */
+ PERF_SAMPLE_BRANCH_NOTX = 1U << 9, /* not in transaction (flag) */
- PERF_SAMPLE_BRANCH_MAX = 1U << 7, /* non-ABI */
+ PERF_SAMPLE_BRANCH_MAX = 1U << 10, /* non-ABI */
};
#define PERF_SAMPLE_BRANCH_PLM_ALL \
--
1.7.7.6
next prev parent reply other threads:[~2013-01-25 22:02 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-01-25 22:00 Basic perf PMU support for Haswell v1 Andi Kleen
2013-01-25 22:00 ` [PATCH 01/12] perf, x86: Add PEBSv2 record support Andi Kleen
2013-01-28 13:15 ` Stephane Eranian
2013-01-28 16:10 ` Andi Kleen
2013-01-31 17:15 ` Stephane Eranian
2013-01-25 22:00 ` [PATCH 02/12] perf, x86: Basic Haswell PMU support v2 Andi Kleen
2013-01-28 15:34 ` Stephane Eranian
2013-01-28 16:16 ` Andi Kleen
2013-01-25 22:00 ` [PATCH 03/12] perf, x86: Basic Haswell PEBS support v3 Andi Kleen
2013-01-28 15:56 ` Stephane Eranian
2013-01-25 22:00 ` [PATCH 04/12] perf, x86: Support the TSX intx/intx_cp qualifiers v2 Andi Kleen
2013-01-26 11:54 ` Ingo Molnar
2013-01-26 21:00 ` Andi Kleen
2013-01-27 13:14 ` Ingo Molnar
[not found] ` <20130128050234.GQ30577@one.firstfloor.org>
2013-01-28 10:47 ` Ingo Molnar
2013-01-28 16:52 ` Stephane Eranian
2013-01-28 17:37 ` Andi Kleen
2013-01-25 22:00 ` [PATCH 05/12] perf, x86: Support Haswell v4 LBR format Andi Kleen
2013-01-28 21:47 ` Stephane Eranian
2013-01-28 22:08 ` Andi Kleen
2013-01-28 22:20 ` Stephane Eranian
2013-01-25 22:00 ` [PATCH 06/12] perf, x86: Support full width counting Andi Kleen
2013-01-25 22:00 ` [PATCH 07/12] perf, x86: Avoid checkpointed counters causing excessive TSX aborts v3 Andi Kleen
2013-01-28 22:32 ` Stephane Eranian
2013-01-28 23:16 ` Andi Kleen
2013-01-29 0:30 ` Stephane Eranian
2013-01-29 1:00 ` Andi Kleen
2013-01-30 8:51 ` Stephane Eranian
2013-01-30 20:58 ` Andi Kleen
2013-01-25 22:00 ` [PATCH 08/12] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset Andi Kleen
2013-01-25 22:00 ` [PATCH 09/12] perf, x86: Disable LBR recording for unknown LBR_FMT Andi Kleen
2013-01-25 22:00 ` Andi Kleen [this message]
2013-01-25 22:00 ` [PATCH 11/12] perf, tools: Support sorting by intx, abort branch flags v2 Andi Kleen
2013-01-25 22:00 ` [PATCH 12/12] perf, tools: Add abort_tx,no_tx,in_tx branch filter options to perf record -j v3 Andi Kleen
2013-01-31 17:19 ` Basic perf PMU support for Haswell v1 Stephane Eranian
2013-01-31 17:47 ` Andi Kleen
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