From: Tomasz Figa <tomasz.figa@gmail.com>
To: linux-samsung-soc@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org,
alsa-devel@alsa-project.org, "Kukjin Kim" <kgene.kim@samsung.com>,
"Vinod Koul" <vinod.koul@intel.com>, "Dan Williams" <djbw@fb.com>,
"Linus Walleij" <linus.walleij@linaro.org>,
"Alessandro Rubini" <rubini@gnudd.com>,
"Giancarlo Asnaghi" <giancarlo.asnaghi@st.com>,
"Mark Brown" <broonie@kernel.org>,
"Grant Likely" <grant.likely@linaro.org>,
"Sangbeom Kim" <sbkim73@samsung.com>,
"Liam Girdwood" <lgirdwood@gmail.com>,
"Jaroslav Kysela" <perex@perex.cz>,
"Takashi Iwai" <tiwai@suse.de>,
"Padmavathi Venna" <padma.v@samsung.com>,
"Thomas Abraham" <thomas.abraham@linaro.org>,
"Arnd Bergmann" <arnd@arndb.de>,
"Olof Johansson" <olof@lixom.net>,
"Heiko Stübner" <heiko@sntech.de>,
"Sylwester Nawrocki" <sylvester.nawrocki@gmail.com>,
"Russell King - ARM Linux" <linux@arm.linux.org.uk>,
"Alban Bedel" <alban.bedel@avionic-design.de>,
"Tomasz Figa" <tomasz.figa@gmail.com>
Subject: [RFC PATCH v2 02/12] dmaengine: PL08x: Add support for different offset of CONFIG register
Date: Sat, 22 Jun 2013 22:42:34 +0200 [thread overview]
Message-ID: <1371933764-24875-3-git-send-email-tomasz.figa@gmail.com> (raw)
In-Reply-To: <1371933764-24875-1-git-send-email-tomasz.figa@gmail.com>
Some variants of PL08x (namely PL080S, found in Samsung S3C64xx SoCs)
have CONFIG register at different offset. This patch makes the driver
use offset from vendor data struct.
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
---
drivers/dma/amba-pl08x.c | 30 ++++++++++++++++++------------
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 6a12392..2538e05 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -102,6 +102,7 @@ struct pl08x_driver_data;
* missing
*/
struct vendor_data {
+ u8 config_offset;
u8 channels;
bool dualmaster;
bool nomadik;
@@ -145,6 +146,7 @@ struct pl08x_bus_data {
struct pl08x_phy_chan {
unsigned int id;
void __iomem *base;
+ void __iomem *reg_config;
spinlock_t lock;
struct pl08x_dma_chan *serving;
bool locked;
@@ -334,7 +336,7 @@ static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
{
unsigned int val;
- val = readl(ch->base + PL080_CH_CONFIG);
+ val = readl(ch->reg_config);
return val & PL080_CONFIG_ACTIVE;
}
@@ -373,7 +375,7 @@ static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan)
writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
writel(lli->lli, phychan->base + PL080_CH_LLI);
writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
- writel(txd->ccfg, phychan->base + PL080_CH_CONFIG);
+ writel(txd->ccfg, phychan->reg_config);
/* Enable the DMA channel */
/* Do not access config register until channel shows as disabled */
@@ -381,11 +383,11 @@ static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan)
cpu_relax();
/* Do not access config register until channel shows as inactive */
- val = readl(phychan->base + PL080_CH_CONFIG);
+ val = readl(phychan->reg_config);
while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
- val = readl(phychan->base + PL080_CH_CONFIG);
+ val = readl(phychan->reg_config);
- writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG);
+ writel(val | PL080_CONFIG_ENABLE, phychan->reg_config);
}
/*
@@ -404,9 +406,9 @@ static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
int timeout;
/* Set the HALT bit and wait for the FIFO to drain */
- val = readl(ch->base + PL080_CH_CONFIG);
+ val = readl(ch->reg_config);
val |= PL080_CONFIG_HALT;
- writel(val, ch->base + PL080_CH_CONFIG);
+ writel(val, ch->reg_config);
/* Wait for channel inactive */
for (timeout = 1000; timeout; timeout--) {
@@ -423,9 +425,9 @@ static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
u32 val;
/* Clear the HALT bit */
- val = readl(ch->base + PL080_CH_CONFIG);
+ val = readl(ch->reg_config);
val &= ~PL080_CONFIG_HALT;
- writel(val, ch->base + PL080_CH_CONFIG);
+ writel(val, ch->reg_config);
}
/*
@@ -437,12 +439,12 @@ static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x,
struct pl08x_phy_chan *ch)
{
- u32 val = readl(ch->base + PL080_CH_CONFIG);
+ u32 val = readl(ch->reg_config);
val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK |
PL080_CONFIG_TC_IRQ_MASK);
- writel(val, ch->base + PL080_CH_CONFIG);
+ writel(val, ch->reg_config);
writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR);
writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR);
@@ -1952,6 +1954,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
ch->id = i;
ch->base = pl08x->base + PL080_Cx_BASE(i);
+ ch->reg_config = ch->base + vd->config_offset;
spin_lock_init(&ch->lock);
/*
@@ -1962,7 +1965,7 @@ static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
if (vd->nomadik) {
u32 val;
- val = readl(ch->base + PL080_CH_CONFIG);
+ val = readl(ch->reg_config);
if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) {
dev_info(&adev->dev, "physical channel %d reserved for secure access only\n", i);
ch->locked = true;
@@ -2043,17 +2046,20 @@ out_no_pl08x:
/* PL080 has 8 channels and the PL080 have just 2 */
static struct vendor_data vendor_pl080 = {
+ .config_offset = PL080_CH_CONFIG,
.channels = 8,
.dualmaster = true,
};
static struct vendor_data vendor_nomadik = {
+ .config_offset = PL080_CH_CONFIG,
.channels = 8,
.dualmaster = true,
.nomadik = true,
};
static struct vendor_data vendor_pl081 = {
+ .config_offset = PL080_CH_CONFIG,
.channels = 2,
.dualmaster = false,
};
--
1.8.2.1
next prev parent reply other threads:[~2013-06-22 20:43 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-06-22 20:42 [RFC PATCH v2 00/12] ARM: s3c64xx: Let amba-pl08x driver handle DMA Tomasz Figa
2013-06-22 20:42 ` [RFC PATCH v2 01/12] dmaengine: PL08x: Refactor pl08x_getbytes_chan() to lower indentation Tomasz Figa
2013-06-25 15:16 ` Vinod Koul
2013-06-25 18:30 ` Russell King - ARM Linux
2013-06-22 20:42 ` Tomasz Figa [this message]
2013-06-25 15:34 ` [RFC PATCH v2 02/12] dmaengine: PL08x: Add support for different offset of CONFIG register Vinod Koul
2013-06-22 20:42 ` [RFC PATCH v2 03/12] dmaengine: PL08x: Rework LLI handling to be less fragile Tomasz Figa
2013-06-22 20:42 ` [RFC PATCH v2 04/12] dmaengine: PL08x: Add support for PL080S variant Tomasz Figa
2013-06-22 20:42 ` [RFC PATCH v2 05/12] dmaengine: PL08x: Add support for different maximum transfer size Tomasz Figa
2013-06-25 16:10 ` Vinod Koul
2013-06-22 20:42 ` [RFC PATCH v2 06/12] dmaengine: PL08x: Fix reading the byte count in cctl Tomasz Figa
2013-06-22 20:42 ` [RFC PATCH v2 07/12] dmaengine: PL08x: Add cyclic transfer support Tomasz Figa
2013-06-22 20:42 ` [RFC PATCH v2 08/12] ASoC: Samsung: Do not queue cyclic buffers multiple times Tomasz Figa
2013-06-22 20:42 ` [RFC PATCH v2 09/12] clk: samsung: s3c64xx: Add aliases for DMA clocks Tomasz Figa
2013-06-22 20:42 ` [RFC PATCH v2 10/12] spi: s3c64xx: Do not require legacy DMA API in case of S3C64XX Tomasz Figa
2013-06-22 20:42 ` [RFC PATCH v2 11/12] ASoC: Samsung: " Tomasz Figa
2013-06-22 20:42 ` [RFC PATCH v2 12/12] ARM: s3c64xx: Add support for DMA using generic amba-pl08x driver Tomasz Figa
2013-06-25 10:28 ` [RFC PATCH v2 00/12] ARM: s3c64xx: Let amba-pl08x driver handle DMA Mark Brown
2013-06-25 11:22 ` Tomasz Figa
2013-06-25 15:38 ` Mark Brown
2013-06-25 15:44 ` Tomasz Figa
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