From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932156Ab3KXGe2 (ORCPT ); Sun, 24 Nov 2013 01:34:28 -0500 Received: from gnurou.org ([207.192.72.5]:41271 "EHLO mail.gnurou.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756639Ab3KXGeY (ORCPT ); Sun, 24 Nov 2013 01:34:24 -0500 From: Alexandre Courbot To: Russell King , Stephen Warren , Thierry Reding Cc: Tomasz Figa , Olof Johansson , Dave Martin , Kevin Hilman , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, gnurou@gmail.com, Alexandre Courbot Subject: [PATCH v11 5/7] ARM: tegra: split setting of CPU reset handler Date: Sun, 24 Nov 2013 15:30:50 +0900 Message-Id: <1385274652-16415-6-git-send-email-acourbot@nvidia.com> X-Mailer: git-send-email 1.8.4.2 In-Reply-To: <1385274652-16415-1-git-send-email-acourbot@nvidia.com> References: <1385274652-16415-1-git-send-email-acourbot@nvidia.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Not all Tegra devices can set the CPU reset handler in the same way. In particular, devices using a TrustZone secure monitor cannot set it up directly and need to ask the firmware to do it. This patch separates the act of setting the reset handler from its preparation, so the former can be implemented in a different way. Signed-off-by: Alexandre Courbot Reviewed-by: Tomasz Figa Reviewed-by: Stephen Warren --- arch/arm/mach-tegra/reset.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c index 568f5bb..17c4b6d 100644 --- a/arch/arm/mach-tegra/reset.c +++ b/arch/arm/mach-tegra/reset.c @@ -33,26 +33,18 @@ static bool is_enabled; -static void __init tegra_cpu_reset_handler_enable(void) +static void __init tegra_cpu_reset_handler_set(const u32 reset_address) { - void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE); void __iomem *evp_cpu_reset = IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100); void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE); u32 reg; - BUG_ON(is_enabled); - BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE); - - memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start, - tegra_cpu_reset_handler_size); - /* * NOTE: This must be the one and only write to the EVP CPU reset * vector in the entire system. */ - writel(TEGRA_IRAM_RESET_BASE + tegra_cpu_reset_handler_offset, - evp_cpu_reset); + writel(reset_address, evp_cpu_reset); wmb(); reg = readl(evp_cpu_reset); @@ -66,6 +58,21 @@ static void __init tegra_cpu_reset_handler_enable(void) writel(reg, sb_ctrl); wmb(); } +} + +static void __init tegra_cpu_reset_handler_enable(void) +{ + void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE); + const u32 reset_address = TEGRA_IRAM_RESET_BASE + + tegra_cpu_reset_handler_offset; + + BUG_ON(is_enabled); + BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE); + + memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start, + tegra_cpu_reset_handler_size); + + tegra_cpu_reset_handler_set(reset_address); is_enabled = true; } -- 1.8.4.2