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From: srinivas.kandagatla@linaro.org
To: linux-mmc@vger.kernel.org
Cc: Russell King <linux@arm.linux.org.uk>,
	Chris Ball <chris@printf.net>,
	Ulf Hansson <ulf.hansson@linaro.org>,
	linux-kernel@vger.kernel.org, agross@quicinc.com,
	linux-arm-msm@vger.kernel.org,
	Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Subject: [PATCH RFC 04/12] mmc: mmci: Add register read/write wrappers.
Date: Mon, 21 Apr 2014 22:47:46 +0100	[thread overview]
Message-ID: <1398116866-31357-1-git-send-email-srinivas.kandagatla@linaro.org> (raw)
In-Reply-To: <1398116624-31052-1-git-send-email-srinivas.kandagatla@linaro.org>

From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

This patch adds wrappers for readl/writel functions used in the driver. The
reason for this wrappers is to accommodate SOCs like Qualcomm which has
requirement for delaying the write for few cycles when writing to its SD Card
Controller registers.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 drivers/mmc/host/mmci.c |  114 +++++++++++++++++++++++++----------------------
 1 file changed, 61 insertions(+), 53 deletions(-)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 19d6b6f..36db31e 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -171,6 +171,16 @@ static struct variant_data variant_qcom = {
 	.pwrreg_powerup		= MCI_PWR_UP,
 };
 
+static inline u32 mmci_readl(struct mmci_host *host, u32 off)
+{
+	return readl(host->base  + off);
+}
+
+static inline void mmci_writel(struct mmci_host *host, u32 data, u32 off)
+{
+	writel(data, host->base + off);
+}
+
 static int mmci_card_busy(struct mmc_host *mmc)
 {
 	struct mmci_host *host = mmc_priv(mmc);
@@ -180,7 +190,7 @@ static int mmci_card_busy(struct mmc_host *mmc)
 	pm_runtime_get_sync(mmc_dev(mmc));
 
 	spin_lock_irqsave(&host->lock, flags);
-	if (readl(host->base + MMCISTATUS) & MCI_ST_CARDBUSY)
+	if (mmci_readl(host, MMCISTATUS) & MCI_ST_CARDBUSY)
 		busy = 1;
 	spin_unlock_irqrestore(&host->lock, flags);
 
@@ -230,7 +240,7 @@ static void mmci_write_clkreg(struct mmci_host *host, u32 clk)
 {
 	if (host->clk_reg != clk) {
 		host->clk_reg = clk;
-		writel(clk, host->base + MMCICLOCK);
+		mmci_writel(host, clk, MMCICLOCK);
 	}
 }
 
@@ -241,7 +251,7 @@ static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
 {
 	if (host->pwr_reg != pwr) {
 		host->pwr_reg = pwr;
-		writel(pwr, host->base + MMCIPOWER);
+		mmci_writel(host, pwr, MMCIPOWER);
 	}
 }
 
@@ -255,7 +265,7 @@ static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
 
 	if (host->datactrl_reg != datactrl) {
 		host->datactrl_reg = datactrl;
-		writel(datactrl, host->base + MMCIDATACTRL);
+		mmci_writel(host, datactrl, MMCIDATACTRL);
 	}
 }
 
@@ -321,7 +331,7 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
 static void
 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
 {
-	writel(0, host->base + MMCICOMMAND);
+	mmci_writel(host, 0, MMCICOMMAND);
 
 	BUG_ON(host->data);
 
@@ -336,18 +346,16 @@ mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
 
 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
 {
-	void __iomem *base = host->base;
-
 	if (host->singleirq) {
-		unsigned int mask0 = readl(base + MMCIMASK0);
+		unsigned int mask0 = mmci_readl(host, MMCIMASK0);
 
 		mask0 &= ~MCI_IRQ1MASK;
 		mask0 |= mask;
 
-		writel(mask0, base + MMCIMASK0);
+		mmci_writel(host, mask0, MMCIMASK0);
 	}
 
-	writel(mask, base + MMCIMASK1);
+	mmci_writel(host, mask, MMCIMASK1);
 }
 
 static void mmci_stop_data(struct mmci_host *host)
@@ -498,7 +506,7 @@ static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
 
 	/* Wait up to 1ms for the DMA to complete */
 	for (i = 0; ; i++) {
-		status = readl(host->base + MMCISTATUS);
+		status = mmci_readl(host, MMCISTATUS);
 		if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
 			break;
 		udelay(10);
@@ -637,8 +645,8 @@ static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
 	 * to fire next DMA request. When that happens, MMCI will
 	 * call mmci_data_end()
 	 */
-	writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
-	       host->base + MMCIMASK0);
+	mmci_writel(host, mmci_readl(host, MMCIMASK0) | MCI_DATAENDMASK,
+		    MMCIMASK0);
 	return 0;
 }
 
@@ -756,8 +764,8 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
 	timeout = data->timeout_clks + (unsigned int)clks;
 
 	base = host->base;
-	writel(timeout, base + MMCIDATATIMER);
-	writel(host->size, base + MMCIDATALENGTH);
+	mmci_writel(host, timeout, MMCIDATATIMER);
+	mmci_writel(host, host->size, MMCIDATALENGTH);
 
 	blksz_bits = ffs(data->blksz) - 1;
 	BUG_ON(1 << blksz_bits != data->blksz);
@@ -831,20 +839,19 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
 	}
 
 	mmci_write_datactrlreg(host, datactrl);
-	writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
+	mmci_writel(host, mmci_readl(host, MMCIMASK0) & ~MCI_DATAENDMASK,
+		    MMCIMASK0);
 	mmci_set_mask1(host, irqmask);
 }
 
 static void
 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
 {
-	void __iomem *base = host->base;
-
 	dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
 	    cmd->opcode, cmd->arg, cmd->flags);
 
-	if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
-		writel(0, base + MMCICOMMAND);
+	if (mmci_readl(host, MMCICOMMAND) & MCI_CPSM_ENABLE) {
+		mmci_writel(host, 0, MMCICOMMAND);
 		udelay(1);
 	}
 
@@ -859,8 +866,8 @@ mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
 
 	host->cmd = cmd;
 
-	writel(cmd->arg, base + MMCIARGUMENT);
-	writel(c, base + MMCICOMMAND);
+	mmci_writel(host, cmd->arg, MMCIARGUMENT);
+	mmci_writel(host, c, MMCICOMMAND);
 }
 
 static void
@@ -885,7 +892,7 @@ mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
 		 * can be as much as a FIFO-worth of data ahead.  This
 		 * matters for FIFO overruns only.
 		 */
-		remain = readl(host->base + MMCIDATACNT);
+		remain = mmci_readl(host, MMCIDATACNT);
 		success = data->blksz * data->blocks - remain;
 
 		dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
@@ -967,10 +974,10 @@ mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
 	} else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
 		cmd->error = -EILSEQ;
 	} else {
-		cmd->resp[0] = readl(base + MMCIRESPONSE0);
-		cmd->resp[1] = readl(base + MMCIRESPONSE1);
-		cmd->resp[2] = readl(base + MMCIRESPONSE2);
-		cmd->resp[3] = readl(base + MMCIRESPONSE3);
+		cmd->resp[0] = mmci_readl(host, MMCIRESPONSE0);
+		cmd->resp[1] = mmci_readl(host, MMCIRESPONSE1);
+		cmd->resp[2] = mmci_readl(host, MMCIRESPONSE2);
+		cmd->resp[3] = mmci_readl(host, MMCIRESPONSE3);
 	}
 
 	if ((!sbc && !cmd->data) || cmd->error) {
@@ -1081,11 +1088,10 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
 	struct mmci_host *host = dev_id;
 	struct sg_mapping_iter *sg_miter = &host->sg_miter;
 	struct variant_data *variant = host->variant;
-	void __iomem *base = host->base;
 	unsigned long flags;
 	u32 status;
 
-	status = readl(base + MMCISTATUS);
+	status = mmci_readl(host, MMCISTATUS);
 
 	dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
 
@@ -1125,7 +1131,7 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
 		if (remain)
 			break;
 
-		status = readl(base + MMCISTATUS);
+		status = mmci_readl(host, MMCISTATUS);
 	} while (1);
 
 	sg_miter_stop(sg_miter);
@@ -1147,7 +1153,9 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
 	 */
 	if (host->size == 0) {
 		mmci_set_mask1(host, 0);
-		writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
+		mmci_writel(host,
+			    mmci_readl(host, MMCIMASK0) | MCI_DATAENDMASK,
+			    MMCIMASK0);
 	}
 
 	return IRQ_HANDLED;
@@ -1168,10 +1176,10 @@ static irqreturn_t mmci_irq(int irq, void *dev_id)
 		struct mmc_command *cmd;
 		struct mmc_data *data;
 
-		status = readl(host->base + MMCISTATUS);
+		status = mmci_readl(host, MMCISTATUS);
 
 		if (host->singleirq) {
-			if (status & readl(host->base + MMCIMASK1))
+			if (status & mmci_readl(host, MMCIMASK1))
 				mmci_pio_irq(irq, dev_id);
 
 			status &= ~MCI_IRQ1MASK;
@@ -1182,8 +1190,8 @@ static irqreturn_t mmci_irq(int irq, void *dev_id)
 		 * enabled) since the HW seems to be triggering the IRQ on both
 		 * edges while monitoring DAT0 for busy completion.
 		 */
-		status &= readl(host->base + MMCIMASK0);
-		writel(status, host->base + MMCICLEAR);
+		status &= mmci_readl(host, MMCIMASK0);
+		mmci_writel(host, status, MMCICLEAR);
 
 		dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
 
@@ -1627,9 +1635,9 @@ static int mmci_probe(struct amba_device *dev,
 
 	spin_lock_init(&host->lock);
 
-	writel(0, host->base + MMCIMASK0);
-	writel(0, host->base + MMCIMASK1);
-	writel(0xfff, host->base + MMCICLEAR);
+	mmci_writel(host, 0, MMCIMASK0);
+	mmci_writel(host, 0, MMCIMASK1);
+	mmci_writel(host, 0xfff, MMCICLEAR);
 
 	if (plat->gpio_cd == -EPROBE_DEFER) {
 		ret = -EPROBE_DEFER;
@@ -1689,7 +1697,7 @@ static int mmci_probe(struct amba_device *dev,
 			goto irq0_free;
 	}
 
-	writel(MCI_IRQENABLE, host->base + MMCIMASK0);
+	mmci_writel(host, MCI_IRQENABLE, MMCIMASK0);
 
 	amba_set_drvdata(dev, mmc);
 
@@ -1745,11 +1753,11 @@ static int mmci_remove(struct amba_device *dev)
 
 		mmc_remove_host(mmc);
 
-		writel(0, host->base + MMCIMASK0);
-		writel(0, host->base + MMCIMASK1);
+		mmci_writel(host, 0, MMCIMASK0);
+		mmci_writel(host, 0, MMCIMASK1);
 
-		writel(0, host->base + MMCICOMMAND);
-		writel(0, host->base + MMCIDATACTRL);
+		mmci_writel(host, 0, MMCICOMMAND);
+		mmci_writel(host, 0, MMCIDATACTRL);
 
 		mmci_dma_release(host);
 		free_irq(dev->irq[0], host);
@@ -1783,7 +1791,7 @@ static int mmci_suspend(struct device *dev)
 	if (mmc) {
 		struct mmci_host *host = mmc_priv(mmc);
 		pm_runtime_get_sync(dev);
-		writel(0, host->base + MMCIMASK0);
+		mmci_writel(host, 0, MMCIMASK0);
 	}
 
 	return 0;
@@ -1796,7 +1804,7 @@ static int mmci_resume(struct device *dev)
 
 	if (mmc) {
 		struct mmci_host *host = mmc_priv(mmc);
-		writel(MCI_IRQENABLE, host->base + MMCIMASK0);
+		mmci_writel(host, MCI_IRQENABLE, MMCIMASK0);
 		pm_runtime_put(dev);
 	}
 
@@ -1812,10 +1820,10 @@ static void mmci_save(struct mmci_host *host)
 	if (host->variant->pwrreg_nopower) {
 		spin_lock_irqsave(&host->lock, flags);
 
-		writel(0, host->base + MMCIMASK0);
-		writel(0, host->base + MMCIDATACTRL);
-		writel(0, host->base + MMCIPOWER);
-		writel(0, host->base + MMCICLOCK);
+		mmci_writel(host, 0, MMCIMASK0);
+		mmci_writel(host, 0, MMCIDATACTRL);
+		mmci_writel(host, 0, MMCIPOWER);
+		mmci_writel(host, 0, MMCICLOCK);
 		mmci_reg_delay(host);
 
 		spin_unlock_irqrestore(&host->lock, flags);
@@ -1830,10 +1838,10 @@ static void mmci_restore(struct mmci_host *host)
 	if (host->variant->pwrreg_nopower) {
 		spin_lock_irqsave(&host->lock, flags);
 
-		writel(host->clk_reg, host->base + MMCICLOCK);
-		writel(host->datactrl_reg, host->base + MMCIDATACTRL);
-		writel(host->pwr_reg, host->base + MMCIPOWER);
-		writel(MCI_IRQENABLE, host->base + MMCIMASK0);
+		mmci_writel(host, host->clk_reg, MMCICLOCK);
+		mmci_writel(host, host->datactrl_reg, MMCIDATACTRL);
+		mmci_writel(host, host->pwr_reg, MMCIPOWER);
+		mmci_writel(host, MCI_IRQENABLE, MMCIMASK0);
 		mmci_reg_delay(host);
 
 		spin_unlock_irqrestore(&host->lock, flags);
-- 
1.7.9.5


  parent reply	other threads:[~2014-04-21 21:48 UTC|newest]

Thread overview: 96+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-04-21 21:43 [PATCH RFC 00/12] Add Qualcomm SD Card Controller support srinivas.kandagatla
2014-04-21 21:47 ` [PATCH RFC 01/12] ARM: amba: Add Qualcomm vendor ID srinivas.kandagatla
2014-04-21 21:47 ` [PATCH RFC 02/12] mmc: mmci: Add Qualcomm Id to amba id table srinivas.kandagatla
2014-04-21 21:47 ` [PATCH RFC 03/12] mmc: mmci: Add Qcom datactrl register variant srinivas.kandagatla
2014-04-21 21:47 ` srinivas.kandagatla [this message]
2014-04-21 21:47 ` [PATCH RFC 05/12] mmc: mmci: use NSEC_PER_SEC macro srinivas.kandagatla
2014-04-21 21:48 ` [PATCH RFC 06/12] mmc: mmci: Add write delay to variant structure srinivas.kandagatla
2014-04-21 22:08   ` Felipe Balbi
2014-04-22  8:15     ` Srinivas Kandagatla
2014-04-21 21:48 ` [PATCH RFC 07/12] mmc: mmci: Qcomm: Add 3 clock cycle delay after each register write srinivas.kandagatla
2014-04-21 21:48 ` [PATCH RFC 08/12] mmc: mmci: move ST specific register extensions access under condition srinivas.kandagatla
2014-04-21 21:48 ` [PATCH RFC 09/12] mmc: mmci: Qcom fix MCICLK register settings srinivas.kandagatla
2014-04-21 21:49 ` [PATCH RFC 10/12] mmc: mmci: Add clock support for Qualcomm srinivas.kandagatla
2014-04-21 22:20   ` Stephen Boyd
2014-04-22 10:03     ` Srinivas Kandagatla
2014-04-21 21:49 ` [PATCH RFC 11/12] mmc: mmci: Add Qcom variations to MCICommand register srinivas.kandagatla
2014-04-21 21:49 ` [PATCH RFC 12/12] mmc: mmci: Add Qcom specific pio_read function srinivas.kandagatla
2014-04-22 12:58 ` [PATCH RFC 00/12] Add Qualcomm SD Card Controller support Christopher Covington
2014-04-22 14:16   ` Srinivas Kandagatla
2014-04-29  8:18 ` [PATCH v1 00/11] " srinivas.kandagatla
2014-04-29  8:19   ` [PATCH v1 01/11] ARM: amba: Add Qualcomm vendor ID srinivas.kandagatla
2014-05-13  7:16     ` Linus Walleij
2014-05-13  9:41       ` Srinivas Kandagatla
2014-05-13 22:13         ` Stephen Boyd
2014-05-14  6:45           ` Srinivas Kandagatla
2014-05-16 16:24           ` Linus Walleij
2014-05-16 16:43             ` Stephen Boyd
2014-05-22 21:54               ` Linus Walleij
2014-04-29  8:19   ` [PATCH v1 02/11] mmc: mmci: Add Qualcomm Id to amba id table srinivas.kandagatla
2014-05-13  7:17     ` Linus Walleij
2014-05-13  9:00       ` Srinivas Kandagatla
2014-04-29  8:19   ` [PATCH v1 03/11] mmc: mmci: Add Qcom datactrl register variant srinivas.kandagatla
2014-05-13  7:19     ` Linus Walleij
2014-04-29  8:19   ` [PATCH v1 04/11] mmc: mmci: Add register read/write wrappers srinivas.kandagatla
2014-04-29  8:20   ` [PATCH v1 05/11] mmc: mmci: use NSEC_PER_SEC macro srinivas.kandagatla
2014-05-13  7:20     ` Linus Walleij
2014-05-13  9:02       ` Srinivas Kandagatla
2014-04-29  8:20   ` [PATCH v1 06/11] mmc: mmci: Qcomm: Add 3 clock cycle delay after register write srinivas.kandagatla
2014-05-13  7:29     ` Linus Walleij
2014-05-13  9:14       ` Srinivas Kandagatla
2014-04-29  8:20   ` [PATCH v1 07/11] mmc: mmci: move ST specific register extensions access under condition srinivas.kandagatla
2014-05-13  8:08     ` Linus Walleij
2014-05-13  9:33       ` Srinivas Kandagatla
2014-04-29  8:20   ` [PATCH v1 08/11] mmc: mmci: Qcom fix MCICLK register settings srinivas.kandagatla
2014-05-13  8:19     ` Linus Walleij
2014-05-13  9:36       ` Srinivas Kandagatla
2014-04-29  8:20   ` [PATCH v1 09/11] mmc: mmci: Add clock support for Qualcomm srinivas.kandagatla
2014-05-13  8:28     ` Linus Walleij
2014-05-13  9:39       ` Srinivas Kandagatla
2014-04-29  8:21   ` [PATCH v1 10/11] mmc: mmci: Add Qcom variations to MCICommand register srinivas.kandagatla
2014-05-13  8:29     ` Linus Walleij
2014-04-29  8:21   ` [PATCH v1 11/11] mmc: mmci: Add Qcom specific pio_read function srinivas.kandagatla
2014-05-13  8:34     ` Linus Walleij
2014-05-13  9:42       ` Srinivas Kandagatla
2014-05-09 17:56   ` [PATCH v1 00/11] Add Qualcomm SD Card Controller support Bjorn Andersson
2014-05-09 18:32     ` Srinivas Kandagatla
2014-05-13 10:04   ` Ulf Hansson
2014-05-13 10:21     ` Srinivas Kandagatla
2014-05-15  9:34 ` [PATCH v2 00/14] " srinivas.kandagatla
2014-05-15  9:36   ` [PATCH v2 01/14] mmc: mmci: use NSEC_PER_SEC macro srinivas.kandagatla
2014-05-15  9:36   ` [PATCH v2 02/14] mmc: mmci: convert register bits to use BIT() macro srinivas.kandagatla
2014-05-15  9:36   ` [PATCH v2 03/14] mmc: mmci: Add Qualcomm Id to amba id table srinivas.kandagatla
2014-05-15  9:36   ` [PATCH v2 04/14] mmc: mmci: Add Qcom datactrl register variant srinivas.kandagatla
2014-05-15  9:36   ` [PATCH v2 05/14] mmc: mmci: Add register read/write wrappers srinivas.kandagatla
2014-05-23  9:04     ` Linus Walleij
2014-05-15  9:37   ` [PATCH v2 06/14] mmc: mmci: Qcomm: Add 3 clock cycle delay after register write srinivas.kandagatla
2014-05-23  9:03     ` Linus Walleij
2014-05-15  9:37   ` [PATCH v2 07/14] mmc: mmci: add ddrmode mask to variant data srinivas.kandagatla
2014-05-23  9:05     ` Linus Walleij
2014-05-15  9:37   ` [PATCH v2 08/14] mmc: mmci: add 8bit bus support in " srinivas.kandagatla
2014-05-23  9:05     ` Linus Walleij
2014-05-15  9:37   ` [PATCH v2 09/14] mmc: mmci: add edge support to data and command out " srinivas.kandagatla
2014-05-23  9:06     ` Linus Walleij
2014-05-15  9:37   ` [PATCH v2 10/14] mmc: mmci: add Qcom specifics of clk and datactrl registers srinivas.kandagatla
2014-05-23  9:08     ` Linus Walleij
2014-05-15  9:37   ` [PATCH v2 11/14] mmc: mmci: Add support to data commands via variant structure srinivas.kandagatla
2014-05-23  9:09     ` Linus Walleij
2014-05-23  9:10       ` Srinivas Kandagatla
2014-05-15  9:37   ` [PATCH v2 12/14] mmc: mmci: add support for fbclk to latch data and cmd srinivas.kandagatla
2014-05-23  9:12     ` Linus Walleij
2014-05-23  9:20       ` Srinivas Kandagatla
2014-05-15  9:37   ` [PATCH v2 13/14] mmc: mmci: add qcom specific clk control srinivas.kandagatla
2014-05-23  9:14     ` Linus Walleij
2014-05-15  9:38   ` [PATCH v2 14/14] mmc: mmci: Add Qcom specific pio_read function srinivas.kandagatla
2014-05-23  9:31     ` Linus Walleij
2014-05-23  9:42       ` Srinivas Kandagatla
2014-05-23 11:53       ` Srinivas Kandagatla
2014-05-23  7:13   ` [PATCH v2 00/14] Add Qualcomm SD Card Controller support Srinivas Kandagatla
2014-05-23  7:50     ` Ulf Hansson
2014-05-23  8:11       ` Srinivas Kandagatla
2014-05-23 15:20         ` Bjorn Andersson
2014-05-23 16:50           ` Srinivas Kandagatla
2014-05-23 23:26             ` Bjorn Andersson
2014-05-24  7:32               ` Srinivas Kandagatla
2014-05-19 22:08 ` [PATCH RFC 00/12] " Bjorn Andersson
2014-05-20  8:10   ` Srinivas Kandagatla

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