From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755957AbaD2HVx (ORCPT ); Tue, 29 Apr 2014 03:21:53 -0400 Received: from mail-wg0-f52.google.com ([74.125.82.52]:45125 "EHLO mail-wg0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755814AbaD2HVv (ORCPT ); Tue, 29 Apr 2014 03:21:51 -0400 From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: lee.jones@linaro.org, kernel@stlinux.com, Kishon Vijay Abraham I Subject: [PATCH 1/4] phy: miphy365x: Add Device Tree bindings for the MiPHY365x Date: Tue, 29 Apr 2014 08:21:31 +0100 Message-Id: <1398756095-32542-2-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1398756095-32542-1-git-send-email-lee.jones@linaro.org> References: <1398756095-32542-1-git-send-email-lee.jones@linaro.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The MiPHY365x is a Generic PHY which can serve various SATA or PCIe devices. It has 2 ports which it can use for either; both SATA, both PCIe or one of each in any configuration. Cc: Kishon Vijay Abraham I Acked-by: Mark Rutland Acked-by: Alexandre Torgue Signed-off-by: Lee Jones --- .../devicetree/bindings/phy/phy-miphy365x.txt | 62 ++++++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-miphy365x.txt diff --git a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt new file mode 100644 index 0000000..cb39de1 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt @@ -0,0 +1,62 @@ +STMicroelectronics STi MIPHY365x PHY binding +============================================ + +This binding describes a miphy device that is used to control PHY hardware +for SATA and PCIe. + +Required properties: +- compatible : Should be "st,miphy365x-phy" +- #phy-cells : Should be 2 (See second example) + First cell is the port number from: + - MIPHY_PORT_0 + - MIPHY_PORT_1 + Second cell is device type from: + - MIPHY_TYPE_SATA + - MIPHY_TYPE_PCI +- reg : Address and length of register sets for each device in + "reg-names" +- reg-names : The names of the register addresses corresponding to the + registers filled in "reg", from: + - sata0: For SATA port 0 registers + - sata1: For SATA port 1 registers + - pcie0: For PCIE port 0 registers + - pcie1: For PCIE port 1 registers +- st,syscfg : Should be a phandle of the system configuration register group + which contain the SATA, PCIe mode setting bits + +Optional properties: +- st,sata-gen : Generation of locally attached SATA IP. Expected values + are {1,2,3). If not supplied generation 1 hardware will + be expected +- st,pcie-tx-pol-inv : Bool property to invert the polarity PCIe Tx (Txn/Txp) +- st,sata-tx-pol-inv : Bool property to invert the polarity SATA Tx (Txn/Txp) + +Example: + + miphy365x_phy: miphy365x@fe382000 { + compatible = "st,miphy365x-phy"; + #phy-cells = <2>; + reg = <0xfe382000 0x100>, + <0xfe38a000 0x100>, + <0xfe394000 0x100>, + <0xfe804000 0x100>; + reg-names = "sata0", "sata1", "pcie0", "pcie1"; + st,syscfg = <&syscfg_rear>; + }; + +Specifying phy control of devices +================================= + +Device nodes should specify the configuration required in their "phys" +property, containing a phandle to the miphy device node, a port number +and a device type. + +Example: + +#include + + sata0: sata@fe380000 { + ... + phys = <&miphy365x_phy MIPHY_PORT_0 MIPHY_TYPE_SATA>; + ... + }; -- 1.8.3.2