From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753446AbaEOAdo (ORCPT ); Wed, 14 May 2014 20:33:44 -0400 Received: from mail-vc0-f201.google.com ([209.85.220.201]:50145 "EHLO mail-vc0-f201.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752860AbaEOAdU (ORCPT ); Wed, 14 May 2014 20:33:20 -0400 From: Andrew Bresticker To: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org Cc: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Stephen Warren , Thierry Reding , Russell King , Peter De Schrijver , Prashant Gaikwad , Mike Turquette , Kishon Vijay Abraham I , Greg Kroah-Hartman , Mathias Nyman , Grant Likely , Randy Dunlap , Andrew Bresticker Subject: [RFC PATCH 09/10] ARM: tegra124: Add XHCI controller and PHY Date: Wed, 14 May 2014 17:33:05 -0700 Message-Id: <1400113986-339-10-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 1.9.1.423.g4596e3a In-Reply-To: <1400113986-339-1-git-send-email-abrestic@chromium.org> References: <1400113986-339-1-git-send-email-abrestic@chromium.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org And nodes for the XHCI host controller and XUSB PHY present on Tegra124. Signed-off-by: Andrew Bresticker --- arch/arm/boot/dts/tegra124.dtsi | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 47fb61c..ee3209bc 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -462,6 +462,43 @@ clock-names = "pclk", "clk32k_in"; }; + usb@0,70090000 { + compatible = "nvidia,tegra124-xhci"; + reg = <0x0 0x70090000 0x0 0x8000>, + <0x0 0x70098000 0x0 0x1000>, + <0x0 0x70099000 0x0 0x1000>; + interrupts = , + ; + clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, + <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>; + clock-names = "xusb_host", "xusb_falcon_src"; + resets = <&tegra_car 89>; + reset-names = "xusb_host"; + phys = <&xusb_phy>; + phy-names = "xusb"; + status = "disabled"; + }; + + xusb_phy: phy@0,7009f000 { + compatible = "nvidia,tegra124-xusb-phy"; + reg = <0x0 0x7009f000 0x0 0x1000>; + #phy-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_XUSB_SS>, + <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, + <&tegra_car TEGRA124_CLK_PLL_U_480M>, + <&tegra_car TEGRA124_CLK_CLK_M>, + <&tegra_car TEGRA124_CLK_PLL_E>; + clock-names = "xusb_ss", "xusb_ss_src", "xusb_hs_src", + "xusb_fs_src", "pll_u_480M", "clk_m", + "pll_e"; + resets = <&tegra_car 156>; + reset-names = "xusb_ss"; + nvidia,clkrst = <&tegra_car>; + status = "disabled"; + }; + sdhci@0,700b0000 { compatible = "nvidia,tegra124-sdhci"; reg = <0x0 0x700b0000 0x0 0x200>; -- 1.9.1.423.g4596e3a