From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934829AbaE3W3J (ORCPT ); Fri, 30 May 2014 18:29:09 -0400 Received: from mail-ig0-f171.google.com ([209.85.213.171]:42575 "EHLO mail-ig0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756272AbaE3W3G (ORCPT ); Fri, 30 May 2014 18:29:06 -0400 From: Alex Elder To: mporter@linaro.org, bcm@fixthebug.org, linux@arm.linux.org.uk, devicetree@vger.kernel.org, arnd@arndb.de, sboyd@codeaurora.org Cc: bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, galak@codeaurora.org, ijc+devicetree@hellion.org.uk, jason@lakedaemon.net, lorenzo.pieralisi@arm.com, mark.rutland@arm.com, pawel.moll@arm.com, rdunlap@infradead.org, rjui@broadcom.com, robh+dt@kernel.org, rvaswani@codeaurora.org Subject: [PATCH v4 RESEND 4/5] ARM: dts: enable SMP support for bcm28155 Date: Fri, 30 May 2014 17:28:55 -0500 Message-Id: <1401488936-21186-5-git-send-email-elder@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1401488936-21186-1-git-send-email-elder@linaro.org> References: <1401488936-21186-1-git-send-email-elder@linaro.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Define nodes representing the two Cortex A9 CPUs in a bcm28155 SoC. Signed-off-by: Ray Jui Signed-off-by: Alex Elder --- arch/arm/boot/dts/bcm11351.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index 64d069b..61372a6 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -27,6 +27,25 @@ bootargs = "console=ttyS0,115200n8"; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "brcm,bcm11351-cpu-method"; + secondary-boot-reg = <0x3500417c>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + }; + }; + gic: interrupt-controller@3ff00100 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; -- 1.9.1