From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758139AbaFSP6u (ORCPT ); Thu, 19 Jun 2014 11:58:50 -0400 Received: from mail-wg0-f49.google.com ([74.125.82.49]:41726 "EHLO mail-wg0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757906AbaFSP6r (ORCPT ); Thu, 19 Jun 2014 11:58:47 -0400 From: Stephane Eranian To: linux-kernel@vger.kernel.org Cc: peterz@infradead.org, mingo@elte.hu, ak@linux.intel.com, jmario@redhat.com, dzickus@redhat.com, jolsa@redhat.com, acme@redhat.com Subject: [PATCH 1/2] perf/x86: update Haswell PEBS event constraints Date: Thu, 19 Jun 2014 17:58:28 +0200 Message-Id: <1403193509-22393-2-git-send-email-eranian@google.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1403193509-22393-1-git-send-email-eranian@google.com> References: <1403193509-22393-1-git-send-email-eranian@google.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The following events support PEBS for all umasks, thus use INTEL_EVENT_CONSTRAINT() instead of INTEL_UEVENT_CONSTRAINT(): 0xd1 MEM_LOAD_UOPS_RETIRED 0xd2 MEM_LOAD_UOPS_LLC_HIT_RETIRED 0xd3 MEM_LOAD_UOPS_LLC_MISS_RETIRED For event 0xd0 (MEM_UOPS_RETIRED), the same is true, except we need to distinguish precise store (umask 0x82) from load latency events, thus we keep the breakdown per umask. But all umasks do support PEBS. Signed-off-by: Stephane Eranian --- arch/x86/kernel/cpu/perf_event_intel_ds.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c index 980970c..46d4def 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c @@ -672,17 +672,11 @@ struct event_constraint intel_hsw_pebs_event_constraints[] = { INTEL_UEVENT_CONSTRAINT(0x42d0, 0xf), INTEL_UEVENT_CONSTRAINT(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */ INTEL_PST_HSW_CONSTRAINT(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */ - INTEL_UEVENT_CONSTRAINT(0x01d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L1_HIT */ - INTEL_UEVENT_CONSTRAINT(0x02d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L2_HIT */ - INTEL_UEVENT_CONSTRAINT(0x04d1, 0xf), /* MEM_LOAD_UOPS_RETIRED.L3_HIT */ - /* MEM_LOAD_UOPS_RETIRED.HIT_LFB */ - INTEL_UEVENT_CONSTRAINT(0x40d1, 0xf), - /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS */ - INTEL_UEVENT_CONSTRAINT(0x01d2, 0xf), - /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT */ - INTEL_UEVENT_CONSTRAINT(0x02d2, 0xf), - /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM */ - INTEL_UEVENT_CONSTRAINT(0x01d3, 0xf), + INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ + /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ + INTEL_EVENT_CONSTRAINT(0xd2, 0xf), + /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */ + INTEL_EVENT_CONSTRAINT(0xd3, 0xf), INTEL_UEVENT_CONSTRAINT(0x04c8, 0xf), /* HLE_RETIRED.Abort */ INTEL_UEVENT_CONSTRAINT(0x04c9, 0xf), /* RTM_RETIRED.Abort */ -- 1.7.9.5