From: Tomasz Figa <t.figa@samsung.com>
To: linux-samsung-soc@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org,
Kukjin Kim <kgene.kim@samsung.com>,
Laura Abbott <lauraa@codeaurora.org>,
Linus Walleij <linus.walleij@linaro.org>,
Russell King - ARM Linux <linux@arm.linux.org.uk>,
Santosh Shilimkar <santosh.shilimkar@ti.com>,
Tony Lindgren <tony@atomide.com>,
Tomasz Figa <tomasz.figa@gmail.com>,
Daniel Drake <drake@endlessm.com>,
Marek Szyprowski <m.szyprowski@samsung.com>,
Tomasz Figa <t.figa@samsung.com>
Subject: [PATCH v2 6/6] ARM: dts: exynos4: Add nodes for L2 cache controller
Date: Wed, 25 Jun 2014 15:37:31 +0200 [thread overview]
Message-ID: <1403703451-12233-7-git-send-email-t.figa@samsung.com> (raw)
In-Reply-To: <1403703451-12233-1-git-send-email-t.figa@samsung.com>
This patch adds device tree nodes for L2 cache controller present on
Exynos4 SoCs.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
---
arch/arm/boot/dts/exynos4210.dtsi | 9 +++++++++
arch/arm/boot/dts/exynos4x12.dtsi | 14 ++++++++++++++
2 files changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index ee3001f..99970ab 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -54,6 +54,15 @@
reg = <0x10023CA0 0x20>;
};
+ l2c: l2-cache-controller@10502000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x10502000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ arm,tag-latency = <2 2 1>;
+ arm,data-latency = <2 2 1>;
+ };
+
gic: interrupt-controller@10490000 {
cpu-offset = <0x8000>;
};
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index c5a943d..ddffefe 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -60,6 +60,20 @@
reg = <0x10023CA0 0x20>;
};
+ l2c: l2-cache-controller@10502000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x10502000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ arm,tag-latency = <2 2 1>;
+ arm,data-latency = <3 2 1>;
+ arm,double-linefill = <1>;
+ arm,double-linefill-incr = <0>;
+ arm,double-linefill-wrap = <1>;
+ arm,prefetch-drop = <1>;
+ arm,prefetch-offset = <7>;
+ };
+
clock: clock-controller@10030000 {
compatible = "samsung,exynos4412-clock";
reg = <0x10030000 0x20000>;
--
1.9.3
next prev parent reply other threads:[~2014-06-25 13:39 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-25 13:37 [PATCH v2 0/6] Enable L2 cache support on Exynos4210/4x12 SoCs Tomasz Figa
2014-06-25 13:37 ` [PATCH v2 1/6] ARM: mm: cache-l2x0: Add base address argument to write_sec callback Tomasz Figa
2014-06-27 7:44 ` Linus Walleij
2014-06-25 13:37 ` [PATCH v2 2/6] ARM: Get outer cache .write_sec callback from mach_desc only if not NULL Tomasz Figa
2014-06-25 13:37 ` [PATCH v2 3/6] ARM: mm: cache-l2x0: Use l2c_write_sec() for LATENCY_CTRL registers Tomasz Figa
2014-06-25 13:37 ` [PATCH v2 4/6] ARM: mm: l2x0: Add support for overriding prefetch settings Tomasz Figa
2014-06-25 13:37 ` [PATCH v2 5/6] ARM: EXYNOS: Add .write_sec outer cache callback for L2C-310 Tomasz Figa
2014-06-25 13:37 ` Tomasz Figa [this message]
2014-06-25 13:50 ` [PATCH v2 0/6] Enable L2 cache support on Exynos4210/4x12 SoCs Russell King - ARM Linux
2014-06-25 14:13 ` Tomasz Figa
2014-06-25 14:37 ` Russell King - ARM Linux
2014-06-25 15:46 ` Tomasz Figa
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