From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751946AbaHROOQ (ORCPT ); Mon, 18 Aug 2014 10:14:16 -0400 Received: from mail-wi0-f174.google.com ([209.85.212.174]:55459 "EHLO mail-wi0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751714AbaHRON1 (ORCPT ); Mon, 18 Aug 2014 10:13:27 -0400 From: Daniel Thompson To: Russell King Cc: Daniel Thompson , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kgdb-bugreport@lists.sourceforge.net, patches@linaro.org, linaro-kernel@lists.linaro.org, John Stultz , Anton Vorontsov , Colin Cross , kernel-team@android.com, Rob Herring , Linus Walleij , Ben Dooks , Catalin Marinas , Dave Martin , Fabio Estevam , Frederic Weisbecker , Nicolas Pitre , Thomas Gleixner , Jason Cooper Subject: [PATCH v9 10/16] irqchip: gic: Group 0 workaround. Date: Mon, 18 Aug 2014 15:12:58 +0100 Message-Id: <1408371184-12576-11-git-send-email-daniel.thompson@linaro.org> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1404979427-12943-1-git-send-email-daniel.thompson@linaro.org> References: <1404979427-12943-1-git-send-email-daniel.thompson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org An ARM system based on GICv1 that runs by default in secure mode and uses both group 0 and group 1 interrupts (in order to exploit FIQ) will suffer a problem where the IRQ handler occasionally spuriously acknowledges a group 0 (FIQ) interrupt. This can be prevented by ensuring the IRQ handler makes non-secure memory access to the GIC registers but this is complex because the non-secure bits cannot be apply to 4k pages (the bit is one level up in the page table and applies to 1MB at a time). This workaround uses an alternative approach that spots the spurious acknowledgment and regenerates the FIQ. This keeps the workaround exclusively within the GIC driver (although there is a runtime perforamnce penalty resulting from this approach). Reported-by: Harro Haan Signed-off-by: Daniel Thompson Tested-by: Harro Haan Cc: Thomas Gleixner Cc: Jason Cooper --- drivers/irqchip/irq-gic.c | 52 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 49 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c index 3fa824e..a670e72 100644 --- a/drivers/irqchip/irq-gic.c +++ b/drivers/irqchip/irq-gic.c @@ -279,14 +279,59 @@ static int gic_set_wake(struct irq_data *d, unsigned int on) #define gic_set_wake NULL #endif +#ifdef CONFIG_FIQ +/* This is a software emulation of the Aliased Interrupt Acknowledge Register + * (GIC_AIAR) found in GICv2+. + */ +static u32 gic_handle_spurious_group_0(struct gic_chip_data *gic, u32 irqstat) +{ + u32 irqnr = irqstat & GICC_IAR_INT_ID_MASK; + void __iomem *dist_base = gic_data_dist_base(gic); + u32 offset, mask; + + if (!gic_data_fiq_enable(gic) || irqnr >= 1021) + return irqstat; + + offset = irqnr / 32 * 4; + mask = 1 << (irqnr % 32); + if (readl_relaxed(dist_base + GIC_DIST_IGROUP + offset) & mask) + return irqstat; + + /* this interrupt must be taken as a FIQ so put it back into the + * pending state and end our own servicing of it. + */ + writel_relaxed(mask, dist_base + GIC_DIST_PENDING_SET + offset); + readl_relaxed(dist_base + GIC_DIST_PENDING_SET + offset); + writel_relaxed(irqstat, gic_data_cpu_base(gic) + GIC_CPU_EOI); + + return 1023; +} + +static u32 gic_ack_irq(struct gic_chip_data *gic) +{ + u32 irqstat; + + local_fiq_disable(); + irqstat = readl_relaxed(gic_data_cpu_base(gic) + GIC_CPU_INTACK); + irqstat = gic_handle_spurious_group_0(gic, irqstat); + local_fiq_enable(); + + return irqstat; +} +#else +static u32 gic_ack_irq(struct gic_chip_data *gic) +{ + return readl_relaxed(gic_data_cpu_base(gic) + GIC_CPU_INTACK); +} +#endif + static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) { u32 irqstat, irqnr; struct gic_chip_data *gic = &gic_data[0]; - void __iomem *cpu_base = gic_data_cpu_base(gic); do { - irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); + irqstat = gic_ack_irq(gic); irqnr = irqstat & GICC_IAR_INT_ID_MASK; if (likely(irqnr > 15 && irqnr < 1021)) { @@ -295,7 +340,8 @@ static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) continue; } if (irqnr < 16) { - writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); + writel_relaxed(irqstat, + gic_data_cpu_base(gic) + GIC_CPU_EOI); #ifdef CONFIG_SMP handle_IPI(irqnr, regs); #endif -- 1.9.3