From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755931AbaISF4L (ORCPT ); Fri, 19 Sep 2014 01:56:11 -0400 Received: from regular1.263xmail.com ([211.150.99.130]:57915 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750865AbaISF4I (ORCPT ); Fri, 19 Sep 2014 01:56:08 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-RL-SENDER: mark.yao@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 127.0.0.1 X-LOGIN-NAME: mark.yao@rock-chips.com X-UNIQUE-TAG: <45fefecd85ae5e1dacefac5d7d094901> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 1 From: Mark yao To: heiko@sntech.de, Boris BREZILLON , David Airlie , Rob Clark , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Randy Dunlap , Grant Likely , Greg Kroah-Hartman , John Stultz , Rom Lemarchand Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-api@vger.kernel.org, linux-rockchip@lists.infradead.org, dianders@chromium.org, marcheu@chromium.org, dbehr@chromium.org, olof@lixom.net, djkurtz@chromium.org, xjq@rock-chips.com, kfx@rock-chips.com, cym@rock-chips.com, cf@rock-chips.com, zyw@rock-chips.com, xxm@rock-chips.com, huangtao@rock-chips.com, kever.yang@rock-chips.com, yxj@rock-chips.com, wxt@rock-chips.com, xw@rock-chips.com, Mark yao , Jeff Chen Subject: [PATCH v3 4/5] dt-bindings: video: Add documentation for rockchip edp Date: Fri, 19 Sep 2014 13:54:56 +0800 Message-Id: <1411106096-502-1-git-send-email-mark.yao@rock-chips.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1411105668-32722-1-git-send-email-mark.yao@rock-chips.com> References: <1411105668-32722-1-git-send-email-mark.yao@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add binding documentation for Rockchip SoC EDP driver. Signed-off-by: Jeff Chen Signed-off-by: Mark Yao --- Changes in v2: - add edp reset - add panel node - add port for display-subsystem Changes in v3: None .../devicetree/bindings/video/rockchip-edp.txt | 50 ++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/video/rockchip-edp.txt diff --git a/Documentation/devicetree/bindings/video/rockchip-edp.txt b/Documentation/devicetree/bindings/video/rockchip-edp.txt new file mode 100644 index 0000000..515e806 --- /dev/null +++ b/Documentation/devicetree/bindings/video/rockchip-edp.txt @@ -0,0 +1,50 @@ +Rockchip RK3288 EDP interface +================================ + +Required properties: +- compatible: "rockchip,rk3288-edp"; + +- reg: physical base address of the controller and length +- clocks: from common clock binding: handle to dp clock. + of memory mapped region. +- clock-names: from common clock binding: + Required elements: "clk_edp" + "clk_edp_24m" + "pclk_edp" +- resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names: Must include the name "edp" + +- rockchip,grf: this soc should set GRF regs, so need get grf here. +- rockchip,panel: required a simple panel node as described by + Documentation/devicetree/bindings/panel/simple-panel.txt + +- ports: contain a port node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + +Example: + edp: edp@ff970000 { + compatible = "rockchip,rk3288-edp"; + reg = <0xff970000 0x4000>; + interrupts = ; + clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>; + clock-names = "clk_edp", "clk_edp_24m", "pclk_edp"; + rockchip,grf = <&grf>; + resets = <&cru 111>; + reset-names = "edp"; + rockchip,panel = <&panel>; + ports { + edp_in: port { + #address-cells = <1>; + #size-cells = <0>; + edp_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_edp>; + }; + edp_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_edp>; + }; + }; + }; + }; -- 1.7.9.5