From: Chao Xie <chao.xie@marvell.com>
To: <haojian.zhuang@gmail.com>, <haojian.zhuang@linaro.org>,
<mturquette@linaro.org>, <chao.xie@marvell.com>,
<xiechao_mail@163.com>, <linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH V2 02/13] clk: mmp: add spin lock for clk-frac
Date: Fri, 31 Oct 2014 10:13:42 +0800 [thread overview]
Message-ID: <1414721633-29508-3-git-send-email-chao.xie@marvell.com> (raw)
In-Reply-To: <1414721633-29508-1-git-send-email-chao.xie@marvell.com>
From: Chao Xie <chao.xie@marvell.com>
The register used by clk-frac may be shared with
other clocks.
So it needs to use spin lock to protect the register
access.
Signed-off-by: Chao Xie <chao.xie@marvell.com>
---
drivers/clk/mmp/clk-frac.c | 11 ++++++++++-
drivers/clk/mmp/clk-mmp2.c | 2 +-
drivers/clk/mmp/clk-pxa168.c | 2 +-
drivers/clk/mmp/clk-pxa910.c | 2 +-
drivers/clk/mmp/clk.h | 3 ++-
5 files changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/mmp/clk-frac.c b/drivers/clk/mmp/clk-frac.c
index 3fbc9ca..e29d006 100644
--- a/drivers/clk/mmp/clk-frac.c
+++ b/drivers/clk/mmp/clk-frac.c
@@ -29,6 +29,7 @@ struct mmp_clk_factor {
struct mmp_clk_factor_masks *masks;
struct mmp_clk_factor_tbl *ftbl;
unsigned int ftbl_cnt;
+ spinlock_t *lock;
};
static long clk_factor_round_rate(struct clk_hw *hw, unsigned long drate,
@@ -86,6 +87,7 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
int i;
unsigned long val;
unsigned long prev_rate, rate = 0;
+ unsigned long flags = 0;
for (i = 0; i < factor->ftbl_cnt; i++) {
prev_rate = rate;
@@ -97,6 +99,9 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
if (i > 0)
i--;
+ if (factor->lock)
+ spin_lock_irqsave(factor->lock, flags);
+
val = readl_relaxed(factor->base);
val &= ~(masks->num_mask << masks->num_shift);
@@ -107,6 +112,9 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long drate,
writel_relaxed(val, factor->base);
+ if (factor->lock)
+ spin_unlock_irqrestore(factor->lock, flags);
+
return 0;
}
@@ -120,7 +128,7 @@ struct clk *mmp_clk_register_factor(const char *name, const char *parent_name,
unsigned long flags, void __iomem *base,
struct mmp_clk_factor_masks *masks,
struct mmp_clk_factor_tbl *ftbl,
- unsigned int ftbl_cnt)
+ unsigned int ftbl_cnt, spinlock_t *lock)
{
struct mmp_clk_factor *factor;
struct clk_init_data init;
@@ -143,6 +151,7 @@ struct clk *mmp_clk_register_factor(const char *name, const char *parent_name,
factor->ftbl = ftbl;
factor->ftbl_cnt = ftbl_cnt;
factor->hw.init = &init;
+ factor->lock = lock;
init.name = name;
init.ops = &clk_factor_ops;
diff --git a/drivers/clk/mmp/clk-mmp2.c b/drivers/clk/mmp/clk-mmp2.c
index 7083f12..5c90a42 100644
--- a/drivers/clk/mmp/clk-mmp2.c
+++ b/drivers/clk/mmp/clk-mmp2.c
@@ -191,7 +191,7 @@ void __init mmp2_clk_init(void)
clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
mpmu_base + MPMU_UART_PLL,
&uart_factor_masks, uart_factor_tbl,
- ARRAY_SIZE(uart_factor_tbl));
+ ARRAY_SIZE(uart_factor_tbl), &clk_lock);
clk_set_rate(clk, 14745600);
clk_register_clkdev(clk, "uart_pll", NULL);
diff --git a/drivers/clk/mmp/clk-pxa168.c b/drivers/clk/mmp/clk-pxa168.c
index 75266ac..93e967c 100644
--- a/drivers/clk/mmp/clk-pxa168.c
+++ b/drivers/clk/mmp/clk-pxa168.c
@@ -158,7 +158,7 @@ void __init pxa168_clk_init(void)
uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
mpmu_base + MPMU_UART_PLL,
&uart_factor_masks, uart_factor_tbl,
- ARRAY_SIZE(uart_factor_tbl));
+ ARRAY_SIZE(uart_factor_tbl), &clk_lock);
clk_set_rate(uart_pll, 14745600);
clk_register_clkdev(uart_pll, "uart_pll", NULL);
diff --git a/drivers/clk/mmp/clk-pxa910.c b/drivers/clk/mmp/clk-pxa910.c
index f817999..993abcd 100644
--- a/drivers/clk/mmp/clk-pxa910.c
+++ b/drivers/clk/mmp/clk-pxa910.c
@@ -163,7 +163,7 @@ void __init pxa910_clk_init(void)
uart_pll = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
mpmu_base + MPMU_UART_PLL,
&uart_factor_masks, uart_factor_tbl,
- ARRAY_SIZE(uart_factor_tbl));
+ ARRAY_SIZE(uart_factor_tbl), &clk_lock);
clk_set_rate(uart_pll, 14745600);
clk_register_clkdev(uart_pll, "uart_pll", NULL);
diff --git a/drivers/clk/mmp/clk.h b/drivers/clk/mmp/clk.h
index 3fe92be..b71b717 100644
--- a/drivers/clk/mmp/clk.h
+++ b/drivers/clk/mmp/clk.h
@@ -31,5 +31,6 @@ extern struct clk *mmp_clk_register_apmu(const char *name,
extern struct clk *mmp_clk_register_factor(const char *name,
const char *parent_name, unsigned long flags,
void __iomem *base, struct mmp_clk_factor_masks *masks,
- struct mmp_clk_factor_tbl *ftbl, unsigned int ftbl_cnt);
+ struct mmp_clk_factor_tbl *ftbl, unsigned int ftbl_cnt,
+ spinlock_t *lock);
#endif
--
1.8.3.2
next prev parent reply other threads:[~2014-10-31 2:16 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-31 2:13 [PATCH V2 00/13] clk: mmp: clock device tree support Chao Xie
2014-10-31 2:13 ` [PATCH V2 01/13] clk: mmp: add prefix "mmp" for structures defined for clk-frac Chao Xie
2014-10-31 2:13 ` Chao Xie [this message]
2014-10-31 2:13 ` [PATCH V2 03/13] clk: mmp: add init callback " Chao Xie
2014-10-31 2:13 ` [PATCH V2 04/13] clk: mmp: move definiton of mmp_clk_frac to clk.h Chao Xie
2014-10-31 2:13 ` [PATCH V2 05/13] clk: mmp: add clock type mix Chao Xie
2014-10-31 2:13 ` [PATCH V2 06/13] clk: mmp: add mmp private gate clock Chao Xie
2014-10-31 2:13 ` [PATCH V2 07/13] clk: mmp: add basic support functions for DT support Chao Xie
2014-10-31 2:13 ` [PATCH V2 08/13] clk: mmp: add reset support Chao Xie
2014-10-31 2:13 ` [PATCH V2 09/13] clk: mmp: add pxa168 DT support for clock driver Chao Xie
2014-10-31 2:13 ` [PATCH V2 10/13] clk: mmp: add pxa910 " Chao Xie
2014-10-31 2:13 ` [PATCH V2 11/13] clk: mmp: add mmp2 " Chao Xie
2014-10-31 2:13 ` [PATCH V2 12/13] arm: mmp: Make all the dts file to be compiled by Makefile Chao Xie
2014-10-31 2:13 ` [PATCH V2 13/13] arm: mmp: Make use of the DT supported clock Chao Xie
2014-11-04 8:15 ` [PATCH V2 00/13] clk: mmp: clock device tree support Haojian Zhuang
2014-11-13 0:35 ` Mike Turquette
2014-11-13 1:21 ` Haojian Zhuang
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