From: Marc Zyngier <marc.zyngier@arm.com>
To: Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Jiang Liu <jiang.liu@linux.intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Yingjoe Chen <yingjoe.chen@mediatek.com>,
Will Deacon <will.deacon@arm.com>,
Catalin marinas <catalin.marinas@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>,
Robert Richter <robert.richter@caviumnetworks.com>,
"Yun Wu (Abel)" <wuyun.wu@huawei.com>
Subject: [PATCH v2 02/13] irqchip: GICv3: Convert to domain hierarchy
Date: Tue, 18 Nov 2014 18:52:57 +0000 [thread overview]
Message-ID: <1416336788-22634-3-git-send-email-marc.zyngier@arm.com> (raw)
In-Reply-To: <1416336788-22634-1-git-send-email-marc.zyngier@arm.com>
In order to start supporting stacked domains, convert the GICv3
code base to the new domain hierarchy framework, which mostly
amounts to supporting the new alloc/free callbacks.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
drivers/irqchip/Kconfig | 1 +
drivers/irqchip/irq-gic-v3.c | 42 +++++++++++++++++++++++++++++++++++++-----
2 files changed, 38 insertions(+), 5 deletions(-)
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index b21f12f..4631685 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -14,6 +14,7 @@ config ARM_GIC_V3
bool
select IRQ_DOMAIN
select MULTI_IRQ_HANDLER
+ select IRQ_DOMAIN_HIERARCHY
config ARM_NVIC
bool
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index aa17ae8..aef4b9e 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -594,14 +594,14 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
/* PPIs */
if (hw < 32) {
irq_set_percpu_devid(irq);
- irq_set_chip_and_handler(irq, &gic_chip,
- handle_percpu_devid_irq);
+ irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data,
+ handle_percpu_devid_irq, NULL, NULL);
set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
}
/* SPIs */
if (hw >= 32 && hw < gic_data.irq_nr) {
- irq_set_chip_and_handler(irq, &gic_chip,
- handle_fasteoi_irq);
+ irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data,
+ handle_fasteoi_irq, NULL, NULL);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
irq_set_chip_data(irq, d->host_data);
@@ -633,9 +633,41 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
return 0;
}
+static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs, void *arg)
+{
+ int i, ret;
+ irq_hw_number_t hwirq;
+ unsigned int type = IRQ_TYPE_NONE;
+ struct of_phandle_args *irq_data = arg;
+
+ ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args,
+ irq_data->args_count, &hwirq, &type);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < nr_irqs; i++)
+ gic_irq_domain_map(domain, virq + i, hwirq + i);
+
+ return 0;
+}
+
+static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs)
+{
+ int i;
+
+ for (i = 0; i < nr_irqs; i++) {
+ irq_set_handler(virq + i, NULL);
+ irq_domain_set_hwirq_and_chip(domain, virq + i, 0, NULL, NULL);
+ }
+}
+
+
static const struct irq_domain_ops gic_irq_domain_ops = {
- .map = gic_irq_domain_map,
.xlate = gic_irq_domain_xlate,
+ .alloc = gic_irq_domain_alloc,
+ .free = gic_irq_domain_free,
};
static int __init gic_of_init(struct device_node *node, struct device_node *parent)
--
2.1.3
next prev parent reply other threads:[~2014-11-18 18:53 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-18 18:52 [PATCH v2 00/13] arm64: PCI/MSI: GICv3 ITS support (stacked domain edition) Marc Zyngier
2014-11-18 18:52 ` [PATCH v2 01/13] arm64: PCI/MSI: Use asm-generic/msi.h Marc Zyngier
2014-11-19 10:35 ` Will Deacon
2014-11-18 18:52 ` Marc Zyngier [this message]
2014-11-19 1:07 ` [PATCH v2 02/13] irqchip: GICv3: Convert to domain hierarchy Jiang Liu
2014-11-19 7:37 ` Marc Zyngier
2014-11-18 18:52 ` [PATCH v2 03/13] irqchip: GICv3: rework redistributor structure Marc Zyngier
2014-11-18 18:52 ` [PATCH v2 04/13] irqchip: GICv3: ITS command queue Marc Zyngier
2014-11-18 18:53 ` [PATCH v2 05/13] irqchip: GICv3: ITS: irqchip implementation Marc Zyngier
2014-11-18 18:53 ` [PATCH v2 06/13] irqchip: GICv3: ITS: LPI allocator Marc Zyngier
2014-11-18 18:53 ` [PATCH v2 07/13] irqchip: GICv3: ITS: tables allocators Marc Zyngier
2014-11-18 18:53 ` [PATCH v2 08/13] irqchip: GICv3: ITS: device allocation and configuration Marc Zyngier
2014-11-18 18:53 ` [PATCH v2 09/13] irqchip: GICv3: ITS: MSI support Marc Zyngier
2014-11-18 18:53 ` [PATCH v2 10/13] irqchip: GICv3: ITS: DT probing and initialization Marc Zyngier
2014-11-18 18:53 ` [PATCH v2 11/13] irqchip: GICv3: ITS: plug ITS init into main GICv3 code Marc Zyngier
2014-11-18 18:53 ` [PATCH v2 12/13] irqchip: GICv3: ITS: enable compilation of the ITS driver Marc Zyngier
2014-11-18 18:53 ` [PATCH v2 13/13] irqchip: GICv3: Binding updates for ITS Marc Zyngier
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