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From: Kevin Cernekee <cernekee@gmail.com>
To: ralf@linux-mips.org
Cc: f.fainelli@gmail.com, jfraser@broadcom.com, dtor@chromium.org,
	tglx@linutronix.de, jason@lakedaemon.net, jogo@openwrt.org,
	arnd@arndb.de, computersforpeace@gmail.com,
	linux-mips@linux-mips.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH V3 10/11] MIPS: Reorder MIPS_L1_CACHE_SHIFT priorities
Date: Sun, 23 Nov 2014 18:40:45 -0800	[thread overview]
Message-ID: <1416796846-28149-11-git-send-email-cernekee@gmail.com> (raw)
In-Reply-To: <1416796846-28149-1-git-send-email-cernekee@gmail.com>

Enabling support for more than one BMIPS CPU in the same build may
result in different L1_CACHE_SHIFT values, e.g.

    CPU_BMIPS5000 selects MIPS_L1_CACHE_SHIFT_7
    CPU_BMIPS4380 selects MIPS_L1_CACHE_SHIFT_6
    anything else defaults to MIPS_L1_CACHE_SHIFT_5

Ensure that if more than one MIPS_L1_CACHE_SHIFT_x option is selected,
Kconfig sets CONFIG_MIPS_L1_CACHE_SHIFT to the highest value.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
---
 arch/mips/Kconfig | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index ae8ae77b2ecd..9c09a5a43f87 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1167,10 +1167,10 @@ config MIPS_L1_CACHE_SHIFT_7
 
 config MIPS_L1_CACHE_SHIFT
 	int
-	default "4" if MIPS_L1_CACHE_SHIFT_4
-	default "5" if MIPS_L1_CACHE_SHIFT_5
-	default "6" if MIPS_L1_CACHE_SHIFT_6
 	default "7" if MIPS_L1_CACHE_SHIFT_7
+	default "6" if MIPS_L1_CACHE_SHIFT_6
+	default "5" if MIPS_L1_CACHE_SHIFT_5
+	default "4" if MIPS_L1_CACHE_SHIFT_4
 	default "5"
 
 config HAVE_STD_PC_SERIAL_PORT
-- 
2.1.1


  parent reply	other threads:[~2014-11-24  2:41 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-11-24  2:40 [PATCH V3 00/11] Multiplatform BMIPS kernel Kevin Cernekee
2014-11-24  2:40 ` [PATCH V3 01/11] irqchip: Update docs regarding irq_domain_add_tree() Kevin Cernekee
2014-11-24  2:40 ` [PATCH V3 02/11] irqchip: brcmstb-l2: don't clear wakeable interrupts at init time Kevin Cernekee
2014-11-24  2:40 ` [PATCH V3 03/11] irqchip: brcmstb-l2: fix error handling of irq_of_parse_and_map Kevin Cernekee
2014-11-24  2:40 ` [PATCH V3 04/11] irqchip: bcm7120-l2: " Kevin Cernekee
2014-11-24  2:40 ` [PATCH V3 05/11] irqchip: bcm7120-l2: Refactor driver for arbitrary IRQEN/IRQSTAT offsets Kevin Cernekee
2014-11-24  2:40 ` [PATCH V3 06/11] irqchip: bcm7120-l2: Change DT binding to allow non-contiguous IRQEN/IRQSTAT Kevin Cernekee
2014-11-24 14:31   ` Jonas Gorski
2014-11-26  5:18     ` Kevin Cernekee
2014-11-26  9:45       ` Jonas Gorski
2014-11-26 10:25         ` Jonas Gorski
2014-11-26 18:54           ` Kevin Cernekee
2014-11-26 20:13             ` Jonas Gorski
2014-11-26 21:06               ` Kevin Cernekee
2014-11-24  2:40 ` [PATCH V3 07/11] irqchip: Add new driver for BCM7038-style level 1 interrupt controllers Kevin Cernekee
2014-11-24  2:40 ` [PATCH V3 08/11] MIPS: Let __dt_register_buses accept a single bus type Kevin Cernekee
2014-11-24  2:40 ` [PATCH V3 09/11] MIPS: Fall back to the generic restart notifier Kevin Cernekee
2014-11-24  2:40 ` Kevin Cernekee [this message]
2014-11-24  2:40 ` [PATCH V3 11/11] MIPS: Add multiplatform BMIPS target Kevin Cernekee
2014-11-24 14:00   ` Arnd Bergmann
2014-11-24 18:34     ` Andrew Bresticker
2014-11-24 21:07     ` Kevin Cernekee
2014-11-24 21:39       ` Arnd Bergmann
2014-11-26 20:45         ` Kevin Cernekee
2014-11-26 21:28           ` Arnd Bergmann
2014-11-26 22:54             ` Kevin Cernekee
2014-11-24 19:29   ` Andrew Bresticker
2014-11-24 19:57     ` Kevin Cernekee
2014-11-24 13:34 ` [PATCH V3 00/11] Multiplatform BMIPS kernel Arnd Bergmann

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