From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755593AbbAWPNK (ORCPT ); Fri, 23 Jan 2015 10:13:10 -0500 Received: from mga14.intel.com ([192.55.52.115]:30550 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755473AbbAWPNH (ORCPT ); Fri, 23 Jan 2015 10:13:07 -0500 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.09,454,1418112000"; d="scan'208";a="666508886" From: Heikki Krogerus To: Felipe Balbi , Greg Kroah-Hartman Cc: Baolu Lu , linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/8] usb: dwc3: USB2 PHY register access bits Date: Fri, 23 Jan 2015 17:12:52 +0200 Message-Id: <1422025978-178336-3-git-send-email-heikki.krogerus@linux.intel.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1422025978-178336-1-git-send-email-heikki.krogerus@linux.intel.com> References: <1422025978-178336-1-git-send-email-heikki.krogerus@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Definitions for Global USB2 PHY Vendor Control Register bits. We will need them to access ULPI PHY registers later. Signed-off-by: Heikki Krogerus --- drivers/usb/dwc3/core.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 0842aa8..be1c20e 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -174,6 +174,14 @@ #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) +/* Global USB2 PHY Vendor Control Register */ +#define DWC3_GUSB2PHYACC_NEWREGREQ (1 << 25) +#define DWC3_GUSB2PHYACC_BUSY (1 << 23) +#define DWC3_GUSB2PHYACC_WRITE (1 << 22) +#define DWC3_GUSB2PHYACC_ADDR(n) (n << 16) +#define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8) +#define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff) + /* Global USB3 PIPE Control Register */ #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) #define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29) -- 2.1.4