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Subject: Re: [PATCH 0/3] clk: divider: three exactness fixes (and a rant)
From: Philipp Zabel <p.zabel@pengutronix.de>
To: Stephen Boyd <sboyd@codeaurora.org>
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Date: Thu, 12 Mar 2015 09:57:53 +0100
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Hi Stephen,

Am Mittwoch, den 11.03.2015, 18:21 -0700 schrieb Stephen Boyd:
[...]
> Why does Philipp like 110Hz the most? Where is the desire for that rate
> coming from?
> 
> > And the lower
> > abs(1 / 110 - 1 / r) the better. 
> 
> Similarly, where is this requirement coming from? Some datasheet? Or is
> it just some arbitrary decision we've made that may not hold true for
> all consumers?

In my panel example the datasheet usually documents the typical pixel
clock and vertical and horizontal timings that exactly result in the
nominal panel refresh rate, currently most often 60 Hz.

In this use case, the driver doesn't want the pixel clock to stay below
a hard frequency limit, but to get as close as possible to the target
frequency, either above or below, so the relative error to the nominal
panel refresh rate stays as small as possible. Thus for a fictional
target rate of 110 Hz, I'd like to minimize abs((round_rate / 110) - 1).

regards
Philipp