[PATCH V3 0/6] Add initial support for Broadcom Cygnus SoC

[PATCH V3 0/6] Add initial support for Broadcom Cygnus SoC

[Scott Branden]

This patchset contains initial support for Broadcom's Cygnus SoC based on our
iProc architecture. Initial support is minimal and includes just the mach
platform code, clock driver, and a basic device tree configuration. Peripheral
drivers will be submitted soon, as will device tree configurations for other
Cygnus board variants.

Changes from v2:
 - rebased to 3.17 kernel

Changes from v1:
 - Address code review comments as per previous responses.
 - Copyright headers updated to remove Broadcom URL.
 - mach platform code still contains hard coded addresses. These address are
   the same for all Cygnus variants. Could you please provide guidance on where
   they should go if you would still like them changed.  There does not seem to
   be a reason to change them to device tree as they do not change.

Jonathan Richardson (6):
  ARM: cygnus: Initial support for Broadcom Cygnus SoC
  clk: Clock driver support for Broadcom Cygnus SoC
  dt-bindings: Document Broadcom Cygnus SoC and clock driver
  ARM: cygnus defconfig : Initial defconfig for Broadcom Cygnus SoC
  ARM: dts: Enable Broadcom Cygnus SoC
  MAINTAINERS: Entry for Cygnus/iproc arm architecture and clock
    drivers

 Documentation/devicetree/bindings/arm/cygnus.txt   |   12 +
 .../devicetree/bindings/clock/clk-cygnus.txt       |  121 ++
 .../devicetree/bindings/clock/clk-iproc.txt        |   48 +
 MAINTAINERS                                        |   15 +
 arch/arm/boot/dts/Makefile                         |    1 +
 arch/arm/boot/dts/bcm-cygnus.dtsi                  |  349 ++++++
 arch/arm/boot/dts/bcm911360_entphn.dts             |   22 +
 arch/arm/configs/bcm_cygnus_defconfig              |  222 ++++
 arch/arm/mach-bcm/Kconfig                          |   31 +
 arch/arm/mach-bcm/Makefile                         |    3 +
 arch/arm/mach-bcm/bcm_cygnus.c                     |  166 +++
 drivers/clk/Makefile                               |    1 +
 drivers/clk/bcm/Makefile                           |    2 +
 drivers/clk/bcm/clk-cygnus.c                       | 1186 ++++++++++++++++++++
 drivers/clk/bcm/clk-iproc.c                        |  451 ++++++++
 15 files changed, 2630 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/cygnus.txt
 create mode 100644 Documentation/devicetree/bindings/clock/clk-cygnus.txt
 create mode 100644 Documentation/devicetree/bindings/clock/clk-iproc.txt
 create mode 100644 arch/arm/boot/dts/bcm-cygnus.dtsi
 create mode 100644 arch/arm/boot/dts/bcm911360_entphn.dts
 create mode 100644 arch/arm/configs/bcm_cygnus_defconfig
 create mode 100644 arch/arm/mach-bcm/bcm_cygnus.c
 create mode 100644 drivers/clk/bcm/clk-cygnus.c
 create mode 100644 drivers/clk/bcm/clk-iproc.c

-- 
1.7.9.5

[PATCH 1/6] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Scott Branden]

From: Jonathan Richardson <jonathar@broadcom.com>

Adds initial support for the Cygnus SoC based on Broadcom’s iProc series.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Desmond Liu <desmondl@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/mach-bcm/Kconfig      |   31 ++++++++
 arch/arm/mach-bcm/Makefile     |    3 +
 arch/arm/mach-bcm/bcm_cygnus.c |  166 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 200 insertions(+)
 create mode 100644 arch/arm/mach-bcm/bcm_cygnus.c

diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index fc93800..2dd3f78 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -5,6 +5,37 @@ menuconfig ARCH_BCM
 
 if ARCH_BCM
 
+config ARCH_BCM_IPROC
+	bool "Broadcom ARMv7 iProc boards" if ARCH_MULTI_V7
+	select ARM_GIC
+	select CACHE_L2X0
+	select HAVE_ARM_TWD if LOCAL_TIMERS
+	select HAVE_CLK
+	select CLKSRC_OF
+	select CLKSRC_MMIO
+	select GENERIC_CLOCKEVENTS
+	select ARM_GLOBAL_TIMER
+	select ARCH_REQUIRE_GPIOLIB
+	select ARM_AMBA
+	select PINCTRL
+	select DEBUG_UART_8250
+	help
+	  This enables support for systems based on Broadcom IPROC architected SoCs.
+	  The IPROC complex contains one or more ARM CPUs along with common
+	  core periperals. Application specific SoCs are created by adding a
+	  uArchitecture containing peripherals outside of the IPROC complex.
+	  Currently supported SoCs are Cygnus.
+
+menu "iProc SoC based Machine types"
+	depends on ARCH_BCM_IPROC
+
+	config ARCH_BCM_CYGNUS
+		bool "Support Broadcom Cygnus board"
+		select USB_ARCH_HAS_EHCI if USB_SUPPORT
+		help
+		  Support for Broadcom Cygnus SoC.
+endmenu
+
 config ARCH_BCM_MOBILE
 	bool "Broadcom Mobile SoC Support" if ARCH_MULTI_V7
 	select ARCH_REQUIRE_GPIOLIB
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index b19a396..46e092a 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -10,6 +10,9 @@
 # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
 
+# Cygnus
+obj-$(CONFIG_ARCH_BCM_CYGNUS) +=  bcm_cygnus.o
+
 # BCM281XX
 obj-$(CONFIG_ARCH_BCM_281XX)	+= board_bcm281xx.o
 
diff --git a/arch/arm/mach-bcm/bcm_cygnus.c b/arch/arm/mach-bcm/bcm_cygnus.c
new file mode 100644
index 0000000..8e430ed
--- /dev/null
+++ b/arch/arm/mach-bcm/bcm_cygnus.c
@@ -0,0 +1,166 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/clocksource.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/proc-fns.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#define CRMU_MAIL_BOX1      0x03024028
+#define CRMU_SOFT_RESET_CMD 0xFFFFFFFF
+
+/* CRU_RESET register */
+static void * __iomem crmu_mail_box1_reg;
+
+#ifdef CONFIG_NEON
+
+#define CRU_BASE                  0x1800e000
+#define CRU_SIZE                  0x34
+#define CRU_CONTROL_OFFSET        0x0
+#define CRU_PWRDWN_EN_OFFSET      0x4
+#define CRU_PWRDWN_STATUS_OFFSET  0x8
+#define CRU_NEON0_HW_RESET  6
+#define CRU_CLAMP_ON_NEON0  20
+#define CRU_PWRONIN_NEON0   21
+#define CRU_PWRONOUT_NEON0  21
+#define CRU_PWROKIN_NEON0   22
+#define CRU_PWROKOUT_NEON0  22
+#define CRU_STATUS_DELAY_NS 500
+#define CRU_MAX_RETRY_COUNT 10
+#define CRU_RETRY_INTVL_US  1
+
+/* Power up the NEON/VFPv3 block. */
+static void bcm_cygnus_powerup_neon(void)
+{
+	void * __iomem cru_base = ioremap(CRU_BASE, CRU_SIZE);
+	u32 reg, i;
+
+	if (WARN_ON(!cru_base))
+		return;
+
+	/* De-assert the neon hardware block reset */
+	reg = readl(cru_base + CRU_CONTROL_OFFSET);
+	reg &= ~(1 << CRU_NEON0_HW_RESET);
+	writel(reg, cru_base + CRU_CONTROL_OFFSET);
+
+	/* Assert the power ON register bit */
+	reg = readl(cru_base + CRU_PWRDWN_EN_OFFSET);
+	reg |= (1 << CRU_PWRONIN_NEON0);
+	writel(reg, cru_base + CRU_PWRDWN_EN_OFFSET);
+
+	/*
+	 * Wait up to 10 usec in 1 usec increments for the
+	 * status register to acknowledge the power ON assert
+	 */
+	for (i = 0; i < CRU_MAX_RETRY_COUNT; i++) {
+		reg = readl(cru_base + CRU_PWRDWN_STATUS_OFFSET);
+		if (reg & CRU_PWRONOUT_NEON0)
+			break;
+
+		udelay(CRU_RETRY_INTVL_US);
+	}
+
+	if (WARN_ON(i == CRU_MAX_RETRY_COUNT))
+		goto neon_unmap;
+
+	/* Wait 0.5 usec = 500 nsec */
+	ndelay(CRU_STATUS_DELAY_NS);
+
+	/* Assert the power OK register bit */
+	reg = readl(cru_base + CRU_PWRDWN_EN_OFFSET);
+	reg |= (1 << CRU_PWROKIN_NEON0);
+	writel(reg, cru_base + CRU_PWRDWN_EN_OFFSET);
+
+	/*
+	 * Wait up to 10 usec in 1 usec increments for the
+	 * status register to acknowledge the power OK assert
+	 */
+	for (i = 0; i < CRU_MAX_RETRY_COUNT; i++) {
+		reg = readl(cru_base + CRU_PWRDWN_STATUS_OFFSET);
+		if (reg & CRU_PWROKOUT_NEON0)
+			break;
+
+		udelay(CRU_RETRY_INTVL_US);
+	}
+
+	if (WARN_ON(i == CRU_MAX_RETRY_COUNT))
+		goto neon_unmap;
+
+	/* Wait 0.5 usec = 500 nsec */
+	ndelay(CRU_STATUS_DELAY_NS);
+
+	/* Set the logic clamp for the neon block */
+	reg = readl(cru_base + CRU_PWRDWN_EN_OFFSET);
+	reg &= ~(1 << CRU_CLAMP_ON_NEON0);
+	writel(reg, cru_base + CRU_PWRDWN_EN_OFFSET);
+
+	/* Wait 0.5 usec = 500 nsec */
+	ndelay(CRU_STATUS_DELAY_NS);
+
+	/* Reset the neon hardware block */
+	reg = readl(cru_base + CRU_CONTROL_OFFSET);
+	reg |= (1 << CRU_NEON0_HW_RESET);
+	writel(reg, cru_base + CRU_CONTROL_OFFSET);
+
+neon_unmap:
+	iounmap(cru_base);
+}
+#endif /* CONFIG_NEON */
+
+static void __init bcm_cygnus_init(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+
+	l2x0_of_init(0, ~0UL);
+
+	crmu_mail_box1_reg = ioremap(CRMU_MAIL_BOX1, SZ_4);
+	WARN_ON(!crmu_mail_box1_reg);
+
+#ifdef CONFIG_NEON
+	bcm_cygnus_powerup_neon();
+#endif
+}
+
+/*
+ * Reset the system
+ */
+void bcm_cygnus_restart(enum reboot_mode mode, const char *cmd)
+{
+	/* Send reset command to M0 via Mailbox. */
+	if (crmu_mail_box1_reg) {
+		writel(CRMU_SOFT_RESET_CMD, crmu_mail_box1_reg);
+		iounmap(crmu_mail_box1_reg);
+	}
+
+	/* Wait for M0 to reset the chip. */
+	while (1)
+		cpu_do_idle();
+}
+
+static const char const *bcm_cygnus_dt_compat[] = {
+	"brcm,cygnus",
+	NULL,
+};
+
+DT_MACHINE_START(BCM_CYGNUS_DT, "Broadcom Cygnus SoC")
+	.init_machine = bcm_cygnus_init,
+	.map_io = debug_ll_io_init,
+	.dt_compat = bcm_cygnus_dt_compat,
+	.restart   = bcm_cygnus_restart
+MACHINE_END
-- 
1.7.9.5

[PATCH 2/6] clk: Clock driver support for Broadcom Cygnus SoC

[Scott Branden]

From: Jonathan Richardson <jonathar@broadcom.com>

The iProc clock driver controls PLLs common across iProc chips. The
cygnus driver controls cygnus specific features and variations.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/clk/Makefile         |    1 +
 drivers/clk/bcm/Makefile     |    2 +
 drivers/clk/bcm/clk-cygnus.c | 1186 ++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/bcm/clk-iproc.c  |  451 ++++++++++++++++
 4 files changed, 1640 insertions(+)
 create mode 100644 drivers/clk/bcm/clk-cygnus.c
 create mode 100644 drivers/clk/bcm/clk-iproc.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index f537a0b..8ac0a31 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_ARCH_VT8500)		+= clk-vt8500.o
 obj-$(CONFIG_COMMON_CLK_WM831X)		+= clk-wm831x.o
 obj-$(CONFIG_COMMON_CLK_XGENE)		+= clk-xgene.o
 obj-$(CONFIG_COMMON_CLK_AT91)		+= at91/
+obj-$(CONFIG_ARCH_BCM_IPROC)	+= bcm/
 obj-$(CONFIG_ARCH_BCM_MOBILE)		+= bcm/
 obj-$(CONFIG_ARCH_BERLIN)		+= berlin/
 obj-$(CONFIG_ARCH_HI3xxx)		+= hisilicon/
diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
index 6297d05..f803919 100644
--- a/drivers/clk/bcm/Makefile
+++ b/drivers/clk/bcm/Makefile
@@ -2,3 +2,5 @@ obj-$(CONFIG_CLK_BCM_KONA)	+= clk-kona.o
 obj-$(CONFIG_CLK_BCM_KONA)	+= clk-kona-setup.o
 obj-$(CONFIG_CLK_BCM_KONA)	+= clk-bcm281xx.o
 obj-$(CONFIG_CLK_BCM_KONA)	+= clk-bcm21664.o
+obj-$(CONFIG_ARCH_BCM_IPROC)	+= clk-iproc.o
+obj-$(CONFIG_ARCH_BCM_CYGNUS)	+= clk-cygnus.o
diff --git a/drivers/clk/bcm/clk-cygnus.c b/drivers/clk/bcm/clk-cygnus.c
new file mode 100644
index 0000000..2a4f976
--- /dev/null
+++ b/drivers/clk/bcm/clk-cygnus.c
@@ -0,0 +1,1186 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/clkdev.h>
+#include <linux/of_address.h>
+
+/*
+ * The CRU contains two similar PLLs: LCPLL and GENPLL,
+ * both with several output channels divided from the PLL
+ * output.
+ */
+
+#define CRU_LCPLL_CONTROL1_OFFSET  0x04
+#define CRU_LCPLL_STATUS_OFFSET    0x18
+
+#define LCPLL0_PDIV_SHIFT       26
+#define LCPLL0_PDIV_MASK        0xf
+#define LCPLL0_NDIV_SHIFT       16
+#define LCPLL0_NDIV_MASK        0x3ff
+#define LCPLL_ENABLEB_CH_SHIFT  7
+#define LCPLL_ENABLEB_CH_MASK   0x3f
+#define LCPLL_MDIV_MASK         0xff
+#define LCPLL_STATUS_LOCK_SHIFT 12
+
+#define LCPLL0_CONTROL0_OFFSET  0x00
+#define LCPLL0_CONTROL1_OFFSET  0x04
+#define LCPLL0_CONTROL2_OFFSET  0x08
+#define LCPLL0_CONTROL3_OFFSET  0x0c
+
+#define GENPLL_CONTROL0_OFFSET 0x00
+#define GENPLL_CONTROL1_OFFSET 0x04
+#define GENPLL_CONTROL2_OFFSET 0x08
+#define GENPLL_CONTROL3_OFFSET 0x0c
+#define GENPLL_CONTROL4_OFFSET 0x10
+#define GENPLL_CONTROL5_OFFSET 0x14
+#define GENPLL_CONTROL6_OFFSET 0x18
+#define GENPLL_CONTROL7_OFFSET 0x1c
+#define GENPLL_CONTROL8_OFFSET 0x20
+#define GENPLL_CONTROL9_OFFSET 0x24
+#define GENPLL_STATUS_OFFSET   0x28
+
+#define GENPLL_ENABLEB_CH_SHIFT    0x6
+#define GENPLL_ENABLEB_CH_MASK     0x3f
+
+#define GENPLL_STATUS_LOCK_SHIFT           12
+#define GENPLL_STATUS_LOCK_MASK            1
+#define GENPLL_CONTROL4_NDIV_INT_SHIFT     20
+#define GENPLL_CONTROL4_NDIV_INT_MASK      0x3FF
+#define GENPLL_CONTROL4_NDIV_FRAC_SHIFT    0
+#define GENPLL_CONTROL4_NDIV_FRAC_MASK     0xFFFFF
+#define GENPLL_CONTROL5_PDIV_SHIFT         0
+#define GENPLL_CONTROL5_PDIV_MASK          0xF
+#define GENPLL_MDIV_MASK                   0xff
+
+#define MIPI_DSI_GENPLL_ENABLEB_CH_SHIFT   12
+#define NDIV_FRAC_DIVISOR                  0x100000
+
+#define ASIU_MIPI_GENPLL_PWRON_SHIFT      20
+#define ASIU_MIPI_GENPLL_PWRON_PLL_SHIFT  19
+#define ASIU_MIPI_GENPLL_PWRON_BG_SHIFT   18
+#define ASIU_MIPI_GENPLL_PWRON_LDO_SHIFT  17
+#define ASIU_MIPI_GENPLL_ISO_IN_SHIFT     16
+#define ASIU_AUDIO_GENPLL_PWRON_PLL_SHIFT 11
+#define ASIU_AUDIO_GENPLL_PWRON_BG_SHIFT  10
+#define ASIU_AUDIO_GENPLL_PWRON_LDO_SHIFT 9
+#define ASIU_AUDIO_GENPLL_ISO_IN          8
+
+#define CLK_RATE_NO_DIV                   -1
+
+/*
+ * The clock framework may call recalc even if a clock is is unused, and
+ * therefore before being prepared/enabled. State checking is done for the
+ * MIPI PLL to prevent reading from a MIPI DSI register before the PLL is
+ * powered up because it will cause corruption (imprecise external aborts)
+ * sometimer later on.
+ */
+enum clock_state {
+	CLK_ENABLED,
+	CLK_PREPARED,
+	CLK_DISABLED
+};
+
+struct cygnus_clk {
+	struct clk_hw   hw;
+	void __iomem    *regs_base;
+	void __iomem    *pll_ctrl_reg;
+	void __iomem    *clock_gate_ctrl_reg;
+	int             chan;
+	int             internal_div;
+	unsigned long   rate;
+	enum clock_state state;
+};
+
+#define to_cygnus_clk(p) container_of(p, struct cygnus_clk, hw)
+
+/* Identifies LCPLL clock channels. */
+enum cygnus_lcpll_clk_chan {
+	LCPLL_CH0_PCIE_PHY_REF_CLK      = 0,
+	LCPLL_CH1_DDR_CLK               = 1,
+	LCPLL_CH2_SDIO_CLK              = 2,
+	LCPLL_CH3_USB_PHY_REF_CLK       = 3,
+	LCPLL_CH4_ASIU_SMART_CARD_CLK   = 4,
+	LCPLL_CH5                       = 5
+};
+
+/* Identifies GENPLL clock channels. */
+enum cygnus_genpll_clk_chan {
+	GENPLL_CH0_AXI21_CLK      = 0,
+	GENPLL_CH1_25MHZ_CLK      = 1,
+	GENPLL_CH2_SYS_CLK        = 2,
+	GENPLL_CH3_ETHERNET_CLK   = 3,
+	GENPLL_CH4_ASIU_AUDIO_CLK = 4,
+	GENPLL_CH5_ASIU_CAN_CLK   = 5
+};
+
+/*
+ * Channels for Oscillator dervived clocks are values used to determine
+ * which clock to enable/disable from the top clock gating control.
+ */
+enum cygnus_osc_derived_clk_chan {
+	OSC_DERIVED_CH0_KEYPAD_CLK = 0,
+	OSC_DERIVED_CH1_ADC_CLK    = 1,
+	OSC_DERIVED_CH2_PWM_CLK    = 2,
+};
+
+enum cygnus_mipi_pll_clk_chan {
+	MIPI_PLL_CH0_MIPI_PHY_CLK    = 0,
+	MIPI_PLL_CH1_LCD_CLK         = 1,
+	MIPI_PLL_CH2_3D_GRAPHICS_CLK = 2,
+};
+
+/* Order of registers defined in DT. */
+enum cygnus_clk_dt_regs {
+	CYGNUS_CLK_BASE_REG = 0,
+	CYGNUS_CLK_GATE_CTRL_REG,
+	CYGNUS_PLL_CTRL_REG
+};
+
+enum cygnus_top_clk_gating_ctrl_offsets {
+	GFX_CLK_GATE_EN = 0,
+	AUD_CLK_GATE_EN,
+	CAM_CLK_GATE_EN,
+	MIPI_DSI_CLK_GATE_EN,
+	LCD_CLK_GATE_EN,
+	D1W_CLK_GATE_EN,
+	CAN_CLK_GATE_EN,
+	KEYPAD_CLK_GATE_EN,
+	SMARTCARD_CLK_GATE_EN,
+	ADC_CLK_GATE_EN,
+	CRYPTO_CLK_GATE_EN
+};
+
+/*
+ * Enable clocks controlled through the top clock gating control.
+ *
+ * @param enable true = enable clock, false = disable clock
+ */
+static void cygnus_clkgate_enable_disable(void __iomem *clkgate_reg,
+	enum cygnus_top_clk_gating_ctrl_offsets offset, bool enable)
+{
+	u32 val = readl(clkgate_reg);
+
+	/* Enable or disable the clock. */
+	if (enable)
+		val |= 1 << offset;
+	else
+		val &= ~(1 << offset);
+
+	writel(val, clkgate_reg);
+}
+
+/*
+ * Powers on/off the MIPI GENPLL using CRMU_PLL_AON_CTRL register.
+ *
+ * @param power_on true to power on PLL, false to power off
+ */
+static void cygnus_mipi_genpll_power_on_off(void __iomem *pll_ctrl_reg,
+	bool power_on)
+{
+	u32 val;
+	u32 pll_ldo_on = ((1 << ASIU_MIPI_GENPLL_PWRON_SHIFT) |
+		(1 << ASIU_MIPI_GENPLL_PWRON_PLL_SHIFT) |
+		(1 << ASIU_MIPI_GENPLL_PWRON_BG_SHIFT)  |
+		(1 << ASIU_MIPI_GENPLL_PWRON_LDO_SHIFT));
+
+	val = readl(pll_ctrl_reg);
+
+	/*
+	 * Set PLL on/off. Set input isolation mode to 1 when disabled, 0 when
+	 * enabled.
+	 */
+	if (power_on) {
+		val |= pll_ldo_on;
+		val &= ~(1 << ASIU_MIPI_GENPLL_ISO_IN_SHIFT);
+	} else {
+		val &= ~pll_ldo_on;
+		val |= 1 << ASIU_MIPI_GENPLL_ISO_IN_SHIFT;
+	}
+
+	writel(val, pll_ctrl_reg);
+}
+
+/*
+ * Powers on/off the audio PLL using CRMU_PLL_AON_CTRL register.
+ *
+ * @param power_on true to power on PLL, false to power off
+ */
+static void cygnus_audio_genpll_power_on_off(void __iomem *pll_ctrl_reg,
+	bool power_on)
+{
+	u32 val;
+	u32 pll_ldo_on = ((1 << ASIU_AUDIO_GENPLL_PWRON_PLL_SHIFT) |
+		(1 << ASIU_AUDIO_GENPLL_PWRON_BG_SHIFT) |
+		(1 << ASIU_AUDIO_GENPLL_PWRON_LDO_SHIFT));
+
+	val = readl(pll_ctrl_reg);
+
+	/*
+	 * Set PLL on/off. Set input isolation mode to 1 when disabled, 0 when
+	 * enabled.
+	 */
+	if (power_on) {
+		val |= pll_ldo_on;
+		val &= ~(1 << ASIU_AUDIO_GENPLL_ISO_IN);
+	} else {
+		val &= ~pll_ldo_on;
+		val |= 1 << ASIU_AUDIO_GENPLL_ISO_IN;
+	}
+
+	writel(val, pll_ctrl_reg);
+}
+
+/*
+ * Get PLL running status and calculate output frequency
+ */
+static unsigned long cygnus_lcpll_status(struct cygnus_clk *clk,
+	unsigned long parent_rate)
+{
+	u32 reg;
+	unsigned pdiv, ndiv;
+
+	/* read status register */
+	reg = readl(clk->regs_base + CRU_LCPLL_STATUS_OFFSET);
+
+	/* Must be locked for proper PLL operation. */
+	if ((reg & (1 << LCPLL_STATUS_LOCK_SHIFT)) == 0) {
+		clk->rate = 0;
+		return -EIO;
+	}
+
+	/*
+	 * Calculate PLL frequency based on LCPLL divider values:
+	 *	 pdiv = LCPLL pre-divider ratio
+	 *   ndiv = LCPLL feedback divider
+	 *
+	 * The frequency is calculated by:
+	 *   ndiv * (parent clock rate / pdiv)
+	 */
+
+	reg = readl(clk->regs_base + CRU_LCPLL_CONTROL1_OFFSET);
+
+	/* feedback divider integer and fraction parts */
+	pdiv = (reg >> LCPLL0_PDIV_SHIFT) & LCPLL0_PDIV_MASK;
+	ndiv = (reg >> LCPLL0_NDIV_SHIFT) & LCPLL0_NDIV_MASK;
+
+	if (pdiv == 0)
+		return -EIO;
+
+	clk->rate = ndiv * (parent_rate / pdiv);
+
+	return clk->rate;
+}
+
+static unsigned long cygnus_lcpll_clk_recalc_rate(struct clk_hw *hwclk,
+	unsigned long parent_rate)
+{
+	struct cygnus_clk *bcm_clk = to_cygnus_clk(hwclk);
+
+	return cygnus_lcpll_status(bcm_clk, parent_rate);
+}
+
+static const struct clk_ops cygnus_lcpll_ops = {
+	.recalc_rate = cygnus_lcpll_clk_recalc_rate,
+};
+
+static int cygnus_lcpll_chan_status(struct cygnus_clk *clk,
+	unsigned long parent_rate)
+{
+	void * __iomem base;
+	u32 reg;
+	unsigned enable;
+	unsigned mdiv;
+	int offset = 0;
+	int shift = 0;
+
+	/* Register address is only stored in PLL structure */
+	base = clk->regs_base;
+	BUG_ON(base == NULL);
+
+	/* enable bit is in enableb_ch[] inversed */
+	enable = ((readl(base + LCPLL0_CONTROL0_OFFSET) >>
+		LCPLL_ENABLEB_CH_SHIFT) & LCPLL_ENABLEB_CH_MASK) ^
+		LCPLL_ENABLEB_CH_MASK;
+
+	if ((enable & (1 << clk->chan)) == 0) {
+		clk->rate = 0;
+		return -EIO;
+	}
+
+	/* MDIV for the 6 channels is spread over two registers. */
+	switch (clk->chan) {
+	case LCPLL_CH0_PCIE_PHY_REF_CLK:
+		offset = LCPLL0_CONTROL2_OFFSET; shift = 0;
+		break;
+
+	case LCPLL_CH1_DDR_CLK:
+		offset = LCPLL0_CONTROL2_OFFSET; shift = 10;
+		break;
+
+	case LCPLL_CH2_SDIO_CLK:
+		offset = LCPLL0_CONTROL2_OFFSET; shift = 20;
+		break;
+
+	case LCPLL_CH3_USB_PHY_REF_CLK:
+		offset = LCPLL0_CONTROL3_OFFSET; shift = 0;
+		break;
+
+	case LCPLL_CH4_ASIU_SMART_CARD_CLK:
+		offset = LCPLL0_CONTROL3_OFFSET; shift = 10;
+		break;
+
+	case LCPLL_CH5:
+		offset = LCPLL0_CONTROL3_OFFSET; shift = 20;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	/* Read MDIV for requested channel. */
+	reg = readl(base + offset);
+	mdiv = (reg >> shift) & LCPLL_MDIV_MASK;
+
+	/* when divisor is 0, it behaves as max+1 */
+	if (mdiv == 0)
+		mdiv = 256;
+
+	clk->rate = parent_rate / mdiv;
+
+	pr_debug("LCPLL[%d] mdiv=%u Prate=%lu rate=%lu\n",
+		clk->chan, mdiv, parent_rate, clk->rate);
+
+	return clk->rate;
+}
+
+static unsigned long cygnus_lcpll_chan_recalc_rate(struct clk_hw *hwclk,
+	unsigned long parent_rate)
+{
+	struct cygnus_clk *bcm_clk = to_cygnus_clk(hwclk);
+
+	return cygnus_lcpll_chan_status(bcm_clk, parent_rate);
+}
+
+static const struct clk_ops cygnus_lcpll_chan_ops = {
+	.recalc_rate = cygnus_lcpll_chan_recalc_rate,
+};
+
+/*
+ * Get PLL running status and calculate output frequency
+ */
+static unsigned long cygnus_genpll_status(struct cygnus_clk *clk,
+	unsigned long parent_rate)
+{
+	u32 reg;
+	unsigned pdiv;
+	unsigned ndiv_int;
+	unsigned ndiv_frac;
+
+	/* Read PLL status register. It must be locked. */
+	reg = readl(clk->regs_base + GENPLL_STATUS_OFFSET);
+	if ((reg & (1 << GENPLL_STATUS_LOCK_SHIFT)) == 0) {
+		clk->rate = 0;
+		return -EIO;
+	}
+
+	/* Calculate PLL frequency */
+
+	/* Get PLL feedback divider values. */
+	reg = readl(clk->regs_base + GENPLL_CONTROL4_OFFSET);
+
+	/* feedback divider integer and fraction parts */
+	ndiv_int = reg >> GENPLL_CONTROL4_NDIV_INT_SHIFT;
+	ndiv_frac = reg & GENPLL_CONTROL4_NDIV_INT_MASK;
+	ndiv_int += ndiv_frac / NDIV_FRAC_DIVISOR;
+
+	/* Get pdiv - first 4 bits. */
+	reg = readl(clk->regs_base + GENPLL_CONTROL5_OFFSET);
+	pdiv = reg & GENPLL_CONTROL5_PDIV_MASK;
+	if (pdiv == 0)
+		return -EIO;
+
+	clk->rate = (parent_rate / pdiv) * ndiv_int;
+
+	return clk->rate;
+}
+
+static unsigned long cygnus_genpll_recalc_rate(struct clk_hw *hwclk,
+	unsigned long parent_rate)
+{
+	struct cygnus_clk *bcm_clk = to_cygnus_clk(hwclk);
+
+	return cygnus_genpll_status(bcm_clk, parent_rate);
+}
+
+static const struct clk_ops cygnus_genpll_ops = {
+	.recalc_rate = cygnus_genpll_recalc_rate,
+};
+
+/*
+ * Calculates clock rate of the GENPLL channel requested. The clock rate is
+ * calculated as: the configured clock rate
+ *     Parent clock rate / mdiv
+ */
+static unsigned long cygnus_genpll_chan_get_rate(struct cygnus_clk *clk,
+	unsigned long parent_rate, int enableb_ch_shift)
+{
+	u32 reg;
+	unsigned enable;
+	unsigned mdiv;
+	unsigned offset = 0;
+	unsigned shift = 0;
+
+	/*
+	 * Read ENABLEB_CH to determine which channels are enabled. The enable
+	 * bits are inversed: 0 = channel enabled, 1 = channel disabled.
+	 */
+	reg = readl(clk->regs_base + GENPLL_CONTROL1_OFFSET);
+	enable = ((reg >> enableb_ch_shift) &
+		GENPLL_ENABLEB_CH_MASK) ^ GENPLL_ENABLEB_CH_MASK;
+
+	/* If channel is disabled the rate is 0. */
+	if ((enable & (1 << clk->chan)) == 0) {
+		clk->rate = 0;
+		return -EIO;
+	}
+
+	/* MDIV for the 6 channels is spread over two registers. */
+	switch (clk->chan) {
+	case 0:
+		offset = GENPLL_CONTROL8_OFFSET; shift = 0;
+		break;
+
+	case 1:
+		offset = GENPLL_CONTROL8_OFFSET; shift = 10;
+		break;
+
+	case 2:
+		offset = GENPLL_CONTROL8_OFFSET; shift = 20;
+		break;
+
+	case 3:
+		offset = GENPLL_CONTROL9_OFFSET; shift = 0;
+		break;
+
+	case 4:
+		offset = GENPLL_CONTROL9_OFFSET; shift = 10;
+		break;
+
+	case 5:
+		offset = GENPLL_CONTROL9_OFFSET; shift = 20;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	/* Read MDIV (post divider ratio) for requested channel. */
+	reg = readl(clk->regs_base + offset);
+	mdiv = (reg >> shift) & GENPLL_MDIV_MASK;
+
+	/* When divisor is 0, it behaves as max+1. */
+	if (mdiv == 0)
+		mdiv = 256;
+
+	clk->rate = parent_rate / mdiv;
+
+	pr_debug("GENPLL[%d] mdiv=%u parent rate=%lu rate=%lu\n",
+		clk->chan, mdiv, parent_rate, clk->rate);
+
+	return clk->rate;
+}
+
+/*
+ * Powers on the audio PLL for the audio channel from the PLL. No other
+ * GENPLL channels require powering on.
+ */
+static int cygnus_genpll_chan_prepare(struct clk_hw *hwclk)
+{
+	struct cygnus_clk *clk = to_cygnus_clk(hwclk);
+	struct clk *parent_clk = clk_get_parent(hwclk->clk);
+	struct cygnus_clk *cyg_parent_clk =
+		to_cygnus_clk(__clk_get_hw(parent_clk));
+
+	if (WARN_ON(!cyg_parent_clk->pll_ctrl_reg))
+		return -EIO;
+
+	if (clk->chan == GENPLL_CH4_ASIU_AUDIO_CLK) {
+		pr_debug("GENPLL[%d]: Powering on audio PLL/LDO\n", clk->chan);
+		cygnus_audio_genpll_power_on_off(
+			cyg_parent_clk->pll_ctrl_reg, true);
+	}
+
+	return 0;
+}
+
+/*
+ * Powers off the audio PLL for the audio channel from the PLL. No other
+ * GENPLL channels require powering off.
+ */
+static void cygnus_genpll_chan_unprepare(struct clk_hw *hwclk)
+{
+	struct cygnus_clk *clk = to_cygnus_clk(hwclk);
+	struct clk *parent_clk = clk_get_parent(hwclk->clk);
+	struct cygnus_clk *cyg_parent_clk =
+		to_cygnus_clk(__clk_get_hw(parent_clk));
+
+	if (WARN_ON(!cyg_parent_clk->pll_ctrl_reg))
+		return;
+
+	if (clk->chan == GENPLL_CH4_ASIU_AUDIO_CLK) {
+		pr_debug("GENPLL[%d]: Powering down audio PLL and LDO\n",
+			clk->chan);
+		cygnus_audio_genpll_power_on_off(cyg_parent_clk->pll_ctrl_reg,
+			false);
+	}
+}
+
+static unsigned long cygnus_genpll_chan_recalc_rate(struct clk_hw *hwclk,
+	unsigned long parent_rate)
+{
+	struct cygnus_clk *bcm_clk = to_cygnus_clk(hwclk);
+
+	return cygnus_genpll_chan_get_rate(bcm_clk, parent_rate,
+		GENPLL_ENABLEB_CH_SHIFT);
+}
+
+/*
+ * Enables GENPLL channels. The only PLL channel that is controlled through
+ * the top clock gating control is the audio clock which requires enabling.
+ *
+ * Individual channels aren't enabled/disabled on the PLL because they are
+ * enabled by default and drivers don't always refer to them, meaning the
+ * clock framework would disable them. This can be added later when power
+ * saving is a concern.
+ */
+static int cygnus_genpll_chan_enable(struct clk_hw *hwclk)
+{
+	struct cygnus_clk *clk = to_cygnus_clk(hwclk);
+	struct clk *parent_clk = clk_get_parent(hwclk->clk);
+	struct cygnus_clk *cyg_parent_clk =
+		to_cygnus_clk(__clk_get_hw(parent_clk));
+	int parent_rate;
+
+	if (WARN_ON(!cyg_parent_clk->clock_gate_ctrl_reg))
+		return -EIO;
+
+	pr_debug("Enable GENPLL chan %d\n", clk->chan);
+
+	if (clk->chan == GENPLL_CH4_ASIU_AUDIO_CLK) {
+		cygnus_clkgate_enable_disable(
+			cyg_parent_clk->clock_gate_ctrl_reg,
+			AUD_CLK_GATE_EN, true);
+
+		/* Ensure parent's clock rate is calculated. */
+		parent_rate = clk_get_rate(parent_clk);
+		if (WARN_ON(!parent_rate))
+			return -EIO;
+	}
+
+	return 0;
+}
+
+static void cygnus_genpll_chan_disable(struct clk_hw *hwclk)
+{
+	struct cygnus_clk *clk = to_cygnus_clk(hwclk);
+	struct clk *parent_clk = clk_get_parent(hwclk->clk);
+	struct cygnus_clk *cyg_parent_clk =
+		to_cygnus_clk(__clk_get_hw(parent_clk));
+
+	if (WARN_ON(!cyg_parent_clk->clock_gate_ctrl_reg))
+		return;
+
+	pr_debug("GENPLL: disable chan %d\n", clk->chan);
+
+	/* Enable audio clock. */
+	if (clk->chan == GENPLL_CH4_ASIU_AUDIO_CLK)
+		cygnus_clkgate_enable_disable(
+			cyg_parent_clk->clock_gate_ctrl_reg,
+			AUD_CLK_GATE_EN, false);
+}
+
+static const struct clk_ops cygnus_genpll_chan_ops = {
+	.prepare = cygnus_genpll_chan_prepare,
+	.unprepare = cygnus_genpll_chan_unprepare,
+	.enable = cygnus_genpll_chan_enable,
+	.disable = cygnus_genpll_chan_disable,
+	.recalc_rate = cygnus_genpll_chan_recalc_rate,
+};
+
+static __init struct clk *cygnus_clock_init(struct device_node *node,
+	const struct clk_ops *ops)
+{
+	u32 channel = 0;
+	struct clk *clk;
+	struct cygnus_clk *cygnus_clk;
+	const char *clk_name = node->name;
+	const char *parent_name;
+	struct clk_init_data init;
+	int rc;
+
+	pr_debug("Clock name %s\n", node->name);
+
+	cygnus_clk = kzalloc(sizeof(*cygnus_clk), GFP_KERNEL);
+	if (WARN_ON(!cygnus_clk))
+		return NULL;
+
+	cygnus_clk->state = CLK_DISABLED;
+
+	/* Read base address from device tree and map to virtual address. */
+	cygnus_clk->regs_base = of_iomap(node, CYGNUS_CLK_BASE_REG);
+	if (WARN_ON(!cygnus_clk->regs_base))
+		goto err_alloc;
+
+	/* Read optional base addresses for PLL control and clock gating. */
+	cygnus_clk->clock_gate_ctrl_reg = of_iomap(node,
+		CYGNUS_CLK_GATE_CTRL_REG);
+	cygnus_clk->pll_ctrl_reg = of_iomap(node, CYGNUS_PLL_CTRL_REG);
+
+	of_property_read_u32(node, "channel", &channel);
+	cygnus_clk->chan = channel;
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	/*
+	 * Internal divider is optional and used for PLL derived clocks with
+	 * hardcoded dividers.
+	 */
+	cygnus_clk->internal_div = CLK_RATE_NO_DIV;
+	of_property_read_u32(node, "div", &cygnus_clk->internal_div);
+
+	init.name = clk_name;
+	init.ops = ops;
+	init.flags = CLK_GET_RATE_NOCACHE;
+	parent_name = of_clk_get_parent_name(node, 0);
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	cygnus_clk->hw.init = &init;
+
+	clk = clk_register(NULL, &cygnus_clk->hw);
+	if (WARN_ON(IS_ERR(clk)))
+		goto err_unmap;
+
+	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+	if (WARN_ON(IS_ERR_VALUE(rc)))
+		goto err_unregister;
+
+	rc = clk_register_clkdev(clk, clk_name, NULL);
+	if (WARN_ON(IS_ERR_VALUE(rc)))
+		goto err_provider;
+
+	return clk;
+
+err_provider:
+	of_clk_del_provider(node);
+
+err_unregister:
+	clk_unregister(clk);
+
+err_unmap:
+	iounmap(cygnus_clk->regs_base);
+	iounmap(cygnus_clk->clock_gate_ctrl_reg);
+	iounmap(cygnus_clk->pll_ctrl_reg);
+
+err_alloc:
+	kfree(cygnus_clk);
+
+	return NULL;
+}
+
+static void __init cygnus_lcpll_init(struct device_node *node)
+{
+	cygnus_clock_init(node, &cygnus_lcpll_ops);
+}
+CLK_OF_DECLARE(cygnus_lcpll, "brcm,cygnus-lcpll-clk", cygnus_lcpll_init);
+
+static void __init cygnus_genpll_init(struct device_node *node)
+{
+	cygnus_clock_init(node, &cygnus_genpll_ops);
+}
+CLK_OF_DECLARE(cygnus_genpll, "brcm,cygnus-genpll-clk", cygnus_genpll_init);
+
+static void __init cygnus_lcpll_ch_init(struct device_node *node)
+{
+	cygnus_clock_init(node, &cygnus_lcpll_chan_ops);
+}
+CLK_OF_DECLARE(cygnus_lcpll_ch, "brcm,cygnus-lcpll-ch", cygnus_lcpll_ch_init);
+
+static void __init cygnus_genpll_ch_init(struct device_node *node)
+{
+	cygnus_clock_init(node, &cygnus_genpll_chan_ops);
+}
+CLK_OF_DECLARE(cygnus_genpll_ch, "brcm,cygnus-genpll-ch",
+	cygnus_genpll_ch_init);
+
+/*
+ * Some clocks on Cygnus are derived from the oscillator directly without
+ * going through either the GENPLL or LCPLL. These clocks have specific
+ * registers for their dividers. The clocks included are: keypad, ADC, PWM.
+ */
+
+#define ASIU_CLK_DIV_ENABLE_SHIFT  31
+#define ASIU_CLK_DIV_ENABLE_MASK   0x1
+#define ASIU_CLK_DIV_HIGH_SHIFT    16
+#define ASIU_CLK_DIV_HIGH_MASK     0x3ff
+#define ASIU_CLK_DIV_LOW_SHIFT     0
+#define ASIU_CLK_DIV_LOW_MASK      0x3ff
+
+/*
+ * Calculate clock frequency for clocks derived from oscillator.
+ *
+ * @return The clock rate in Hz
+ */
+static int cygnus_osc_derived_clk_get_rate(struct cygnus_clk *clk,
+	unsigned long parent_rate)
+{
+	int reg_val;
+	int enabled;
+	int clk_div_high;
+	int clk_div_low;
+	unsigned long rate = 0;
+
+	reg_val = readl(clk->regs_base);
+
+	/* Ensure clock is enabled. */
+	enabled = (reg_val >> ASIU_CLK_DIV_ENABLE_SHIFT) &
+		ASIU_CLK_DIV_ENABLE_MASK;
+	if (!enabled)
+		return rate;
+
+	clk_div_high = (reg_val >> ASIU_CLK_DIV_HIGH_SHIFT) &
+		ASIU_CLK_DIV_HIGH_MASK;
+	clk_div_high += 1;
+
+	clk_div_low = (reg_val >> ASIU_CLK_DIV_LOW_SHIFT) &
+		ASIU_CLK_DIV_LOW_MASK;
+	clk_div_low += 1;
+
+	/*
+	 * Rate calculated as:
+	 *   (oscillator rate) / ((clk high + 1) + (clk_low + 1))
+	 */
+	rate = parent_rate / (clk_div_high + clk_div_low);
+
+	pr_debug("Osc derived clk: Prate=%lu div_high=%d div_low=%d rate=%lu\n",
+		parent_rate, clk_div_high, clk_div_low, rate);
+
+	return rate;
+}
+
+static unsigned long cygnus_osc_derived_clk_recalc_rate(struct clk_hw *hwclk,
+	unsigned long parent_rate)
+{
+	struct cygnus_clk *bcm_clk = to_cygnus_clk(hwclk);
+
+	return cygnus_osc_derived_clk_get_rate(bcm_clk, parent_rate);
+}
+
+/*
+ * Enables the top clock gating control for clocks that require it.
+ */
+static int cygnus_osc_derived_clk_enable(struct clk_hw *hwclk)
+{
+	struct cygnus_clk *clk = to_cygnus_clk(hwclk);
+	struct clk *parent_clk = clk_get_parent(hwclk->clk);
+	int parent_rate;
+	u32 val;
+
+	if (WARN_ON(!clk->clock_gate_ctrl_reg))
+		return 0;
+
+	pr_debug("OSC derived clk enable chan %d\n", clk->chan);
+
+	/* Enable top clock gating control if necessary. */
+	if (clk->chan == OSC_DERIVED_CH0_KEYPAD_CLK)
+		cygnus_clkgate_enable_disable(clk->clock_gate_ctrl_reg,
+			KEYPAD_CLK_GATE_EN, true);
+	else if (clk->chan == OSC_DERIVED_CH1_ADC_CLK)
+		cygnus_clkgate_enable_disable(clk->clock_gate_ctrl_reg,
+			ADC_CLK_GATE_EN, true);
+
+	/* Set and enable divider if specified. */
+	if (clk->internal_div != CLK_RATE_NO_DIV) {
+		val = (1 << ASIU_CLK_DIV_ENABLE_SHIFT) |
+			((clk->internal_div & ASIU_CLK_DIV_HIGH_MASK) <<
+			ASIU_CLK_DIV_HIGH_SHIFT) |
+			((clk->internal_div & ASIU_CLK_DIV_LOW_MASK) <<
+			ASIU_CLK_DIV_LOW_SHIFT);
+		writel(val, clk->regs_base);
+	}
+
+	/* Ensure parent's clock rate is calculated. */
+	parent_rate = clk_get_rate(parent_clk);
+	if (WARN_ON(!parent_rate))
+		return -EIO;
+
+	return 0;
+}
+
+/*
+ * Disables top clock gating control for clocks that were enabled.
+ */
+static void cygnus_osc_derived_clk_disable(struct clk_hw *hwclk)
+{
+	struct cygnus_clk *clk = to_cygnus_clk(hwclk);
+
+	if (WARN_ON(!clk->clock_gate_ctrl_reg))
+		return;
+
+	pr_debug("OSC derived clk disable chan %d\n", clk->chan);
+
+	/* Disable top clock gating control if necessary. */
+	if (clk->chan == OSC_DERIVED_CH0_KEYPAD_CLK)
+		cygnus_clkgate_enable_disable(clk->clock_gate_ctrl_reg,
+			KEYPAD_CLK_GATE_EN, false);
+	else if (clk->chan == OSC_DERIVED_CH1_ADC_CLK)
+		cygnus_clkgate_enable_disable(clk->clock_gate_ctrl_reg,
+			ADC_CLK_GATE_EN, false);
+}
+
+static const struct clk_ops cygnus_osc_derived_clk_ops = {
+	.enable = cygnus_osc_derived_clk_enable,
+	.disable = cygnus_osc_derived_clk_disable,
+	.recalc_rate = cygnus_osc_derived_clk_recalc_rate,
+};
+
+static void __init cygnus_osc_derived_init(struct device_node *node)
+{
+	cygnus_clock_init(node, &cygnus_osc_derived_clk_ops);
+}
+
+CLK_OF_DECLARE(cygnus_osc_derived, "brcm,cygnus-osc-derived",
+	cygnus_osc_derived_init);
+
+/*
+ * Some clocks are derived from a PLL. The dividers are internal and can't
+ * be read from a register. If the parent clock rate changes then the derived
+ * clock rates scale accordingly.
+ */
+
+ /*
+  * Calculate clock frequency for clocks derived from oscillator.
+  * Rate calculated as:  parent rate / internal divider
+  * The internal divider must be specified in DT.
+  *
+  * @return The clock rate in Hz.
+  */
+static unsigned long cygnus_pll_derived_clk_get_rate(struct cygnus_clk *clk,
+	unsigned long parent_rate)
+{
+	unsigned long rate = parent_rate / clk->internal_div;
+
+	pr_debug("PLL derived clk: Prate=%lu rate=%lu\n", parent_rate, rate);
+
+	return rate;
+}
+
+static unsigned long cygnus_pll_derived_clk_recalc_rate(struct clk_hw *hwclk,
+	unsigned long parent_rate)
+{
+	struct cygnus_clk *bcm_clk = to_cygnus_clk(hwclk);
+
+	return cygnus_pll_derived_clk_get_rate(bcm_clk, parent_rate);
+}
+
+static const struct clk_ops cygnus_pll_derived_clk_ops = {
+	.recalc_rate = cygnus_pll_derived_clk_recalc_rate,
+};
+
+static void __init cygnus_pll_derived_init(struct device_node *node)
+{
+	cygnus_clock_init(node, &cygnus_pll_derived_clk_ops);
+}
+
+CLK_OF_DECLARE(cygnus_pll_derived, "brcm,cygnus-pll-derived",
+	cygnus_pll_derived_init);
+
+/*
+ * MIPI DSI GENPLL
+ */
+
+/*
+ * Get PLL running status and calculate output frequency.
+ */
+static unsigned long cygnus_mipipll_get_rate(struct cygnus_clk *clk,
+	unsigned long parent_rate)
+{
+	u32 reg;
+	u32 rate;
+	u32 pdiv;
+	u32 ndiv_int;
+	u32 ndiv_frac;
+	int pll_locked;
+
+	/* Read lock field from PLL status register. It must be unlocked. */
+	reg = readl(clk->regs_base + GENPLL_STATUS_OFFSET);
+
+	pll_locked = (reg >> GENPLL_STATUS_LOCK_SHIFT) &
+		GENPLL_STATUS_LOCK_MASK;
+	if (pll_locked) {
+		clk->rate = 0;
+		return -EIO;
+	}
+	/*
+	 * Calculate PLL frequency:
+	 *   PLL freq = ((crystal clock / pdiv) * ndiv ) / mdiv
+	 */
+
+	/* Get PLL feedback divider values. */
+	reg = readl(clk->regs_base + GENPLL_CONTROL4_OFFSET);
+
+	/* Feedback divider integer and fractional parts. */
+	ndiv_int = (reg >> GENPLL_CONTROL4_NDIV_INT_SHIFT) &
+		GENPLL_CONTROL4_NDIV_INT_MASK;
+	ndiv_frac = (reg >> GENPLL_CONTROL4_NDIV_FRAC_SHIFT) &
+		GENPLL_CONTROL4_NDIV_FRAC_MASK;
+	ndiv_int += ndiv_frac / NDIV_FRAC_DIVISOR;
+
+	/* Get pdiv. */
+	reg = readl(clk->regs_base + GENPLL_CONTROL5_OFFSET);
+	pdiv = (reg >> GENPLL_CONTROL5_PDIV_SHIFT) &
+		GENPLL_CONTROL5_PDIV_MASK;
+
+	/* If pdiv is 0, divide by 0.5 - doubler. */
+	if (pdiv == 0)
+		rate = parent_rate * 2;
+	else
+		rate = parent_rate / pdiv;
+
+	clk->rate = rate * ndiv_int;
+
+	pr_debug("[MIPI PLL] parent rate=%lu, ndiv int=%d, pdiv=%d, rate=%lu\n",
+	    parent_rate, ndiv_int, pdiv, clk->rate);
+
+	return clk->rate;
+}
+
+/*
+ * Powers on the necessary PLL's and LDO for MIPI GEN PLL.
+ */
+static int cygnus_mipipll_prepare(struct clk_hw *hwclk)
+{
+	struct cygnus_clk *clk = to_cygnus_clk(hwclk);
+
+	if (WARN_ON(!clk->pll_ctrl_reg))
+		return -EIO;
+
+	pr_debug("Powering up MIPI PLL and LDO\n");
+
+	/* Power on the PLL. */
+	cygnus_mipi_genpll_power_on_off(clk->pll_ctrl_reg, true);
+
+	clk->state = CLK_PREPARED;
+
+	return 0;
+}
+
+/*
+ * Powers off the PLL's and LDO for MIPI GEN PLL.
+ */
+static void cygnus_mipipll_unprepare(struct clk_hw *hwclk)
+{
+	struct cygnus_clk *clk = to_cygnus_clk(hwclk);
+
+	if (WARN_ON(!clk->pll_ctrl_reg))
+		return;
+
+	pr_debug("Powering down MIPI PLL and LDO\n");
+
+	/* Power off the PLL. */
+	cygnus_mipi_genpll_power_on_off(clk->pll_ctrl_reg, false);
+
+	clk->state = CLK_DISABLED;
+}
+
+static unsigned long cygnus_mipipll_recalc_rate(struct clk_hw *hwclk,
+	unsigned long parent_rate)
+{
+	struct cygnus_clk *bcm_clk = to_cygnus_clk(hwclk);
+
+	if (bcm_clk->state != CLK_ENABLED)
+		return 0;
+
+	return cygnus_mipipll_get_rate(bcm_clk, parent_rate);
+}
+
+/*
+ * Enables the MIPI DSI clock gate through the top clock gating control.
+ */
+static int cygnus_mipipll_enable(struct clk_hw *hwclk)
+{
+	struct cygnus_clk *clk = to_cygnus_clk(hwclk);
+
+	if (WARN_ON(!clk->clock_gate_ctrl_reg))
+		return -EIO;
+
+	pr_debug("Enable MIPI PLL\n");
+
+	/* Enable MIPI DSI clock. */
+	cygnus_clkgate_enable_disable(clk->clock_gate_ctrl_reg,
+		MIPI_DSI_CLK_GATE_EN, true);
+
+	clk->state = CLK_ENABLED;
+
+	return 0;
+}
+
+/*
+ * Turns off the MIPI PLL clock.
+ */
+static void cygnus_mipipll_disable(struct clk_hw *hwclk)
+{
+	struct cygnus_clk *clk = to_cygnus_clk(hwclk);
+
+	if (WARN_ON(!clk->clock_gate_ctrl_reg))
+		return;
+
+	pr_debug("Disabling MIPI PLL and LDO\n");
+
+	/* Disable MIPI DSI clock through top clock gating control. */
+	cygnus_clkgate_enable_disable(clk->clock_gate_ctrl_reg,
+		MIPI_DSI_CLK_GATE_EN, false);
+
+	clk->state = CLK_DISABLED;
+}
+
+static const struct clk_ops cygnus_mipipll_ops = {
+	.prepare = cygnus_mipipll_prepare,
+	.unprepare = cygnus_mipipll_unprepare,
+	.enable = cygnus_mipipll_enable,
+	.disable = cygnus_mipipll_disable,
+	.recalc_rate = cygnus_mipipll_recalc_rate,
+};
+
+static void __init cygnus_mipipll_init(struct device_node *node)
+{
+	cygnus_clock_init(node, &cygnus_mipipll_ops);
+}
+CLK_OF_DECLARE(cygnus_mipipll, "brcm,cygnus-mipipll-clk", cygnus_mipipll_init);
+
+/*
+ * MIPI PLL clock channel management.
+ */
+
+/*
+ * Enables a MIPI PLL channel.
+ */
+static void mipi_pll_enable_chan(void __iomem *base, int chan, bool state)
+{
+	u32 val;
+
+	val = readl(base + GENPLL_CONTROL1_OFFSET);
+
+	/* ENABLEB_CH bit set to 0 to enable channel, 1 to disable. */
+	if (state)
+		val &= ~(1 << (chan + MIPI_DSI_GENPLL_ENABLEB_CH_SHIFT));
+	else
+		val |= (1 << (chan + MIPI_DSI_GENPLL_ENABLEB_CH_SHIFT));
+
+	writel(val, base + GENPLL_CONTROL1_OFFSET);
+}
+
+static unsigned long cygnus_mipipll_chan_recalc_rate(struct clk_hw *hwclk,
+	unsigned long parent_rate)
+{
+	struct cygnus_clk *clk = to_cygnus_clk(hwclk);
+
+	if (WARN_ON(!clk->clock_gate_ctrl_reg))
+		return 0;
+
+	if (clk->state != CLK_ENABLED)
+		return 0;
+
+	return cygnus_genpll_chan_get_rate(clk, parent_rate,
+		MIPI_DSI_GENPLL_ENABLEB_CH_SHIFT);
+}
+
+/*
+ * Enables the PLL channel and the top clock gating control for clocks that
+ * are controlled through it.
+ */
+static int cygnus_mipipll_chan_enable(struct clk_hw *hwclk)
+{
+	struct cygnus_clk *clk = to_cygnus_clk(hwclk);
+	struct clk *parent_clk = clk_get_parent(hwclk->clk);
+	int parent_rate;
+
+	if (WARN_ON(!clk->clock_gate_ctrl_reg))
+		return -EIO;
+
+	pr_debug("Enable MIPI PLL chan %d\n", clk->chan);
+
+	/*
+	 * Some MIPI PLL channels have to be enabled through the top clock
+	 * gating ctrl. Add support for other channels here.
+	 */
+	if (clk->chan == MIPI_PLL_CH1_LCD_CLK) {
+		cygnus_clkgate_enable_disable(clk->clock_gate_ctrl_reg,
+			LCD_CLK_GATE_EN, true);
+	}
+
+	/* Enable the PLL channel. */
+	mipi_pll_enable_chan(clk->regs_base, clk->chan, true);
+
+	clk->state = CLK_ENABLED;
+
+	/* Ensure parent's clock rate is calculated. */
+	parent_rate = clk_get_rate(parent_clk);
+	if (WARN_ON(!parent_rate))
+		return -EIO;
+
+	return 0;
+}
+
+/*
+ * Disables the PLL channel. Some channels also have to be shut down through
+ * the top clock gating control.
+ */
+static void cygnus_mipipll_chan_disable(struct clk_hw *hwclk)
+{
+	struct cygnus_clk *clk = to_cygnus_clk(hwclk);
+
+	if (WARN_ON(!clk->clock_gate_ctrl_reg))
+		return;
+
+	pr_debug("Disable MIPI PLL chan %d\n", clk->chan);
+
+	/* Disable LCD clock through top clock gating control. */
+	if (clk->chan == MIPI_PLL_CH1_LCD_CLK) {
+		cygnus_clkgate_enable_disable(clk->clock_gate_ctrl_reg,
+			LCD_CLK_GATE_EN, false);
+	}
+
+	/* Disable the PLL channel. */
+	mipi_pll_enable_chan(clk->regs_base, clk->chan, false);
+
+	clk->state = CLK_DISABLED;
+}
+
+static const struct clk_ops cygnus_mipipll_chan_ops = {
+	.enable = cygnus_mipipll_chan_enable,
+	.disable = cygnus_mipipll_chan_disable,
+	.recalc_rate = cygnus_mipipll_chan_recalc_rate,
+};
+
+static void __init cygnus_mipipll_ch_init(struct device_node *node)
+{
+	cygnus_clock_init(node, &cygnus_mipipll_chan_ops);
+}
+
+CLK_OF_DECLARE(cygnus_mipipll_ch, "brcm,cygnus-mipipll-ch",
+	cygnus_mipipll_ch_init);
diff --git a/drivers/clk/bcm/clk-iproc.c b/drivers/clk/bcm/clk-iproc.c
new file mode 100644
index 0000000..aca4851
--- /dev/null
+++ b/drivers/clk/bcm/clk-iproc.c
@@ -0,0 +1,451 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/clkdev.h>
+#include <linux/of_address.h>
+
+#define IPROC_CLK_POLICY_FREQ_OFFSET    0x008
+#define IPROC_CLK_POLICY0_MSK_OFFSET    0x010
+#define IPROC_CLK_APB_SW_DIV_OFFSET     0xA10
+#define IPROC_CLK_PLL_ARMA_OFFSET       0xC00
+#define IPROC_CLK_PLL_ARMB_OFFSET       0xC04
+#define IPROC_CLK_PLL_ARMC_OFFSET       0xC08
+#define IPROC_CLK_PLL_ARMCTL5_OFFSET    0xC20
+#define IPROC_CLK_PLL_ARM_OFFSET_OFFSET 0xC24
+#define IPROC_CLK_ARM_DIV_OFFSET        0xE00
+#define IPROC_CLK_POLICY_DBG_OFFSET     0xEC0
+
+#define IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_OVERRIDE_SHIFT        4
+#define IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_MASK                  0xf
+#define IPROC_CLK_POLICY_FREQ_OFFSET_POLICY_FREQ_MASK          0xf
+#define IPROC_CLK_POLICY_FREQ_OFFSET_POLICY_FREQ_SHIFT         8
+#define IPROC_CLK_POLICY_DBG_OFFSET_ACT_FREQ_SHIFT             12
+#define IPROC_CLK_POLICY_DBG_OFFSET_ACT_FREQ_MASK              7
+#define IPROC_CLK_PLL_ARM_OFFSET_PLLARM_OFFSET_SW_CTL_SHIFT    29
+#define CLK_PLL_ARM_OFFSET_PLLARM_NDIV_INT_OFFSET              20
+#define CLK_PLL_ARM_OFFSET_PLLARM_NDIV_INT_MASK                0xff
+#define CLK_PLL_ARM_OFFSET_PLLARM_NDIV_FRAC_OFFSET             0xfffff
+#define CLK_PLL_ARMA_PLLARM_NDIV_INT_SHIFT                     8
+#define CLK_PLL_ARMA_PLLARM_NDIV_INT_MASK                      0x3ff
+#define CLK_PLL_ARMB_PLLARM_NDIV_FRAC_MASK                     0xfffff
+#define CLK_PLL_ARMC_PLLARM_MDIV_MASK                          0xff
+#define CLK_PLL_ARMCTL5_PLLARM_H_MDIV_MASK                     0xff
+#define CLK_PLL_ARMC_PLLARM_BYPCLK_EN_SHIFT                    8
+#define CLK_PLL_ARMA_PLLARM_PDIV_SHIFT                         24
+#define CLK_PLL_ARMA_PLLARM_PDIV_MASK                          0xf
+#define CLK_PLL_ARMA_PLLARM_LOCK_SHIFT                         28
+#define CLK_ARM_DIV_APB0_FREE_DIV_SHIFT                        8
+#define CLK_ARM_DIV_APB0_FREE_DIV_MASK                         0x7
+#define CLK_ARM_DIV_ARM_SWITCH_DIV_SHIFT                       8
+#define CLK_ARM_DIV_ARM_SWITCH_DIV_MASK                        0x3
+#define CLK_APB_SW_DIV_APB_CLK_DIV_MASK                        0x3
+
+struct brcm_clk {
+	struct clk_hw   hw;
+	void __iomem    *regs_base;
+	int             chan;
+	unsigned long   rate;
+};
+
+/* Identifies derived clocks from ARM PLL. */
+enum {
+	ARMPLL_APB0_FREE_CLK   = 0,
+	ARMPLL_ARM_SWITCH_CLK  = 1,
+	ARMPLL_ARM_APB_CLK     = 2,
+	ARMPLL_ARM_PERIPH_CLK  = 3
+};
+
+/* Frequency id's from policy0_freq field of POLICY_FREQ register. */
+enum a9pll_policy_freq {
+	PLL_CRYSTAL_CLK   = 0,
+	PLL_SYS_CLK       = 2,
+	PLL_CH0_SLOW_CLK  = 6,
+	PLL_CH1_FAST_CLK  = 7
+};
+
+#define to_brcm_clk(p) container_of(p, struct brcm_clk, hw)
+
+static int iproc_cru_arm_freq_id(void __iomem *regs_base)
+{
+	u32 reg_f, reg;
+	unsigned policy = 0;
+	unsigned fid;
+	unsigned active_freq;
+
+	/* Read policy frequency. */
+	reg_f = readl(regs_base + IPROC_CLK_POLICY_FREQ_OFFSET);
+
+	/* Check for PLL policy software override. */
+	reg = readl(regs_base + IPROC_CLK_ARM_DIV_OFFSET);
+	if (reg & (1 << IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_OVERRIDE_SHIFT))
+		policy = reg & IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_MASK;
+
+	/* Get frequency ID based on policy. */
+	fid = (reg_f >>
+		(IPROC_CLK_POLICY_FREQ_OFFSET_POLICY_FREQ_SHIFT * policy)) &
+		IPROC_CLK_POLICY_FREQ_OFFSET_POLICY_FREQ_MASK;
+
+	/* Verify freq id from debug register. */
+	reg = readl(regs_base + IPROC_CLK_POLICY_DBG_OFFSET);
+	/* Read current active frequency id. */
+	active_freq = IPROC_CLK_POLICY_DBG_OFFSET_ACT_FREQ_MASK &
+		(reg >> IPROC_CLK_POLICY_DBG_OFFSET_ACT_FREQ_SHIFT);
+
+	if (fid != active_freq) {
+		pr_debug("IPROC CRU clock frequency id override %d->%d\n",
+			fid, active_freq);
+
+		fid = active_freq;
+	}
+
+	pr_debug("Active frequency ID %d\n", fid);
+
+	return fid;
+}
+
+/*
+ * Get ndiv integer and combine with fractional part to create 64 bit
+ * value.
+ */
+static u64 a9pll_get_ndiv(struct brcm_clk *clk)
+{
+	u32 arm_offset_reg;
+	u32 pllarma_reg;
+	u32 pllarmb_reg;
+	u32 ndiv_int;
+	u32 ndiv_frac;
+	u64 ndiv;
+
+	arm_offset_reg = readl(clk->regs_base +
+		IPROC_CLK_PLL_ARM_OFFSET_OFFSET);
+
+    /*
+	 * Check if offset mode is active to determine which register to
+	 * get ndiv from.
+	 */
+	if (arm_offset_reg &
+		(1 << IPROC_CLK_PLL_ARM_OFFSET_PLLARM_OFFSET_SW_CTL_SHIFT)) {
+		/* Offset mode active. Get integer divide from offset reg. */
+		ndiv_int = (arm_offset_reg >>
+			CLK_PLL_ARM_OFFSET_PLLARM_NDIV_INT_OFFSET) &
+			CLK_PLL_ARM_OFFSET_PLLARM_NDIV_INT_MASK;
+
+		if (ndiv_int == 0)
+			ndiv_int = 256;
+
+		/* Get ndiv fractional divider. */
+		ndiv_frac = arm_offset_reg &
+			CLK_PLL_ARM_OFFSET_PLLARM_NDIV_FRAC_OFFSET;
+	} else {
+		/* Offset mode not active so read PLL ndiv from PLLARMA. */
+		pllarma_reg = readl(clk->regs_base + IPROC_CLK_PLL_ARMA_OFFSET);
+		ndiv_int = (pllarma_reg >> CLK_PLL_ARMA_PLLARM_NDIV_INT_SHIFT) &
+			CLK_PLL_ARMA_PLLARM_NDIV_INT_MASK;
+
+		if (ndiv_int == 0)
+			ndiv_int = 1024;
+
+		/* Get ndiv fractional divider. */
+		pllarmb_reg = readl(clk->regs_base + IPROC_CLK_PLL_ARMB_OFFSET);
+		ndiv_frac = pllarmb_reg & CLK_PLL_ARMB_PLLARM_NDIV_FRAC_MASK;
+	}
+
+	ndiv = ((u64) ndiv_int << 20) | ndiv_frac;
+
+	return ndiv;
+}
+
+/*
+ * Determine mdiv (post divider) based on the frequency id being used.
+ * There are 4 clocks that can be used to derive the output clock rate:
+ *    - 25 MHz crystal
+ *    - sys_clk
+ *    - channel 0 (slow clock)
+ *    - channel 1 (fast clock)
+ *
+ * If the slow clock is being used then mdiv is read from PLLARMC. If
+ * the fast clock is being used then the channel 1 mdiv is used.
+ * Otherwise there is no post divider.
+ *
+ * @return The mdiv value. -EIO if an error occurred.
+ */
+static int a9pll_get_mdiv(struct brcm_clk *clk)
+{
+	u32 mdiv;
+	u32 pllarmc_reg;
+	u32 armctl5_reg;
+	u32 freq_id;
+
+	/* Get the policy frequency. */
+	freq_id = iproc_cru_arm_freq_id(clk->regs_base);
+
+	switch (freq_id) {
+	/* There is no divider for these frequency id's. */
+	case PLL_CRYSTAL_CLK:
+	case PLL_SYS_CLK:
+		mdiv = 1;
+		break;
+
+	case PLL_CH0_SLOW_CLK: {
+	    /* Read mdiv (post-divider) from PLLARMC bits 0:7 */
+	    pllarmc_reg = readl(clk->regs_base + IPROC_CLK_PLL_ARMC_OFFSET);
+	    mdiv = pllarmc_reg & CLK_PLL_ARMC_PLLARM_MDIV_MASK;
+	    if (mdiv == 0)
+			mdiv = 256;
+		break;
+	}
+
+	case PLL_CH1_FAST_CLK: {
+		/* Post divider for channel 1 is in CTL5 (pllarm_h_mdiv). */
+		armctl5_reg = readl(clk->regs_base +
+			IPROC_CLK_PLL_ARMCTL5_OFFSET);
+	    mdiv = armctl5_reg & CLK_PLL_ARMCTL5_PLLARM_H_MDIV_MASK;
+	    if (mdiv == 0)
+			mdiv = 256;
+		break;
+	}
+
+	default:
+		return -EIO;
+	}
+
+	return mdiv;
+}
+
+/*
+ * Calculate the output frequency of the ARM PLL. The main output clock
+ * is 'arm_clk'.
+ *
+ * The frequency is calculated based on the ARM PLL divider values:
+ *	 pdiv = ARM PLL input pre-divider
+ *   ndiv = ARM PLL feedback divider
+ *   mdiv = ARM PLL post divider
+ *
+ * The frequency is calculated by:
+ *   ((ndiv * parent clock rate) / pdiv) / mdiv
+ */
+static int a9pll_status(struct brcm_clk *clk, unsigned long parent_rate)
+{
+	u32 pllarma_reg;
+	u32 pllarmc_reg;
+	u32 pdiv;
+	u32 mdiv;
+	u64 ndiv;
+	u32 arm_clk_freq;
+
+	pr_debug("a9pll_status: clk 0x%x\n", (unsigned int)clk);
+
+	BUG_ON(!clk->regs_base);
+
+	pllarma_reg = readl(clk->regs_base + IPROC_CLK_PLL_ARMA_OFFSET);
+	pllarmc_reg = readl(clk->regs_base + IPROC_CLK_PLL_ARMC_OFFSET);
+
+	/* Check if PLL is in bypass mode - input frequency to output */
+	if (pllarmc_reg & (1 << CLK_PLL_ARMC_PLLARM_BYPCLK_EN_SHIFT)) {
+		clk->rate = parent_rate;
+		return 0;
+	}
+
+	/* Check if PLL is locked. It must be unlocked. */
+	if ((pllarma_reg &
+		(1 << CLK_PLL_ARMA_PLLARM_LOCK_SHIFT)) == 0) {
+		clk->rate = 0;
+		return -EIO;
+	}
+
+	/* Read pdiv from PLLARMA. */
+	pdiv = (pllarma_reg >> CLK_PLL_ARMA_PLLARM_PDIV_SHIFT) &
+		CLK_PLL_ARMA_PLLARM_PDIV_MASK;
+	if (pdiv == 0)
+		pdiv = 16;
+
+	/* Determine ndiv. */
+	ndiv = a9pll_get_ndiv(clk);
+
+	/* Determine mdiv (post divider). */
+	mdiv = a9pll_get_mdiv(clk);
+	if (mdiv == -EIO) {
+		clk->rate = 0;
+		return -EIO;
+	}
+
+	/* Calculate clock frequency. */
+	arm_clk_freq = (ndiv * parent_rate) >> 20;
+	arm_clk_freq = (arm_clk_freq / pdiv) / mdiv;
+
+	clk->rate = arm_clk_freq;
+
+	pr_debug("ARM PLL (arm_clk) rate %lu. parent rate = %lu, ",
+		clk->rate, parent_rate);
+	pr_debug("ndiv_int = %d, pdiv = %d, mdiv = %d\n",
+		 (u32)ndiv >> 20, pdiv, mdiv);
+
+	return clk->rate;
+}
+
+static unsigned long clk_a9pll_recalc_rate(struct clk_hw *hwclk,
+	unsigned long parent_rate)
+{
+	struct brcm_clk *bcm_clk = to_brcm_clk(hwclk);
+
+	return a9pll_status(bcm_clk, parent_rate);
+}
+
+static const struct clk_ops a9pll_ops = {
+	.recalc_rate = clk_a9pll_recalc_rate,
+};
+
+/*
+ * Get status of any of the ARMPLL output channels
+ */
+static int a9pll_chan_status(struct brcm_clk *clk, unsigned long parent_rate)
+{
+	u32 reg;
+	unsigned div;
+
+	BUG_ON(!clk->regs_base);
+
+	reg = readl(clk->regs_base + IPROC_CLK_ARM_DIV_OFFSET);
+	pr_debug("Clock Div = %#x\n", reg);
+
+	switch (clk->chan) {
+	case ARMPLL_APB0_FREE_CLK:
+		/* apb0_free_div bits 10:8 */
+		div = (reg >> CLK_ARM_DIV_APB0_FREE_DIV_SHIFT) &
+			CLK_ARM_DIV_APB0_FREE_DIV_MASK;
+		div++;
+		break;
+
+	case ARMPLL_ARM_SWITCH_CLK:
+		/* arm_switch_div bits 6:5 */
+		div = (reg >> CLK_ARM_DIV_ARM_SWITCH_DIV_SHIFT) &
+			CLK_ARM_DIV_ARM_SWITCH_DIV_MASK;
+		div++;
+		break;
+
+	case ARMPLL_ARM_APB_CLK:
+		/* IPROC_CLK_APB_SW_DIV_REG apb_clk_div bits 1:0 */
+		reg = readl(clk->regs_base + IPROC_CLK_APB_SW_DIV_OFFSET);
+		div = reg & CLK_APB_SW_DIV_APB_CLK_DIV_MASK;
+		div++;
+		break;
+
+	case ARMPLL_ARM_PERIPH_CLK:      /* periph_clk */
+		div = 2;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	clk->rate = parent_rate / div;
+	pr_debug("Clock rate A9PLL chan 0x%x: %lu, div: %d\n",
+		clk->chan, clk->rate, div);
+
+	return clk->rate;
+}
+
+static unsigned long clk_a9pll_chan_recalc_rate(struct clk_hw *hwclk,
+	unsigned long parent_rate)
+{
+	struct brcm_clk *bcm_clk = to_brcm_clk(hwclk);
+
+	return a9pll_chan_status(bcm_clk, parent_rate);
+}
+
+static const struct clk_ops a9pll_chan_ops = {
+	.recalc_rate = clk_a9pll_chan_recalc_rate,
+};
+
+static __init struct clk *iproc_clock_init(struct device_node *node,
+	const struct clk_ops *ops)
+{
+	u32 channel = 0;
+	struct clk *clk;
+	struct brcm_clk *brcm_clk;
+	const char *clk_name = node->name;
+	const char *parent_name;
+	struct clk_init_data init;
+	int rc;
+
+	pr_debug("Clock name %s\n", node->name);
+
+	rc = of_property_read_u32(node, "channel", &channel);
+	brcm_clk = kzalloc(sizeof(*brcm_clk), GFP_KERNEL);
+	if (WARN_ON(!brcm_clk))
+		return NULL;
+
+	/* Read base address from device tree and map to virtual address. */
+	brcm_clk->regs_base = of_iomap(node, 0);
+	if (WARN_ON(!brcm_clk->regs_base))
+		goto err_alloc;
+
+	brcm_clk->chan = channel;
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	init.name = clk_name;
+	init.ops = ops;
+	init.flags = 0;
+	parent_name = of_clk_get_parent_name(node, 0);
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	brcm_clk->hw.init = &init;
+
+	clk = clk_register(NULL, &brcm_clk->hw);
+	if (WARN_ON(IS_ERR(clk)))
+		goto err_unmap;
+
+	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+	if (WARN_ON(IS_ERR_VALUE(rc)))
+		goto err_unregister;
+
+	rc = clk_register_clkdev(clk, clk_name, NULL);
+	if (WARN_ON(IS_ERR_VALUE(rc)))
+		goto err_provider;
+
+	return clk;
+
+err_provider:
+	of_clk_del_provider(node);
+
+err_unregister:
+	clk_unregister(clk);
+
+err_unmap:
+	iounmap(brcm_clk->regs_base);
+
+err_alloc:
+	kfree(brcm_clk);
+
+	return NULL;
+}
+
+static void __init iproc_armpll_init(struct device_node *node)
+{
+	iproc_clock_init(node, &a9pll_ops);
+}
+CLK_OF_DECLARE(iproc_armpllx, "brcm,iproc-arm-a9pll", iproc_armpll_init);
+
+static void __init iproc_arm_ch_init(struct device_node *node)
+{
+	iproc_clock_init(node, &a9pll_chan_ops);
+}
+CLK_OF_DECLARE(iproc_arm_ch, "brcm,iproc-arm-ch", iproc_arm_ch_init);
-- 
1.7.9.5

[PATCH 3/6] dt-bindings: Document Broadcom Cygnus SoC and clock driver

[Scott Branden]

From: Jonathan Richardson <jonathar@broadcom.com>

Reviewed-by: Arun Parameswaran <aparames@broadcom.com>
Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 Documentation/devicetree/bindings/arm/cygnus.txt   |   12 ++
 .../devicetree/bindings/clock/clk-cygnus.txt       |  121 ++++++++++++++++++++
 .../devicetree/bindings/clock/clk-iproc.txt        |   48 ++++++++
 3 files changed, 181 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/cygnus.txt
 create mode 100644 Documentation/devicetree/bindings/clock/clk-cygnus.txt
 create mode 100644 Documentation/devicetree/bindings/clock/clk-iproc.txt

diff --git a/Documentation/devicetree/bindings/arm/cygnus.txt b/Documentation/devicetree/bindings/arm/cygnus.txt
new file mode 100644
index 0000000..a210377
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cygnus.txt
@@ -0,0 +1,12 @@
+Broadcom Cygnus device tree bindings
+------------------------------------
+
+All Cygnus boards shall have the following properties:
+
+Required root node property:
+	- compatible = "brcm,cygnus";
+
+Boards variants shall have the following additional properties:
+
+Required root node property for the BCM911360_ENTPHN board:
+	- compatible = "brcm,bcm911360_entphn";
diff --git a/Documentation/devicetree/bindings/clock/clk-cygnus.txt b/Documentation/devicetree/bindings/clock/clk-cygnus.txt
new file mode 100644
index 0000000..7e03837
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clk-cygnus.txt
@@ -0,0 +1,121 @@
+Broadcom Cygnus Clock Controller
+
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The Cygnus clock controller manages several PLL's and their channels, found only
+on the Cygnus chip. Clocks that are common to iProc can be found in the iProc
+clock controller. The controllers are split into a parent-child relationship
+where the parent is the PLL and the child controls the PLL's channels.
+
+All PLL's are derived from a 25MHz oscillator. The PLL's controlled are the
+GENPLL, LCPLL, the MIPI PLL. In addition, there are two clocks derived from
+GENPLL channel 0, and three that are derived directly from the oscillator.
+
+Required properties:
+- compatible: Must be one of the following:
+    "brcm,cygnus-lcpll-clk" - Controls LCPLL.
+    "brcm,cygnus-lcpll-ch" -  Controls LCPLL (parent) channels
+    "brcm,cygnus-genpll-clk" - Controls parent GENPLL
+    "brcm,cygnus-genpll-ch" - Controls GENPLL (parent) channels
+    "brcm,cygnus-mipipll-clk" - Controls MIPI PLL
+    "brcm,cygnus-mipipll-ch" - Controls parent MIPI PLL (parent) channels
+    "brcm,cygnus-osc-derived" - Controls oscillator (parent) derived channels
+        not controlled by any PLL.
+    "brcm,cygnus-pll-derived" - Controls clocks derived from GENPLL channel 0.
+	  These clocks have hard wired internal dividers and their clock rates
+	  scale according to the GENPLL channel.
+
+- reg: First register is the base address of the PLL. Register 2 and 3 are
+  required by some clocks. They are the top clock gating control used to
+  enable/disable clocks (ch 1), and the CRMU PLL AON CONTROL register which
+  powers on PLL/LDO's (ch 2).
+
+- clocks: The input parent clock phandle for the clock. This is either a PLL,
+  oscillator, or GENPLL channel 0.
+
+- channel: The PLL channel that the clock belongs to. This is used for
+  "brcm,cygnus-lcpll-ch", "brcm,cygnus-genpll-ch", "brcm,cygnus-mipipll-ch",
+  "brcm,cygnus-osc-derived" only.
+
+- div: Used by "brcm,cygnus-pll-derived" to define the hard coded internal
+  divider value. Used by "brcm,cygnus-osc-derived" to specify the programmable
+  divider.
+
+- #clock-cells: From common clock binding; shall be set to 0.
+
+Examples:
+
+		osc: oscillator {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <25000000>;
+		};
+
+		lcpll: lcpll@0301d02c {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-lcpll-clk";
+			reg = <0x0301d02c 0x1c>;
+			clocks = <&osc>;
+		};
+
+		genpll: genpll@0301d000 {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-genpll-clk";
+			reg = <0x0301d000 0x2c>,
+				  <0x180AA024 0x4>,
+				  <0x0301C020 0x4>;
+			clocks = <&osc>;
+		};
+
+		axi21_clk: genpll_ch0@0301d000 {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-genpll-ch";
+			reg = <0x0301d000 0x2c>;
+			clocks = <&genpll>;
+			channel = <0>;
+		};
+
+		pcie_clk: lcpll_ch0@0301d02c {
+			compatible = "brcm,cygnus-lcpll-ch";
+			reg = <0x0301d02c 0x1c>;
+			#clock-cells = <0>;
+			clocks = <&lcpll>;
+			channel = <0>;
+		};
+
+		axi41_clk: axi41_clk {
+			reg = <0x0301d000 0x2c>;
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-pll-derived";
+			clocks = <&axi21_clk>;
+			div = <2>;
+		};
+
+		keypad_clk: keypad_clk@0301D048 {
+			compatible = "brcm,cygnus-osc-derived";
+			reg = <0x0301D048 0x4>,
+				  <0x180AA024 0x4>;
+			#clock-cells = <0>;
+			clocks = <&osc>;
+			channel = <0>;
+			div = <392>;
+		};
+
+		mipipll: mipipll@180a9800 {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-mipipll-clk";
+			reg = <0x180a9800 0x2c>,
+				  top_clk_gating_ctrl: <0x180AA024 0x4>,
+				  crmu_pll_aon_ctrl: <0x0301C020 0x4>;
+			clocks = <&osc>;
+		};
+
+		lcd_clk: mipipll_ch1@180a9800 {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-mipipll-ch";
+			reg = <0x180a9800 0x2c>,
+				  <0x180AA024 0x4>;
+			clocks = <&mipipll>;
+			channel = <1>;
+		};
diff --git a/Documentation/devicetree/bindings/clock/clk-iproc.txt b/Documentation/devicetree/bindings/clock/clk-iproc.txt
new file mode 100644
index 0000000..b5d4f08
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clk-iproc.txt
@@ -0,0 +1,48 @@
+Broadcom iProc Clock Controller
+
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The iProc clock controller manages clocks that are common to iProc chips.
+The controllers are split into a parent-child relationship where the parent is
+the PLL and the child controls the PLL's channels.
+
+The only PLL controlled is the ARM PLL which is derived from a 25MHz crystal.
+
+Required properties:
+- compatible: Must be one of the following:
+    "brcm,iproc-arm-a9pll" - Controls ARM PLL.
+    "brcm,iproc-arm-ch" -  Controls ARM PLL (parent) channels
+
+- reg: The base address of the PLL.
+
+- clocks: The input parent clock phandle for the clock. This is either a PLL,
+  or oscillator.
+
+- channel: The PLL channel that the clock belongs to. This is used for
+  "brcm,iproc-arm-ch" only.
+
+- #clock-cells: From common clock binding; shall be set to 0.
+
+Example:
+
+	osc: oscillator {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <25000000>;
+	};
+
+	a9pll: arm_clk@19000000 {
+		compatible = "brcm,iproc-arm-a9pll";
+		reg = <0x19000000 0x1000>;
+		#clock-cells = <0>;
+		clocks = <&osc>;
+	};
+
+	periph_clk: periph_clk@19000000 {
+		compatible = "brcm,iproc-arm-ch";
+		reg = <0x19000000 0x1000>;
+		#clock-cells = <0>;
+		clocks = <&a9pll>;
+		channel = <3>;
+	};
-- 
1.7.9.5

[PATCH 4/6] ARM: cygnus defconfig : Initial defconfig for Broadcom Cygnus SoC

[Scott Branden]

From: Jonathan Richardson <jonathar@broadcom.com>

Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/configs/bcm_cygnus_defconfig |  222 +++++++++++++++++++++++++++++++++
 1 file changed, 222 insertions(+)
 create mode 100644 arch/arm/configs/bcm_cygnus_defconfig

diff --git a/arch/arm/configs/bcm_cygnus_defconfig b/arch/arm/configs/bcm_cygnus_defconfig
new file mode 100644
index 0000000..d148f2d
--- /dev/null
+++ b/arch/arm/configs/bcm_cygnus_defconfig
@@ -0,0 +1,222 @@
+CONFIG_KERNEL_XZ=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=19
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_BLK_CGROUP=y
+CONFIG_NAMESPACES=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BCM_IPROC=y
+CONFIG_ARCH_BCM_CYGNUS=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+# CONFIG_COMPACTION is not set
+# CONFIG_ATAGS is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_TCP_CONG_ADVANCED=y
+# CONFIG_TCP_CONG_BIC is not set
+# CONFIG_TCP_CONG_WESTWOOD is not set
+# CONFIG_TCP_CONG_HTCP is not set
+CONFIG_IPV6=y
+# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET6_XFRM_MODE_BEET is not set
+# CONFIG_IPV6_SIT is not set
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+CONFIG_NETFILTER=y
+# CONFIG_BRIDGE_NETFILTER is not set
+CONFIG_NF_CONNTRACK=y
+# CONFIG_NF_CONNTRACK_PROCFS is not set
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_RAW=y
+CONFIG_NF_CONNTRACK_IPV6=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_MATCH_AH=y
+CONFIG_IP6_NF_MATCH_EUI64=y
+CONFIG_IP6_NF_MATCH_FRAG=y
+CONFIG_IP6_NF_MATCH_OPTS=y
+CONFIG_IP6_NF_MATCH_IPV6HEADER=y
+CONFIG_IP6_NF_MATCH_MH=y
+CONFIG_IP6_NF_MATCH_RT=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_IP6_NF_RAW=y
+CONFIG_BRIDGE=y
+# CONFIG_BRIDGE_IGMP_SNOOPING is not set
+CONFIG_VLAN_8021Q=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_FQ_CODEL=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+# CONFIG_BLK_DEV is not set
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_PHYLIB=y
+CONFIG_BROADCOM_PHY=y
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
+CONFIG_I2C_SMBUS=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_DEBUG=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_SOC=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_PWM=y
+CONFIG_EXT4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_UBIFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_REDUCED=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_OBJECTS=y
+CONFIG_DEBUG_OBJECTS_RCU_HEAD=y
+CONFIG_SLUB_DEBUG_ON=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=110
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_SCHEDSTATS=y
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_PROVE_LOCKING=y
+CONFIG_DEBUG_ATOMIC_SLEEP=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_SG=y
+CONFIG_DEBUG_NOTIFIERS=y
+CONFIG_DEBUG_CREDENTIALS=y
+CONFIG_PROVE_RCU=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_UART_8250=y
+CONFIG_DEBUG_UART_PHYS=0x18023000
+CONFIG_DEBUG_UART_VIRT=0xf1023000
+CONFIG_EARLY_PRINTK=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
-- 
1.7.9.5

[PATCH 5/6] ARM: dts: Enable Broadcom Cygnus SoC

[Scott Branden]

From: Jonathan Richardson <jonathar@broadcom.com>

DT files to enable cygnus consisting of the enterprise phone board variant and
cygnus core configuration.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Arun Parameswaran <aparames@broadcom.com>
Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/boot/dts/Makefile             |    1 +
 arch/arm/boot/dts/bcm-cygnus.dtsi      |  349 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/bcm911360_entphn.dts |   22 ++
 3 files changed, 372 insertions(+)
 create mode 100644 arch/arm/boot/dts/bcm-cygnus.dtsi
 create mode 100644 arch/arm/boot/dts/bcm911360_entphn.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b8c5cd3..b95d41d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -52,6 +52,7 @@ dtb-$(CONFIG_ARCH_AT91)	+= sama5d36ek.dtb
 dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
 dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
+dtb-$(CONFIG_ARCH_BCM_CYGNUS) += bcm911360_entphn.dtb
 dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
 dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
 	bcm21664-garnet.dtb
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
new file mode 100644
index 0000000..81da0d8
--- /dev/null
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -0,0 +1,349 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "brcm,cygnus";
+	model = "Broadcom Cygnus SoC";
+	interrupt-parent = <&gic>;
+
+	aliases {
+		serial0 = &uart3;
+		serial1 = &uart0;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200 earlyprintk debug";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <0x0>;
+		};
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		osc: oscillator {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <25000000>;
+		};
+
+		lcpll: lcpll@0301d02c {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-lcpll-clk";
+			reg = <0x0301d02c 0x1c>;
+			clocks = <&osc>;
+		};
+
+		genpll: genpll@0301d000 {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-genpll-clk";
+			reg = <0x0301d000 0x2c>,
+				  <0x180AA024 0x4>,
+				  <0x0301C020 0x4>;
+			clocks = <&osc>;
+		};
+
+		axi21_clk: genpll_ch0@0301d000 {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-genpll-ch";
+			reg = <0x0301d000 0x2c>;
+			clocks = <&genpll>;
+			channel = <0>;
+		};
+
+		clk_25MHz: genpll_ch1@0301d000 {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-genpll-ch";
+			reg = <0x0301d000 0x2c>;
+			clocks = <&genpll>;
+			channel = <1>;
+		};
+
+		sys_clk: genpll_ch2@0301d000 {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-genpll-ch";
+			reg = <0x0301d000 0x2c>;
+			clocks = <&genpll>;
+			channel = <2>;
+		};
+
+		ethernet_clk: genpll_ch3@0301d000 {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-genpll-ch";
+			reg = <0x0301d000 0x2c>;
+			clocks = <&genpll>;
+			channel = <3>;
+		};
+
+		asiu_audio_clk: genpll_ch4@0301d000 {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-genpll-ch";
+			reg = <0x0301d000 0x2c>;
+			clocks = <&genpll>;
+			channel = <4>;
+		};
+
+		asiu_can_clk: genpll_ch5@0301d000 {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-genpll-ch";
+			reg = <0x0301d000 0x2c>;
+			clocks = <&genpll>;
+			channel = <5>;
+		};
+
+		pcie_clk: lcpll_ch0@0301d02c {
+			compatible = "brcm,cygnus-lcpll-ch";
+			reg = <0x0301d02c 0x1c>;
+			#clock-cells = <0>;
+			clocks = <&lcpll>;
+			channel = <0>;
+		};
+
+		ddr_clk: lcpll_ch1@0301d02c {
+			compatible = "brcm,cygnus-lcpll-ch";
+			reg = <0x0301d02c 0x1c>;
+			#clock-cells = <0>;
+			clocks = <&lcpll>;
+			channel = <1>;
+		};
+
+		sdio_clk: lcpll_ch2@0301d02c {
+			compatible = "brcm,cygnus-lcpll-ch";
+			reg = <0x0301d02c 0x1c>;
+			#clock-cells = <0>;
+			clocks = <&lcpll>;
+			channel = <2>;
+		};
+
+		usb_clk: lcpll_ch3@0301d02c {
+		    compatible = "brcm,cygnus-lcpll-ch";
+			reg = <0x0301d02c 0x1c>;
+			#clock-cells = <0>;
+			clocks = <&lcpll>;
+			channel = <3>;
+		};
+
+		smart_card_clk: lcpll_ch4@0301d02c {
+			compatible = "brcm,cygnus-lcpll-ch";
+			reg = <0x0301d02c 0x1c>;
+			#clock-cells = <0>;
+			clocks = <&lcpll>;
+			channel = <4>;
+		};
+
+		ch5_unknown_clk: lcpll_ch5@0301d02c {
+			compatible = "brcm,cygnus-lcpll-ch";
+			reg = <0x0301d02c 0x1c>;
+			#clock-cells = <0>;
+			clocks = <&lcpll>;
+			channel = <5>;
+		};
+
+		/*
+		 * There are 2 clocks derived from genpll ch0 (axi21) which are
+		 * divided internally by 2 and 4. If axi21 clock rate changes, these
+		 * derived clock rates scale accordingly.
+		 */
+
+		axi41_clk: axi41_clk {
+			reg = <0x0301d000 0x2c>;
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-pll-derived";
+			clocks = <&axi21_clk>;
+			div = <2>;
+		};
+
+		axi81_clk: axi81_clk {
+			reg = <0x0301d000 0x2c>;
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-pll-derived";
+			clocks = <&axi21_clk>;
+			div = <4>;
+		};
+
+		/*
+		 * The main output of the ARM PLL is arm_clk with several derived
+		 * child clocks:
+		 * 		periph_clk
+		 * 		apb_clk
+		 * 		arm_switch
+		 * 		apb0_free
+		 */
+		a9pll: arm_clk@19000000 {
+			compatible = "brcm,iproc-arm-a9pll";
+			reg = <0x19000000 0x1000>;
+			#clock-cells = <0>;
+			clocks = <&osc>;
+		};
+
+		periph_clk: periph_clk@19000000 {
+			compatible = "brcm,iproc-arm-ch";
+			reg = <0x19000000 0x1000>;
+			#clock-cells = <0>;
+			clocks = <&a9pll>;
+			channel = <3>;
+		};
+
+		apb0_free: apb0_free@19000000 {
+			compatible = "brcm,iproc-arm-ch";
+			reg = <0x19000000 0x1000>;
+			#clock-cells = <0>;
+			clocks = <&a9pll>;
+			channel = <0>;
+		};
+
+		arm_switch: arm_switch@19000000 {
+			compatible = "brcm,iproc-arm-ch";
+			reg = <0x19000000 0x1000>;
+			#clock-cells = <0>;
+			clocks = <&a9pll>;
+			channel = <1>;
+		};
+
+		apb_clk: apb_clk@19000000 {
+			compatible = "brcm,iproc-arm-ch";
+			reg = <0x19000000 0x1000>;
+			#clock-cells = <0>;
+			clocks = <&a9pll>;
+			channel = <2>;
+		};
+
+		/*
+		 * Clocks derived from oscillator.
+		 */
+		keypad_clk: keypad_clk@0301D048 {
+			compatible = "brcm,cygnus-osc-derived";
+			reg = <0x0301D048 0x4>,
+				  <0x180AA024 0x4>;
+			#clock-cells = <0>;
+			clocks = <&osc>;
+			channel = <0>;
+			div = <392>;
+		};
+
+		adc_clk: adc_clk@0301D04C {
+			compatible = "brcm,cygnus-osc-derived";
+			reg = <0x0301D04C 0x4>,
+				  <0x180AA024 0x4>;
+			#clock-cells = <0>;
+			clocks = <&osc>;
+			channel = <1>;
+		};
+
+		pwm_clk: pwm_clk@0301D050 {
+			compatible = "brcm,cygnus-osc-derived";
+			reg = <0x0301D050 0x4>,
+				  <0x180AA024 0x4>;
+			#clock-cells = <0>;
+			clocks = <&osc>;
+			channel = <2>;
+		};
+
+		mipipll: mipipll@180a9800 {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-mipipll-clk";
+			reg = <0x180a9800 0x2c>,
+				  top_clk_gating_ctrl: <0x180AA024 0x4>,
+				  crmu_pll_aon_ctrl: <0x0301C020 0x4>;
+			clocks = <&osc>;
+		};
+
+		lcd_clk: mipipll_ch1@180a9800 {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-mipipll-ch";
+			reg = <0x180a9800 0x2c>,
+				  <0x180AA024 0x4>;
+			clocks = <&mipipll>;
+			channel = <1>;
+		};
+	};
+
+	amba {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "arm,amba-bus", "simple-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		wdt@18009000 {
+			 compatible = "arm,sp805" , "arm,primecell";
+			 reg = <0x18009000 0x1000>;
+			 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+			 clocks = <&axi81_clk>;
+			 clock-names = "apb_pclk";
+		};
+	};
+
+	uart3: serial@18023000 {
+		compatible = "snps,dw-apb-uart";
+		reg = <0x18023000 0x100>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <100000000>;
+		clocks = <&axi81_clk>;
+		status = "okay";
+	};
+
+	uart0: serial@18020000 {
+		compatible = "snps,dw-apb-uart";
+		reg = <0x18020000 0x100>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&axi81_clk>;
+		clock-frequency = <100000000>;
+		status = "okay";
+	};
+
+	gic: interrupt-controller@19021000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+		interrupt-controller;
+		reg = <0x19021000 0x1000>,
+		      <0x19020100 0x100>;
+	};
+
+	L2: l2-cache {
+		compatible = "arm,pl310-cache";
+		reg = <0x19022000 0x1000>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	timer@19020200 {
+		compatible = "arm,cortex-a9-global-timer";
+		reg = <0x19020200 0x100>;
+		interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&periph_clk>;
+	};
+
+};
diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts
new file mode 100644
index 0000000..cee4aff
--- /dev/null
+++ b/arch/arm/boot/dts/bcm911360_entphn.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "bcm-cygnus.dtsi"
+
+/ {
+	model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)";
+	compatible = "brcm,bcm911360_entphn", "brcm,cygnus";
+};
-- 
1.7.9.5

[PATCH 6/6] MAINTAINERS: Entry for Cygnus/iproc arm architecture and clock drivers

[Scott Branden]

From: Jonathan Richardson <jonathar@broadcom.com>

Acked-by: Jonathan Richardson <jonathar@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 MAINTAINERS |   15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index a12edf2..9024bac 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2071,6 +2071,21 @@ L:	linux-scsi@vger.kernel.org
 S:	Supported
 F:	drivers/scsi/bnx2i/
 
+BROADCOM CYGNUS/IPROC ARM ARCHITECTURE
+M:	Jonathan Richardson <jonathar@broadcom.com>
+M:	Scott Branden <sbranden@broadcom.com>
+L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S:	Maintained
+F:	Documentation/devicetree/bindings/arm/cygnus.txt
+F:	arch/arm/boot/dts/bcm-cygnus.dtsi
+F:	arch/arm/boot/dts/bcm911360_entphn.dts
+F:	arch/arm/configs/bcm_cygnus_defconfig
+F:	arch/arm/mach-bcm/board_bcm_cygnus.c
+F:	Documentation/devicetree/bindings/clock/clk-cygnus.txt
+F:	Documentation/devicetree/bindings/clock/clk-iproc.txt
+F:	drivers/clk/bcm/clk-cygnus.c
+F:	drivers/clk/bcm/clk-iproc.c
+
 BROADCOM KONA GPIO DRIVER
 M:	Ray Jui <rjui@broadcom.com>
 L:	bcm-kernel-feedback-list@broadcom.com
-- 
1.7.9.5

Re: [PATCH 1/6] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Arnd Bergmann]

On Tuesday 07 October 2014 22:27:00 Scott Branden wrote:
> From: Jonathan Richardson <jonathar@broadcom.com>
> 
> Adds initial support for the Cygnus SoC based on Broadcom’s iProc series.
> 
> Reviewed-by: Ray Jui <rjui@broadcom.com>
> Reviewed-by: Desmond Liu <desmondl@broadcom.com>
> Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
> Tested-by: Jonathan Richardson <jonathar@broadcom.com>
> Signed-off-by: Scott Branden <sbranden@broadcom.com>
> ---
>  arch/arm/mach-bcm/Kconfig      |   31 ++++++++
>  arch/arm/mach-bcm/Makefile     |    3 +
>  arch/arm/mach-bcm/bcm_cygnus.c |  166 ++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 200 insertions(+)
>  create mode 100644 arch/arm/mach-bcm/bcm_cygnus.c
> 
> diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
> index fc93800..2dd3f78 100644
> --- a/arch/arm/mach-bcm/Kconfig
> +++ b/arch/arm/mach-bcm/Kconfig
> @@ -5,6 +5,37 @@ menuconfig ARCH_BCM
>  
>  if ARCH_BCM
>  
> +config ARCH_BCM_IPROC
> +	bool "Broadcom ARMv7 iProc boards" if ARCH_MULTI_V7
> +	select ARM_GIC
> +	select CACHE_L2X0
> +	select HAVE_ARM_TWD if LOCAL_TIMERS
> +	select HAVE_CLK
> +	select CLKSRC_OF
> +	select CLKSRC_MMIO
> +	select GENERIC_CLOCKEVENTS
> +	select ARM_GLOBAL_TIMER
> +	select ARCH_REQUIRE_GPIOLIB
> +	select ARM_AMBA
> +	select PINCTRL
> +	select DEBUG_UART_8250

A lot of these are implied by ARCH_MULTI_V7, just drop them here.

Some others like DEBUG_UART_8250 should remain user-selectable, if
the platform works without them.

> +	help
> +	  This enables support for systems based on Broadcom IPROC architected SoCs.
> +	  The IPROC complex contains one or more ARM CPUs along with common
> +	  core periperals. Application specific SoCs are created by adding a
> +	  uArchitecture containing peripherals outside of the IPROC complex.
> +	  Currently supported SoCs are Cygnus.
> +
> +menu "iProc SoC based Machine types"
> +	depends on ARCH_BCM_IPROC
> +
> +	config ARCH_BCM_CYGNUS
> +		bool "Support Broadcom Cygnus board"
> +		select USB_ARCH_HAS_EHCI if USB_SUPPORT
> +		help
> +		  Support for Broadcom Cygnus SoC.
> +endmenu

I don't think you need per-board config options. The main option
above should be enough.

> +
> +#define CRMU_MAIL_BOX1      0x03024028
> +#define CRMU_SOFT_RESET_CMD 0xFFFFFFFF

Never hardcode physical register locations in source. This should come
from DT, and get moved into a regular 'reset' device driver.

You probably want to use drivers/power/reset/syscon-reboot.c

> +/* CRU_RESET register */
> +static void * __iomem crmu_mail_box1_reg;
> +
> +#ifdef CONFIG_NEON
> +
> +#define CRU_BASE                  0x1800e000
> +#define CRU_SIZE                  0x34
> +#define CRU_CONTROL_OFFSET        0x0
> +#define CRU_PWRDWN_EN_OFFSET      0x4
> +#define CRU_PWRDWN_STATUS_OFFSET  0x8
> +#define CRU_NEON0_HW_RESET  6
> +#define CRU_CLAMP_ON_NEON0  20
> +#define CRU_PWRONIN_NEON0   21
> +#define CRU_PWRONOUT_NEON0  21
> +#define CRU_PWROKIN_NEON0   22
> +#define CRU_PWROKOUT_NEON0  22
> +#define CRU_STATUS_DELAY_NS 500
> +#define CRU_MAX_RETRY_COUNT 10
> +#define CRU_RETRY_INTVL_US  1
> +
> +/* Power up the NEON/VFPv3 block. */
> +static void bcm_cygnus_powerup_neon(void)
> +{
> +	void * __iomem cru_base = ioremap(CRU_BASE, CRU_SIZE);
> +	u32 reg, i;

Same thing here: this should really use the device node for CRU.

Can you describe what the CRU is? Is this specific to NEON or is
it some general-purpose power management unit?

> +static void __init bcm_cygnus_init(void)
> +{
> +	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
> +
> +	l2x0_of_init(0, ~0UL);

The l2x0_of_init can be removed now, just move the arguments into the
respective fields of the machine descriptor.

> +	crmu_mail_box1_reg = ioremap(CRMU_MAIL_BOX1, SZ_4);
> +	WARN_ON(!crmu_mail_box1_reg);
> +
> +#ifdef CONFIG_NEON
> +	bcm_cygnus_powerup_neon();
> +#endif
> +}

In general, try to avoid #ifdef, use

	if (IS_ENABLED(CONFIG_NEON))
		bcm_cygnus_powerup_neon();

instead.

> +
> +static const char const *bcm_cygnus_dt_compat[] = {
> +	"brcm,cygnus",
> +	NULL,
> +};
> +
> +DT_MACHINE_START(BCM_CYGNUS_DT, "Broadcom Cygnus SoC")
> +	.init_machine = bcm_cygnus_init,
> +	.map_io = debug_ll_io_init,
> +	.dt_compat = bcm_cygnus_dt_compat,
> +	.restart   = bcm_cygnus_restart
> +MACHINE_END

The map_io pointer is unnecessary, and the restart pointer should get
set by the reset driver. I hope we can find a way to avoid the 
bcm_cygnus_init callback as well.

	Arnd

Re: [PATCH 3/6] dt-bindings: Document Broadcom Cygnus SoC and clock driver

[Arnd Bergmann]

On Tuesday 07 October 2014 22:27:02 Scott Branden wrote:
> diff --git a/Documentation/devicetree/bindings/arm/cygnus.txt b/Documentation/devicetree/bindings/arm/cygnus.txt
> new file mode 100644
> index 0000000..a210377
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/cygnus.txt
> @@ -0,0 +1,12 @@
> +Broadcom Cygnus device tree bindings
> +------------------------------------
> +
> +All Cygnus boards shall have the following properties:
> +
> +Required root node property:
> +       - compatible = "brcm,cygnus";

Can you add a more specific model number for the soc as well?
I assume that cygnus refers to more than one model, so you
should probably list both the family and the individual
SoC type here.

> +Boards variants shall have the following additional properties:
> +
> +Required root node property for the BCM911360_ENTPHN board:
> +       - compatible = "brcm,bcm911360_entphn";
> 

We normally don't list specific boards here, since it's hard to
keep up.

	Arnd

Re: [PATCH 4/6] ARM: cygnus defconfig : Initial defconfig for Broadcom Cygnus SoC

[Arnd Bergmann]

On Tuesday 07 October 2014 22:27:03 Scott Branden wrote:
> From: Jonathan Richardson <jonathar@broadcom.com>
> 
> Tested-by: Jonathan Richardson <jonathar@broadcom.com>
> Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
> Signed-off-by: Scott Branden <sbranden@broadcom.com>

Do you actually need a separate defconfig?

If possible, just add your drivers to multi_v7_defconfig, otherwise
include a justification in the patch changelog why your platform
should have its own defconfig file.

	Arnd

Re: [PATCH 1/6] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Russell King - ARM Linux]

On Tue, Oct 07, 2014 at 10:27:00PM -0700, Scott Branden wrote:
> +static void __init bcm_cygnus_init(void)
> +{
> +	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
> +
> +	l2x0_of_init(0, ~0UL);

Please don't explicitly call l2x0 initialisation.  Instead, set the
appropriate l2c members here:

> +DT_MACHINE_START(BCM_CYGNUS_DT, "Broadcom Cygnus SoC")
> +	.init_machine = bcm_cygnus_init,
> +	.map_io = debug_ll_io_init,
> +	.dt_compat = bcm_cygnus_dt_compat,
> +	.restart   = bcm_cygnus_restart
> +MACHINE_END

and let the core code call it at the appropriate time.  Thanks.

-- 
FTTC broadband for 0.8mile line: currently at 9.5Mbps down 400kbps up
according to speedtest.net.

Re: [PATCH 3/6] dt-bindings: Document Broadcom Cygnus SoC and clock driver

[Scott Branden]

On 14-10-08 12:57 AM, Arnd Bergmann wrote:
> On Tuesday 07 October 2014 22:27:02 Scott Branden wrote:
>> diff --git a/Documentation/devicetree/bindings/arm/cygnus.txt b/Documentation/devicetree/bindings/arm/cygnus.txt
>> new file mode 100644
>> index 0000000..a210377
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/cygnus.txt
>> @@ -0,0 +1,12 @@
>> +Broadcom Cygnus device tree bindings
>> +------------------------------------
>> +
>> +All Cygnus boards shall have the following properties:
>> +
>> +Required root node property:
>> +       - compatible = "brcm,cygnus";
>
> Can you add a more specific model number for the soc as well?
> I assume that cygnus refers to more than one model, so you
> should probably list both the family and the individual
> SoC type here.
Add specific model numbers does not seem necessary because they are not 
needed to be specified in the device tree for compatible purposes for 
the kernel to work.  Plus, the list of model numbers will continue to 
grow over time and compatible strings would need to be added to the 
kernel for no apparent reason?
>
>> +Boards variants shall have the following additional properties:
>> +
>> +Required root node property for the BCM911360_ENTPHN board:
>> +       - compatible = "brcm,bcm911360_entphn";
>>
>
> We normally don't list specific boards here, since it's hard to
> keep up.
Thanks - removed specific boards from file and moved the cygnus.txt file 
to devicetree/bindings/arm/bcm/cygnus.txt in next version.  This seems 
to be like the appropriate place to put this document. We will need to 
add back in board specific bindings when ALSA support is added.  But 
that will be a later commit to deal with.
>
> 	Arnd
>

Re: [PATCH 4/6] ARM: cygnus defconfig : Initial defconfig for Broadcom Cygnus SoC

[Scott Branden]

On 14-10-08 12:58 AM, Arnd Bergmann wrote:
> On Tuesday 07 October 2014 22:27:03 Scott Branden wrote:
>> From: Jonathan Richardson <jonathar@broadcom.com>
>>
>> Tested-by: Jonathan Richardson <jonathar@broadcom.com>
>> Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>
> Do you actually need a separate defconfig?
>
> If possible, just add your drivers to multi_v7_defconfig, otherwise
> include a justification in the patch changelog why your platform
> should have its own defconfig file.
We need a separate defconfig so that customers and developers have some 
chance of understanding what kernel drivers apply to their SoC.  That 
way they can optimize kernel size if desired.  Will update patch 
changelog in next version.
>
> 	Arnd
>

Re: [PATCH 1/6] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Scott Branden]

On 14-10-08 01:11 AM, Russell King - ARM Linux wrote:
> On Tue, Oct 07, 2014 at 10:27:00PM -0700, Scott Branden wrote:
>> +static void __init bcm_cygnus_init(void)
>> +{
>> +	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
>> +
>> +	l2x0_of_init(0, ~0UL);
>
> Please don't explicitly call l2x0 initialisation.  Instead, set the
> appropriate l2c members here:
>
>> +DT_MACHINE_START(BCM_CYGNUS_DT, "Broadcom Cygnus SoC")
>> +	.init_machine = bcm_cygnus_init,
>> +	.map_io = debug_ll_io_init,
>> +	.dt_compat = bcm_cygnus_dt_compat,
>> +	.restart   = bcm_cygnus_restart
>> +MACHINE_END
>
> and let the core code call it at the appropriate time.  Thanks.
>
Thanks - was unaware of this functionality.  Will add .l2c_aux_val and 
.l2c_aux mask to DT_MATCHINE_START.  BUT, what happens when we need to 
add trustzone support and make SMC call to secure monitor?

Re: [PATCH 1/6] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Russell King - ARM Linux]

On Wed, Oct 08, 2014 at 04:17:29AM -0700, Scott Branden wrote:
> Thanks - was unaware of this functionality.  Will add .l2c_aux_val and  
> .l2c_aux mask to DT_MATCHINE_START.  BUT, what happens when we need to  
> add trustzone support and make SMC call to secure monitor?

You will then need to implement the .l2c_write_sec initialiser in the
same place.

Note that there's work to revise the trustzone support in this area
which will probably be merged for 3.19.

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according to speedtest.net.

Re: [PATCH 1/6] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Scott Branden]

Thanks for the review - comments inline.

On 14-10-08 12:54 AM, Arnd Bergmann wrote:
> On Tuesday 07 October 2014 22:27:00 Scott Branden wrote:
>> From: Jonathan Richardson <jonathar@broadcom.com>
>>
>> Adds initial support for the Cygnus SoC based on Broadcom’s iProc series.
>>
>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>> Reviewed-by: Desmond Liu <desmondl@broadcom.com>
>> Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
>> Tested-by: Jonathan Richardson <jonathar@broadcom.com>
>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>> ---
>>   arch/arm/mach-bcm/Kconfig      |   31 ++++++++
>>   arch/arm/mach-bcm/Makefile     |    3 +
>>   arch/arm/mach-bcm/bcm_cygnus.c |  166 ++++++++++++++++++++++++++++++++++++++++
>>   3 files changed, 200 insertions(+)
>>   create mode 100644 arch/arm/mach-bcm/bcm_cygnus.c
>>
>> diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
>> index fc93800..2dd3f78 100644
>> --- a/arch/arm/mach-bcm/Kconfig
>> +++ b/arch/arm/mach-bcm/Kconfig
>> @@ -5,6 +5,37 @@ menuconfig ARCH_BCM
>>
>>   if ARCH_BCM
>>
>> +config ARCH_BCM_IPROC
>> +	bool "Broadcom ARMv7 iProc boards" if ARCH_MULTI_V7
>> +	select ARM_GIC
>> +	select CACHE_L2X0
>> +	select HAVE_ARM_TWD if LOCAL_TIMERS
>> +	select HAVE_CLK
>> +	select CLKSRC_OF
>> +	select CLKSRC_MMIO
>> +	select GENERIC_CLOCKEVENTS
>> +	select ARM_GLOBAL_TIMER
>> +	select ARCH_REQUIRE_GPIOLIB
>> +	select ARM_AMBA
>> +	select PINCTRL
>> +	select DEBUG_UART_8250
>
> A lot of these are implied by ARCH_MULTI_V7, just drop them here.
>
> Some others like DEBUG_UART_8250 should remain user-selectable, if
> the platform works without them.
>
Will review.  It looks like DEBUG_UART_8250 actually has to move to 
Kconfig.debug as that is where everyone else selects it.
>> +	help
>> +	  This enables support for systems based on Broadcom IPROC architected SoCs.
>> +	  The IPROC complex contains one or more ARM CPUs along with common
>> +	  core periperals. Application specific SoCs are created by adding a
>> +	  uArchitecture containing peripherals outside of the IPROC complex.
>> +	  Currently supported SoCs are Cygnus.
>> +
>> +menu "iProc SoC based Machine types"
>> +	depends on ARCH_BCM_IPROC
>> +
>> +	config ARCH_BCM_CYGNUS
>> +		bool "Support Broadcom Cygnus board"
>> +		select USB_ARCH_HAS_EHCI if USB_SUPPORT
>> +		help
>> +		  Support for Broadcom Cygnus SoC.
>> +endmenu
>
> I don't think you need per-board config options. The main option
> above should be enough.
This is not a per-board config option.  This is actually a per-SoC 
uArchtecture selection.  More major uArchectures will be added to the 
IPROC.  Will Change comment to "Support Broadcom Cygnus SoC"
>
>> +
>> +#define CRMU_MAIL_BOX1      0x03024028
>> +#define CRMU_SOFT_RESET_CMD 0xFFFFFFFF
>
> Never hardcode physical register locations in source. This should come
> from DT, and get moved into a regular 'reset' device driver.
>
> You probably want to use drivers/power/reset/syscon-reboot.c
>
OK, thanks for advice on where to put reset device driver.  Will 
investigate.
>> +/* CRU_RESET register */
>> +static void * __iomem crmu_mail_box1_reg;
>> +
>> +#ifdef CONFIG_NEON
>> +
>> +#define CRU_BASE                  0x1800e000
>> +#define CRU_SIZE                  0x34
>> +#define CRU_CONTROL_OFFSET        0x0
>> +#define CRU_PWRDWN_EN_OFFSET      0x4
>> +#define CRU_PWRDWN_STATUS_OFFSET  0x8
>> +#define CRU_NEON0_HW_RESET  6
>> +#define CRU_CLAMP_ON_NEON0  20
>> +#define CRU_PWRONIN_NEON0   21
>> +#define CRU_PWRONOUT_NEON0  21
>> +#define CRU_PWROKIN_NEON0   22
>> +#define CRU_PWROKOUT_NEON0  22
>> +#define CRU_STATUS_DELAY_NS 500
>> +#define CRU_MAX_RETRY_COUNT 10
>> +#define CRU_RETRY_INTVL_US  1
>> +
>> +/* Power up the NEON/VFPv3 block. */
>> +static void bcm_cygnus_powerup_neon(void)
>> +{
>> +	void * __iomem cru_base = ioremap(CRU_BASE, CRU_SIZE);
>> +	u32 reg, i;
>
> Same thing here: this should really use the device node for CRU.
>
> Can you describe what the CRU is? Is this specific to NEON or is
> it some general-purpose power management unit?
>
It's a central resource unit with a lot of random registers to perform 
various operations.  To reduce confusion I'll probably move this out of 
the kernel init and into the bootloader.  This will simplify the kernel 
init.
>> +static void __init bcm_cygnus_init(void)
>> +{
>> +	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
>> +
>> +	l2x0_of_init(0, ~0UL);
>
> The l2x0_of_init can be removed now, just move the arguments into the
> respective fields of the machine descriptor.
>
Yes, thanks for pointing this out.
>> +	crmu_mail_box1_reg = ioremap(CRMU_MAIL_BOX1, SZ_4);
>> +	WARN_ON(!crmu_mail_box1_reg);
>> +
>> +#ifdef CONFIG_NEON
>> +	bcm_cygnus_powerup_neon();
>> +#endif
>> +}
>
> In general, try to avoid #ifdef, use
>
> 	if (IS_ENABLED(CONFIG_NEON))
> 		bcm_cygnus_powerup_neon();
>
> instead.
>
>> +
>> +static const char const *bcm_cygnus_dt_compat[] = {
>> +	"brcm,cygnus",
>> +	NULL,
>> +};
>> +
>> +DT_MACHINE_START(BCM_CYGNUS_DT, "Broadcom Cygnus SoC")
>> +	.init_machine = bcm_cygnus_init,
>> +	.map_io = debug_ll_io_init,
>> +	.dt_compat = bcm_cygnus_dt_compat,
>> +	.restart   = bcm_cygnus_restart
>> +MACHINE_END
>
> The map_io pointer is unnecessary, and the restart pointer should get
> set by the reset driver. I hope we can find a way to avoid the
> bcm_cygnus_init callback as well.
bcm_cygnus_init callback can be removed by moving initialization to 
bootloader.
>
> 	Arnd
>

Re: [PATCH 1/6] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Rob Herring]

On Wed, Oct 8, 2014 at 12:27 AM, Scott Branden <sbranden@broadcom.com> wrote:
> From: Jonathan Richardson <jonathar@broadcom.com>
>
> Adds initial support for the Cygnus SoC based on Broadcom’s iProc series.
>
> Reviewed-by: Ray Jui <rjui@broadcom.com>
> Reviewed-by: Desmond Liu <desmondl@broadcom.com>
> Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
> Tested-by: Jonathan Richardson <jonathar@broadcom.com>
> Signed-off-by: Scott Branden <sbranden@broadcom.com>
> ---
>  arch/arm/mach-bcm/Kconfig      |   31 ++++++++
>  arch/arm/mach-bcm/Makefile     |    3 +
>  arch/arm/mach-bcm/bcm_cygnus.c |  166 ++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 200 insertions(+)
>  create mode 100644 arch/arm/mach-bcm/bcm_cygnus.c
>
> diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
> index fc93800..2dd3f78 100644
> --- a/arch/arm/mach-bcm/Kconfig
> +++ b/arch/arm/mach-bcm/Kconfig
> @@ -5,6 +5,37 @@ menuconfig ARCH_BCM
>
>  if ARCH_BCM
>
> +config ARCH_BCM_IPROC
> +       bool "Broadcom ARMv7 iProc boards" if ARCH_MULTI_V7
> +       select ARM_GIC
> +       select CACHE_L2X0
> +       select HAVE_ARM_TWD if LOCAL_TIMERS

LOCAL_TIMERS does not exist anymore.

> +       select HAVE_CLK

Selected already by multi-platform.

> +       select CLKSRC_OF
> +       select CLKSRC_MMIO

These should be selected by the timers that need these rather than the platform.

> +       select GENERIC_CLOCKEVENTS

Selected already by multi-platform.

> +       select ARM_GLOBAL_TIMER
> +       select ARCH_REQUIRE_GPIOLIB
> +       select ARM_AMBA
> +       select PINCTRL
> +       select DEBUG_UART_8250

This entry should not be a select. It will break multi-platform.

Sort the select entries alphabetically.

> +       help
> +         This enables support for systems based on Broadcom IPROC architected SoCs.
> +         The IPROC complex contains one or more ARM CPUs along with common
> +         core periperals. Application specific SoCs are created by adding a
> +         uArchitecture containing peripherals outside of the IPROC complex.
> +         Currently supported SoCs are Cygnus.
> +
> +menu "iProc SoC based Machine types"
> +       depends on ARCH_BCM_IPROC
> +
> +       config ARCH_BCM_CYGNUS
> +               bool "Support Broadcom Cygnus board"
> +               select USB_ARCH_HAS_EHCI if USB_SUPPORT
> +               help
> +                 Support for Broadcom Cygnus SoC.
> +endmenu
> +
>  config ARCH_BCM_MOBILE
>         bool "Broadcom Mobile SoC Support" if ARCH_MULTI_V7
>         select ARCH_REQUIRE_GPIOLIB
> diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
> index b19a396..46e092a 100644
> --- a/arch/arm/mach-bcm/Makefile
> +++ b/arch/arm/mach-bcm/Makefile
> @@ -10,6 +10,9 @@
>  # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>  # GNU General Public License for more details.
>
> +# Cygnus
> +obj-$(CONFIG_ARCH_BCM_CYGNUS) +=  bcm_cygnus.o
> +
>  # BCM281XX
>  obj-$(CONFIG_ARCH_BCM_281XX)   += board_bcm281xx.o
>
> diff --git a/arch/arm/mach-bcm/bcm_cygnus.c b/arch/arm/mach-bcm/bcm_cygnus.c
> new file mode 100644
> index 0000000..8e430ed
> --- /dev/null
> +++ b/arch/arm/mach-bcm/bcm_cygnus.c
> @@ -0,0 +1,166 @@
> +/*
> + * Copyright 2014 Broadcom Corporation.  All rights reserved.
> + *
> + * Unless you and Broadcom execute a separate written software license
> + * agreement governing use of this software, this software is licensed to you
> + * under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/of_address.h>
> +#include <linux/of_platform.h>
> +#include <linux/clocksource.h>
> +#include <linux/clk-provider.h>
> +#include <linux/delay.h>
> +#include <asm/mach/arch.h>
> +#include <asm/mach/map.h>
> +#include <asm/proc-fns.h>
> +#include <asm/hardware/cache-l2x0.h>
> +
> +#define CRMU_MAIL_BOX1      0x03024028
> +#define CRMU_SOFT_RESET_CMD 0xFFFFFFFF
> +
> +/* CRU_RESET register */
> +static void * __iomem crmu_mail_box1_reg;
> +
> +#ifdef CONFIG_NEON
> +
> +#define CRU_BASE                  0x1800e000
> +#define CRU_SIZE                  0x34
> +#define CRU_CONTROL_OFFSET        0x0
> +#define CRU_PWRDWN_EN_OFFSET      0x4
> +#define CRU_PWRDWN_STATUS_OFFSET  0x8
> +#define CRU_NEON0_HW_RESET  6
> +#define CRU_CLAMP_ON_NEON0  20
> +#define CRU_PWRONIN_NEON0   21
> +#define CRU_PWRONOUT_NEON0  21
> +#define CRU_PWROKIN_NEON0   22
> +#define CRU_PWROKOUT_NEON0  22
> +#define CRU_STATUS_DELAY_NS 500
> +#define CRU_MAX_RETRY_COUNT 10
> +#define CRU_RETRY_INTVL_US  1
> +
> +/* Power up the NEON/VFPv3 block. */
> +static void bcm_cygnus_powerup_neon(void)
> +{
> +       void * __iomem cru_base = ioremap(CRU_BASE, CRU_SIZE);
> +       u32 reg, i;
> +
> +       if (WARN_ON(!cru_base))
> +               return;
> +
> +       /* De-assert the neon hardware block reset */
> +       reg = readl(cru_base + CRU_CONTROL_OFFSET);
> +       reg &= ~(1 << CRU_NEON0_HW_RESET);
> +       writel(reg, cru_base + CRU_CONTROL_OFFSET);
> +
> +       /* Assert the power ON register bit */
> +       reg = readl(cru_base + CRU_PWRDWN_EN_OFFSET);
> +       reg |= (1 << CRU_PWRONIN_NEON0);
> +       writel(reg, cru_base + CRU_PWRDWN_EN_OFFSET);
> +
> +       /*
> +        * Wait up to 10 usec in 1 usec increments for the
> +        * status register to acknowledge the power ON assert
> +        */
> +       for (i = 0; i < CRU_MAX_RETRY_COUNT; i++) {
> +               reg = readl(cru_base + CRU_PWRDWN_STATUS_OFFSET);
> +               if (reg & CRU_PWRONOUT_NEON0)
> +                       break;
> +
> +               udelay(CRU_RETRY_INTVL_US);
> +       }
> +
> +       if (WARN_ON(i == CRU_MAX_RETRY_COUNT))
> +               goto neon_unmap;
> +
> +       /* Wait 0.5 usec = 500 nsec */
> +       ndelay(CRU_STATUS_DELAY_NS);
> +
> +       /* Assert the power OK register bit */
> +       reg = readl(cru_base + CRU_PWRDWN_EN_OFFSET);
> +       reg |= (1 << CRU_PWROKIN_NEON0);
> +       writel(reg, cru_base + CRU_PWRDWN_EN_OFFSET);
> +
> +       /*
> +        * Wait up to 10 usec in 1 usec increments for the
> +        * status register to acknowledge the power OK assert
> +        */
> +       for (i = 0; i < CRU_MAX_RETRY_COUNT; i++) {
> +               reg = readl(cru_base + CRU_PWRDWN_STATUS_OFFSET);
> +               if (reg & CRU_PWROKOUT_NEON0)
> +                       break;
> +
> +               udelay(CRU_RETRY_INTVL_US);
> +       }
> +
> +       if (WARN_ON(i == CRU_MAX_RETRY_COUNT))
> +               goto neon_unmap;
> +
> +       /* Wait 0.5 usec = 500 nsec */
> +       ndelay(CRU_STATUS_DELAY_NS);
> +
> +       /* Set the logic clamp for the neon block */
> +       reg = readl(cru_base + CRU_PWRDWN_EN_OFFSET);
> +       reg &= ~(1 << CRU_CLAMP_ON_NEON0);
> +       writel(reg, cru_base + CRU_PWRDWN_EN_OFFSET);
> +
> +       /* Wait 0.5 usec = 500 nsec */
> +       ndelay(CRU_STATUS_DELAY_NS);
> +
> +       /* Reset the neon hardware block */
> +       reg = readl(cru_base + CRU_CONTROL_OFFSET);
> +       reg |= (1 << CRU_NEON0_HW_RESET);
> +       writel(reg, cru_base + CRU_CONTROL_OFFSET);
> +
> +neon_unmap:
> +       iounmap(cru_base);
> +}
> +#endif /* CONFIG_NEON */

Is this a single core chip? If not, it seems like all this would
change when you add SMP support.

Rob

Re: [PATCH 1/6] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Arnd Bergmann]

On Wednesday 08 October 2014 05:27:24 Scott Branden wrote:
> >> diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
> >> index fc93800..2dd3f78 100644
> >> --- a/arch/arm/mach-bcm/Kconfig
> >> +++ b/arch/arm/mach-bcm/Kconfig
> >> @@ -5,6 +5,37 @@ menuconfig ARCH_BCM
> >>
> >>   if ARCH_BCM
> >>
> >> +config ARCH_BCM_IPROC
> >> +	bool "Broadcom ARMv7 iProc boards" if ARCH_MULTI_V7
> >> +	select ARM_GIC
> >> +	select CACHE_L2X0
> >> +	select HAVE_ARM_TWD if LOCAL_TIMERS
> >> +	select HAVE_CLK
> >> +	select CLKSRC_OF
> >> +	select CLKSRC_MMIO
> >> +	select GENERIC_CLOCKEVENTS
> >> +	select ARM_GLOBAL_TIMER
> >> +	select ARCH_REQUIRE_GPIOLIB
> >> +	select ARM_AMBA
> >> +	select PINCTRL
> >> +	select DEBUG_UART_8250
> >
> > A lot of these are implied by ARCH_MULTI_V7, just drop them here.
> >
> > Some others like DEBUG_UART_8250 should remain user-selectable, if
> > the platform works without them.
> >
> Will review.  It looks like DEBUG_UART_8250 actually has to move to 
> Kconfig.debug as that is where everyone else selects it.

Actually I think you also need to use DEBUG_LL_UART_8250 rather than
DEBUG_UART_8250.

> >> +	help
> >> +	  This enables support for systems based on Broadcom IPROC architected SoCs.
> >> +	  The IPROC complex contains one or more ARM CPUs along with common
> >> +	  core periperals. Application specific SoCs are created by adding a
> >> +	  uArchitecture containing peripherals outside of the IPROC complex.
> >> +	  Currently supported SoCs are Cygnus.
> >> +
> >> +menu "iProc SoC based Machine types"
> >> +	depends on ARCH_BCM_IPROC
> >> +
> >> +	config ARCH_BCM_CYGNUS
> >> +		bool "Support Broadcom Cygnus board"
> >> +		select USB_ARCH_HAS_EHCI if USB_SUPPORT
> >> +		help
> >> +		  Support for Broadcom Cygnus SoC.
> >> +endmenu
> >
> > I don't think you need per-board config options. The main option
> > above should be enough.
> This is not a per-board config option.  This is actually a per-SoC 
> uArchtecture selection.  More major uArchectures will be added to the 
> IPROC.  Will Change comment to "Support Broadcom Cygnus SoC"

Ok, sounds fine, but remove ARCH_BCM_IPROC then. There should be
no need for a three-level deep hierarchy (BCM -> IPROC -> CYGNUS)


> >> +/* CRU_RESET register */
> >> +static void * __iomem crmu_mail_box1_reg;
> >> +
> >> +#ifdef CONFIG_NEON
> >> +
> >> +#define CRU_BASE                  0x1800e000
> >> +#define CRU_SIZE                  0x34
> >> +#define CRU_CONTROL_OFFSET        0x0
> >> +#define CRU_PWRDWN_EN_OFFSET      0x4
> >> +#define CRU_PWRDWN_STATUS_OFFSET  0x8
> >> +#define CRU_NEON0_HW_RESET  6
> >> +#define CRU_CLAMP_ON_NEON0  20
> >> +#define CRU_PWRONIN_NEON0   21
> >> +#define CRU_PWRONOUT_NEON0  21
> >> +#define CRU_PWROKIN_NEON0   22
> >> +#define CRU_PWROKOUT_NEON0  22
> >> +#define CRU_STATUS_DELAY_NS 500
> >> +#define CRU_MAX_RETRY_COUNT 10
> >> +#define CRU_RETRY_INTVL_US  1
> >> +
> >> +/* Power up the NEON/VFPv3 block. */
> >> +static void bcm_cygnus_powerup_neon(void)
> >> +{
> >> +	void * __iomem cru_base = ioremap(CRU_BASE, CRU_SIZE);
> >> +	u32 reg, i;
> >
> > Same thing here: this should really use the device node for CRU.
> >
> > Can you describe what the CRU is? Is this specific to NEON or is
> > it some general-purpose power management unit?
> >
> It's a central resource unit with a lot of random registers to perform 
> various operations.  To reduce confusion I'll probably move this out of 
> the kernel init and into the bootloader.  This will simplify the kernel 
> init.

That would help too, yes.

> >> +
> >> +static const char const *bcm_cygnus_dt_compat[] = {
> >> +	"brcm,cygnus",
> >> +	NULL,
> >> +};
> >> +
> >> +DT_MACHINE_START(BCM_CYGNUS_DT, "Broadcom Cygnus SoC")
> >> +	.init_machine = bcm_cygnus_init,
> >> +	.map_io = debug_ll_io_init,
> >> +	.dt_compat = bcm_cygnus_dt_compat,
> >> +	.restart   = bcm_cygnus_restart
> >> +MACHINE_END
> >
> > The map_io pointer is unnecessary, and the restart pointer should get
> > set by the reset driver. I hope we can find a way to avoid the
> > bcm_cygnus_init callback as well.
> bcm_cygnus_init callback can be removed by moving initialization to 
> bootloader.

Ok, perfect!

	Arnd

Re: [PATCH 3/6] dt-bindings: Document Broadcom Cygnus SoC and clock driver

[Arnd Bergmann]

On Wednesday 08 October 2014 03:58:15 Scott Branden wrote:
> On 14-10-08 12:57 AM, Arnd Bergmann wrote:
> > On Tuesday 07 October 2014 22:27:02 Scott Branden wrote:
> >> diff --git a/Documentation/devicetree/bindings/arm/cygnus.txt b/Documentation/devicetree/bindings/arm/cygnus.txt
> >> new file mode 100644
> >> index 0000000..a210377
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/arm/cygnus.txt
> >> @@ -0,0 +1,12 @@
> >> +Broadcom Cygnus device tree bindings
> >> +------------------------------------
> >> +
> >> +All Cygnus boards shall have the following properties:
> >> +
> >> +Required root node property:
> >> +       - compatible = "brcm,cygnus";
> >
> > Can you add a more specific model number for the soc as well?
> > I assume that cygnus refers to more than one model, so you
> > should probably list both the family and the individual
> > SoC type here.
> Add specific model numbers does not seem necessary because they are not 
> needed to be specified in the device tree for compatible purposes for 
> the kernel to work.  Plus, the list of model numbers will continue to 
> grow over time and compatible strings would need to be added to the 
> kernel for no apparent reason?

It's always helpful to have them in the DT though, in case you ever
need to add a workaround for one of the SoCs.

You can change the description to just state the format of the
more specific model number so you don't need to add the particular
type to the binding, but I'd definitely recommend listing both
a generic and a more specific name here, such as

	compatible = "brcm,bcm123456", "brcm,cygnus";

> >> +Boards variants shall have the following additional properties:
> >> +
> >> +Required root node property for the BCM911360_ENTPHN board:
> >> +       - compatible = "brcm,bcm911360_entphn";
> >>
> >
> > We normally don't list specific boards here, since it's hard to
> > keep up.
> Thanks - removed specific boards from file and moved the cygnus.txt file 
> to devicetree/bindings/arm/bcm/cygnus.txt in next version.  This seems 
> to be like the appropriate place to put this document. We will need to 
> add back in board specific bindings when ALSA support is added.  But 
> that will be a later commit to deal with.

I believe most new alsa drivers can now use the binding from
Documentation/devicetree/bindings/sound/simple-card.txt
so you should no longer need a board specific driver or binding
for those.

	Arnd

Re: [PATCH 1/6] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Scott Branden]

On 14-10-08 06:28 AM, Arnd Bergmann wrote:
> On Wednesday 08 October 2014 05:27:24 Scott Branden wrote:
>>>> diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
>>>> index fc93800..2dd3f78 100644
>>>> --- a/arch/arm/mach-bcm/Kconfig
>>>> +++ b/arch/arm/mach-bcm/Kconfig
>>>> @@ -5,6 +5,37 @@ menuconfig ARCH_BCM
>>>>
>>>>    if ARCH_BCM
>>>>
>>>> +config ARCH_BCM_IPROC
>>>> +	bool "Broadcom ARMv7 iProc boards" if ARCH_MULTI_V7
>>>> +	select ARM_GIC
>>>> +	select CACHE_L2X0
>>>> +	select HAVE_ARM_TWD if LOCAL_TIMERS
>>>> +	select HAVE_CLK
>>>> +	select CLKSRC_OF
>>>> +	select CLKSRC_MMIO
>>>> +	select GENERIC_CLOCKEVENTS
>>>> +	select ARM_GLOBAL_TIMER
>>>> +	select ARCH_REQUIRE_GPIOLIB
>>>> +	select ARM_AMBA
>>>> +	select PINCTRL
>>>> +	select DEBUG_UART_8250
>>>
>>> A lot of these are implied by ARCH_MULTI_V7, just drop them here.
>>>
>>> Some others like DEBUG_UART_8250 should remain user-selectable, if
>>> the platform works without them.
>>>
>> Will review.  It looks like DEBUG_UART_8250 actually has to move to
>> Kconfig.debug as that is where everyone else selects it.
>
> Actually I think you also need to use DEBUG_LL_UART_8250 rather than
> DEBUG_UART_8250.
>
>>>> +	help
>>>> +	  This enables support for systems based on Broadcom IPROC architected SoCs.
>>>> +	  The IPROC complex contains one or more ARM CPUs along with common
>>>> +	  core periperals. Application specific SoCs are created by adding a
>>>> +	  uArchitecture containing peripherals outside of the IPROC complex.
>>>> +	  Currently supported SoCs are Cygnus.
>>>> +
>>>> +menu "iProc SoC based Machine types"
>>>> +	depends on ARCH_BCM_IPROC
>>>> +
>>>> +	config ARCH_BCM_CYGNUS
>>>> +		bool "Support Broadcom Cygnus board"
>>>> +		select USB_ARCH_HAS_EHCI if USB_SUPPORT
>>>> +		help
>>>> +		  Support for Broadcom Cygnus SoC.
>>>> +endmenu
>>>
>>> I don't think you need per-board config options. The main option
>>> above should be enough.
>> This is not a per-board config option.  This is actually a per-SoC
>> uArchtecture selection.  More major uArchectures will be added to the
>> IPROC.  Will Change comment to "Support Broadcom Cygnus SoC"
>
> Ok, sounds fine, but remove ARCH_BCM_IPROC then. There should be
> no need for a three-level deep hierarchy (BCM -> IPROC -> CYGNUS)
>
I do not need a 3-deep hierarchy, I need a 2-deep hierarchy for IPROC 
and CYGNUS (and future SoCs that have IPROC Architecture in common).  I 
can move IPROC out of the mach-bcm directory if you like a create a new 
directory?  But it looks like the purpose of mach-bcm is to consolidate 
all Broadcom chipsets in it?
>
>>>> +/* CRU_RESET register */
>>>> +static void * __iomem crmu_mail_box1_reg;
>>>> +
>>>> +#ifdef CONFIG_NEON
>>>> +
>>>> +#define CRU_BASE                  0x1800e000
>>>> +#define CRU_SIZE                  0x34
>>>> +#define CRU_CONTROL_OFFSET        0x0
>>>> +#define CRU_PWRDWN_EN_OFFSET      0x4
>>>> +#define CRU_PWRDWN_STATUS_OFFSET  0x8
>>>> +#define CRU_NEON0_HW_RESET  6
>>>> +#define CRU_CLAMP_ON_NEON0  20
>>>> +#define CRU_PWRONIN_NEON0   21
>>>> +#define CRU_PWRONOUT_NEON0  21
>>>> +#define CRU_PWROKIN_NEON0   22
>>>> +#define CRU_PWROKOUT_NEON0  22
>>>> +#define CRU_STATUS_DELAY_NS 500
>>>> +#define CRU_MAX_RETRY_COUNT 10
>>>> +#define CRU_RETRY_INTVL_US  1
>>>> +
>>>> +/* Power up the NEON/VFPv3 block. */
>>>> +static void bcm_cygnus_powerup_neon(void)
>>>> +{
>>>> +	void * __iomem cru_base = ioremap(CRU_BASE, CRU_SIZE);
>>>> +	u32 reg, i;
>>>
>>> Same thing here: this should really use the device node for CRU.
>>>
>>> Can you describe what the CRU is? Is this specific to NEON or is
>>> it some general-purpose power management unit?
>>>
>> It's a central resource unit with a lot of random registers to perform
>> various operations.  To reduce confusion I'll probably move this out of
>> the kernel init and into the bootloader.  This will simplify the kernel
>> init.
>
> That would help too, yes.
>
>>>> +
>>>> +static const char const *bcm_cygnus_dt_compat[] = {
>>>> +	"brcm,cygnus",
>>>> +	NULL,
>>>> +};
>>>> +
>>>> +DT_MACHINE_START(BCM_CYGNUS_DT, "Broadcom Cygnus SoC")
>>>> +	.init_machine = bcm_cygnus_init,
>>>> +	.map_io = debug_ll_io_init,
>>>> +	.dt_compat = bcm_cygnus_dt_compat,
>>>> +	.restart   = bcm_cygnus_restart
>>>> +MACHINE_END
>>>
>>> The map_io pointer is unnecessary, and the restart pointer should get
>>> set by the reset driver. I hope we can find a way to avoid the
>>> bcm_cygnus_init callback as well.
>> bcm_cygnus_init callback can be removed by moving initialization to
>> bootloader.
>
> Ok, perfect!
>
> 	Arnd
>

Re: [PATCH 1/6] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Scott Branden]

Thanks for comments - inline.

On 14-10-08 06:10 AM, Rob Herring wrote:
> On Wed, Oct 8, 2014 at 12:27 AM, Scott Branden <sbranden@broadcom.com> wrote:
>> From: Jonathan Richardson <jonathar@broadcom.com>
>>
>> Adds initial support for the Cygnus SoC based on Broadcom’s iProc series.
>>
>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>> Reviewed-by: Desmond Liu <desmondl@broadcom.com>
>> Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
>> Tested-by: Jonathan Richardson <jonathar@broadcom.com>
>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>> ---
>>   arch/arm/mach-bcm/Kconfig      |   31 ++++++++
>>   arch/arm/mach-bcm/Makefile     |    3 +
>>   arch/arm/mach-bcm/bcm_cygnus.c |  166 ++++++++++++++++++++++++++++++++++++++++
>>   3 files changed, 200 insertions(+)
>>   create mode 100644 arch/arm/mach-bcm/bcm_cygnus.c
>>
>> diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
>> index fc93800..2dd3f78 100644
>> --- a/arch/arm/mach-bcm/Kconfig
>> +++ b/arch/arm/mach-bcm/Kconfig
>> @@ -5,6 +5,37 @@ menuconfig ARCH_BCM
>>
>>   if ARCH_BCM
>>
>> +config ARCH_BCM_IPROC
>> +       bool "Broadcom ARMv7 iProc boards" if ARCH_MULTI_V7
>> +       select ARM_GIC
>> +       select CACHE_L2X0
>> +       select HAVE_ARM_TWD if LOCAL_TIMERS
>
> LOCAL_TIMERS does not exist anymore.
Will change to if SMP so it will work for other iproc chips that have 
SMP going forward.
>
>> +       select HAVE_CLK
>
> Selected already by multi-platform.
>
>> +       select CLKSRC_OF
>> +       select CLKSRC_MMIO
>
> These should be selected by the timers that need these rather than the platform.
>
OK
>> +       select GENERIC_CLOCKEVENTS
>
> Selected already by multi-platform.
>
>> +       select ARM_GLOBAL_TIMER
>> +       select ARCH_REQUIRE_GPIOLIB
>> +       select ARM_AMBA
>> +       select PINCTRL
>> +       select DEBUG_UART_8250
>
> This entry should not be a select. It will break multi-platform.
Yes, this select will be removed from here in next version and moved to 
kconfig.debug as other platforms do.
>
> Sort the select entries alphabetically.
>
>> +       help
>> +         This enables support for systems based on Broadcom IPROC architected SoCs.
>> +         The IPROC complex contains one or more ARM CPUs along with common
>> +         core periperals. Application specific SoCs are created by adding a
>> +         uArchitecture containing peripherals outside of the IPROC complex.
>> +         Currently supported SoCs are Cygnus.
>> +
>> +menu "iProc SoC based Machine types"
>> +       depends on ARCH_BCM_IPROC
>> +
>> +       config ARCH_BCM_CYGNUS
>> +               bool "Support Broadcom Cygnus board"
>> +               select USB_ARCH_HAS_EHCI if USB_SUPPORT
>> +               help
>> +                 Support for Broadcom Cygnus SoC.
>> +endmenu
>> +
>>   config ARCH_BCM_MOBILE
>>          bool "Broadcom Mobile SoC Support" if ARCH_MULTI_V7
>>          select ARCH_REQUIRE_GPIOLIB
>> diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
>> index b19a396..46e092a 100644
>> --- a/arch/arm/mach-bcm/Makefile
>> +++ b/arch/arm/mach-bcm/Makefile
>> @@ -10,6 +10,9 @@
>>   # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>   # GNU General Public License for more details.
>>
>> +# Cygnus
>> +obj-$(CONFIG_ARCH_BCM_CYGNUS) +=  bcm_cygnus.o
>> +
>>   # BCM281XX
>>   obj-$(CONFIG_ARCH_BCM_281XX)   += board_bcm281xx.o
>>
>> diff --git a/arch/arm/mach-bcm/bcm_cygnus.c b/arch/arm/mach-bcm/bcm_cygnus.c
>> new file mode 100644
>> index 0000000..8e430ed
>> --- /dev/null
>> +++ b/arch/arm/mach-bcm/bcm_cygnus.c
>> @@ -0,0 +1,166 @@
>> +/*
>> + * Copyright 2014 Broadcom Corporation.  All rights reserved.
>> + *
>> + * Unless you and Broadcom execute a separate written software license
>> + * agreement governing use of this software, this software is licensed to you
>> + * under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation version 2.
>> + *
>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> + * kind, whether express or implied; without even the implied warranty
>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/of_address.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/clocksource.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/delay.h>
>> +#include <asm/mach/arch.h>
>> +#include <asm/mach/map.h>
>> +#include <asm/proc-fns.h>
>> +#include <asm/hardware/cache-l2x0.h>
>> +
>> +#define CRMU_MAIL_BOX1      0x03024028
>> +#define CRMU_SOFT_RESET_CMD 0xFFFFFFFF
>> +
>> +/* CRU_RESET register */
>> +static void * __iomem crmu_mail_box1_reg;
>> +
>> +#ifdef CONFIG_NEON
>> +
>> +#define CRU_BASE                  0x1800e000
>> +#define CRU_SIZE                  0x34
>> +#define CRU_CONTROL_OFFSET        0x0
>> +#define CRU_PWRDWN_EN_OFFSET      0x4
>> +#define CRU_PWRDWN_STATUS_OFFSET  0x8
>> +#define CRU_NEON0_HW_RESET  6
>> +#define CRU_CLAMP_ON_NEON0  20
>> +#define CRU_PWRONIN_NEON0   21
>> +#define CRU_PWRONOUT_NEON0  21
>> +#define CRU_PWROKIN_NEON0   22
>> +#define CRU_PWROKOUT_NEON0  22
>> +#define CRU_STATUS_DELAY_NS 500
>> +#define CRU_MAX_RETRY_COUNT 10
>> +#define CRU_RETRY_INTVL_US  1
>> +
>> +/* Power up the NEON/VFPv3 block. */
>> +static void bcm_cygnus_powerup_neon(void)
>> +{
>> +       void * __iomem cru_base = ioremap(CRU_BASE, CRU_SIZE);
>> +       u32 reg, i;
>> +
>> +       if (WARN_ON(!cru_base))
>> +               return;
>> +
>> +       /* De-assert the neon hardware block reset */
>> +       reg = readl(cru_base + CRU_CONTROL_OFFSET);
>> +       reg &= ~(1 << CRU_NEON0_HW_RESET);
>> +       writel(reg, cru_base + CRU_CONTROL_OFFSET);
>> +
>> +       /* Assert the power ON register bit */
>> +       reg = readl(cru_base + CRU_PWRDWN_EN_OFFSET);
>> +       reg |= (1 << CRU_PWRONIN_NEON0);
>> +       writel(reg, cru_base + CRU_PWRDWN_EN_OFFSET);
>> +
>> +       /*
>> +        * Wait up to 10 usec in 1 usec increments for the
>> +        * status register to acknowledge the power ON assert
>> +        */
>> +       for (i = 0; i < CRU_MAX_RETRY_COUNT; i++) {
>> +               reg = readl(cru_base + CRU_PWRDWN_STATUS_OFFSET);
>> +               if (reg & CRU_PWRONOUT_NEON0)
>> +                       break;
>> +
>> +               udelay(CRU_RETRY_INTVL_US);
>> +       }
>> +
>> +       if (WARN_ON(i == CRU_MAX_RETRY_COUNT))
>> +               goto neon_unmap;
>> +
>> +       /* Wait 0.5 usec = 500 nsec */
>> +       ndelay(CRU_STATUS_DELAY_NS);
>> +
>> +       /* Assert the power OK register bit */
>> +       reg = readl(cru_base + CRU_PWRDWN_EN_OFFSET);
>> +       reg |= (1 << CRU_PWROKIN_NEON0);
>> +       writel(reg, cru_base + CRU_PWRDWN_EN_OFFSET);
>> +
>> +       /*
>> +        * Wait up to 10 usec in 1 usec increments for the
>> +        * status register to acknowledge the power OK assert
>> +        */
>> +       for (i = 0; i < CRU_MAX_RETRY_COUNT; i++) {
>> +               reg = readl(cru_base + CRU_PWRDWN_STATUS_OFFSET);
>> +               if (reg & CRU_PWROKOUT_NEON0)
>> +                       break;
>> +
>> +               udelay(CRU_RETRY_INTVL_US);
>> +       }
>> +
>> +       if (WARN_ON(i == CRU_MAX_RETRY_COUNT))
>> +               goto neon_unmap;
>> +
>> +       /* Wait 0.5 usec = 500 nsec */
>> +       ndelay(CRU_STATUS_DELAY_NS);
>> +
>> +       /* Set the logic clamp for the neon block */
>> +       reg = readl(cru_base + CRU_PWRDWN_EN_OFFSET);
>> +       reg &= ~(1 << CRU_CLAMP_ON_NEON0);
>> +       writel(reg, cru_base + CRU_PWRDWN_EN_OFFSET);
>> +
>> +       /* Wait 0.5 usec = 500 nsec */
>> +       ndelay(CRU_STATUS_DELAY_NS);
>> +
>> +       /* Reset the neon hardware block */
>> +       reg = readl(cru_base + CRU_CONTROL_OFFSET);
>> +       reg |= (1 << CRU_NEON0_HW_RESET);
>> +       writel(reg, cru_base + CRU_CONTROL_OFFSET);
>> +
>> +neon_unmap:
>> +       iounmap(cru_base);
>> +}
>> +#endif /* CONFIG_NEON */
>
> Is this a single core chip? If not, it seems like all this would
> change when you add SMP support.
Cygnus is a single core chip.  There are other chips in the IPROC family 
that are multi-core.  But they are not part of the Cygnus 
sub-architecture and would have different ways of powering up.  These 
will be added in a different patch in the future.
>
> Rob
>

Re: [PATCH 1/6] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Arnd Bergmann]

On Wednesday 08 October 2014 09:27:08 Scott Branden wrote:
> On 14-10-08 06:28 AM, Arnd Bergmann wrote:
> > On Wednesday 08 October 2014 05:27:24 Scott Branden wrote:
> >>>
> >>> I don't think you need per-board config options. The main option
> >>> above should be enough.
> >> This is not a per-board config option.  This is actually a per-SoC
> >> uArchtecture selection.  More major uArchectures will be added to the
> >> IPROC.  Will Change comment to "Support Broadcom Cygnus SoC"
> >
> > Ok, sounds fine, but remove ARCH_BCM_IPROC then. There should be
> > no need for a three-level deep hierarchy (BCM -> IPROC -> CYGNUS)
> >
> I do not need a 3-deep hierarchy, I need a 2-deep hierarchy for IPROC 
> and CYGNUS (and future SoCs that have IPROC Architecture in common).  I 
> can move IPROC out of the mach-bcm directory if you like a create a new 
> directory?  But it looks like the purpose of mach-bcm is to consolidate 
> all Broadcom chipsets in it?

Yes, better leave it all in mach-bcm. You really shouldn't need much
code at all that is soc specific, so adding new directories is not
encouraged. We have some platforms that need no code at all, and on
arm64 that is required.

Isn't Northstar also IPROC? That one didn't seem to need the symbol.

Could you make ARCH_BCM_IPROC a silent symbol that is just selected
by each SoC family specific symbol?

	Arnd

Re: [PATCH 1/6] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Scott Branden]

On 14-10-08 11:12 AM, Arnd Bergmann wrote:
> On Wednesday 08 October 2014 09:27:08 Scott Branden wrote:
>> On 14-10-08 06:28 AM, Arnd Bergmann wrote:
>>> On Wednesday 08 October 2014 05:27:24 Scott Branden wrote:
>>>>>
>>>>> I don't think you need per-board config options. The main option
>>>>> above should be enough.
>>>> This is not a per-board config option.  This is actually a per-SoC
>>>> uArchtecture selection.  More major uArchectures will be added to the
>>>> IPROC.  Will Change comment to "Support Broadcom Cygnus SoC"
>>>
>>> Ok, sounds fine, but remove ARCH_BCM_IPROC then. There should be
>>> no need for a three-level deep hierarchy (BCM -> IPROC -> CYGNUS)
>>>
>> I do not need a 3-deep hierarchy, I need a 2-deep hierarchy for IPROC
>> and CYGNUS (and future SoCs that have IPROC Architecture in common).  I
>> can move IPROC out of the mach-bcm directory if you like a create a new
>> directory?  But it looks like the purpose of mach-bcm is to consolidate
>> all Broadcom chipsets in it?
>
> Yes, better leave it all in mach-bcm. You really shouldn't need much
> code at all that is soc specific, so adding new directories is not
> encouraged. We have some platforms that need no code at all, and on
> arm64 that is required.
>
> Isn't Northstar also IPROC? That one didn't seem to need the symbol.
Yes, Northstar is an older version of IPROC.  We may be able to 
consolidate it under the IPROC family as we upstream additional SoCs and 
drivers.  Have the commonality with ARCH_BCM_IPROC will allow this.
>
> Could you make ARCH_BCM_IPROC a silent symbol that is just selected
> by each SoC family specific symbol?
OK, I will make ARCH_BCM_IPROC a silent symbol.
>
> 	Arnd
>

Re: [PATCH 1/6] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Scott Branden]

On 14-10-08 11:12 AM, Arnd Bergmann wrote:
> On Wednesday 08 October 2014 09:27:08 Scott Branden wrote:
>> On 14-10-08 06:28 AM, Arnd Bergmann wrote:
>>> On Wednesday 08 October 2014 05:27:24 Scott Branden wrote:
>>>>>
>>>>> I don't think you need per-board config options. The main option
>>>>> above should be enough.
>>>> This is not a per-board config option.  This is actually a per-SoC
>>>> uArchtecture selection.  More major uArchectures will be added to the
>>>> IPROC.  Will Change comment to "Support Broadcom Cygnus SoC"
>>>
>>> Ok, sounds fine, but remove ARCH_BCM_IPROC then. There should be
>>> no need for a three-level deep hierarchy (BCM -> IPROC -> CYGNUS)
>>>
>> I do not need a 3-deep hierarchy, I need a 2-deep hierarchy for IPROC
>> and CYGNUS (and future SoCs that have IPROC Architecture in common).  I
>> can move IPROC out of the mach-bcm directory if you like a create a new
>> directory?  But it looks like the purpose of mach-bcm is to consolidate
>> all Broadcom chipsets in it?
>
> Yes, better leave it all in mach-bcm. You really shouldn't need much
> code at all that is soc specific, so adding new directories is not
> encouraged. We have some platforms that need no code at all, and on
> arm64 that is required.
>
> Isn't Northstar also IPROC? That one didn't seem to need the symbol.
>
> Could you make ARCH_BCM_IPROC a silent symbol that is just selected
> by each SoC family specific symbol?
It looks like I will also be able to add Northstar under the 
ARCH_BCM_IPROC.  This will be good momentum to cleaning up and 
consolidate support going forward.
I will change the Kconfig such that ARCH_BCM_5301X selects ARCH_BCM_IPROC.

Thanks.
>
> 	Arnd
>

Re: [PATCH 1/6] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Arnd Bergmann]

On Wednesday 08 October 2014 15:16:55 Scott Branden wrote:
> It looks like I will also be able to add Northstar under the 
> ARCH_BCM_IPROC.  This will be good momentum to cleaning up and 
> consolidate support going forward.
> I will change the Kconfig such that ARCH_BCM_5301X selects ARCH_BCM_IPROC.
> 
> 

Ok, sounds good.

	Arnd

[PATCH V4 0/7] Add initial support for Broadcom Cygnus SoC

[Scott Branden]

This patchset contains initial support for Broadcom's Cygnus SoC based on our
iProc architecture. Initial support is minimal and includes just the mach
platform code, clock driver, and a basic device tree configuration. Peripheral
drivers will be submitted soon, as will device tree configurations for other
Cygnus board variants.

Changes from v3:
 - restart functionality removed.  Will be added in a different patchset
   in drivers/power
 - removed NEON init sequence.  Will be moved to bootloader
 - cleaned up Kconfigs for ARCH_BCM_CYGNUS by removing unnecessary selects
 - consolidated ARCH_BCM_IPROC with select from ARCH_BCM_CYGNUS and
   ARCH_BCM5301X
 - removed bcm911360_entphn binding
 - added documentation for SoCs currently supported in Cygnus family


Changes from v2:
 - rebased to 3.17 kernel

Changes from v1:
 - Address code review comments as per previous responses.
 - Copyright headers updated to remove Broadcom URL.
 - mach platform code still contains hard coded addresses. These address are
   the same for all Cygnus variants. Could you please provide guidance on where
   they should go if you would still like them changed.  There does not seem to
   be a reason to change them to device tree as they do not change.


Jonathan Richardson (5):
  ARM: cygnus: Initial support for Broadcom Cygnus SoC
  clk: Clock driver support for Broadcom Cygnus SoC
  dt-bindings: Document Broadcom Cygnus SoC and clock driver
  ARM: cygnus defconfig : Initial defconfig for Broadcom Cygnus SoC
  ARM: dts: Enable Broadcom Cygnus SoC

Scott Branden (2):
  MAINTAINERS: Entry for Cygnus/iproc arm architecture and clock
    drivers
  ARM: multi_v7_defconfig: Enable ARCH_BCM_CYGNUS config

 .../devicetree/bindings/arm/bcm/cygnus.txt         |   31 +
 .../devicetree/bindings/clock/clk-cygnus.txt       |  121 ++
 .../devicetree/bindings/clock/clk-iproc.txt        |   48 +
 MAINTAINERS                                        |   17 +-
 arch/arm/Kconfig.debug                             |    2 +-
 arch/arm/boot/dts/Makefile                         |    1 +
 arch/arm/boot/dts/bcm-cygnus.dtsi                  |  349 ++++++
 arch/arm/boot/dts/bcm911360_entphn.dts             |   22 +
 arch/arm/configs/bcm_cygnus_defconfig              |  221 ++++
 arch/arm/configs/multi_v7_defconfig                |    1 +
 arch/arm/mach-bcm/Kconfig                          |   68 +-
 arch/arm/mach-bcm/Makefile                         |    3 +
 arch/arm/mach-bcm/bcm_cygnus.c                     |   26 +
 drivers/clk/Makefile                               |    1 +
 drivers/clk/bcm/Makefile                           |    2 +
 drivers/clk/bcm/clk-cygnus.c                       | 1186 ++++++++++++++++++++
 drivers/clk/bcm/clk-iproc.c                        |  451 ++++++++
 17 files changed, 2527 insertions(+), 23 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/cygnus.txt
 create mode 100644 Documentation/devicetree/bindings/clock/clk-cygnus.txt
 create mode 100644 Documentation/devicetree/bindings/clock/clk-iproc.txt
 create mode 100644 arch/arm/boot/dts/bcm-cygnus.dtsi
 create mode 100644 arch/arm/boot/dts/bcm911360_entphn.dts
 create mode 100644 arch/arm/configs/bcm_cygnus_defconfig
 create mode 100644 arch/arm/mach-bcm/bcm_cygnus.c
 create mode 100644 drivers/clk/bcm/clk-cygnus.c
 create mode 100644 drivers/clk/bcm/clk-iproc.c

-- 
1.7.9.5

[PATCH V4 1/7] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Scott Branden]

From: Jonathan Richardson <jonathar@broadcom.com>

Adds initial support for the Cygnus SoC based on Broadcom’s iProc series.
Move ARCH_BCM_5301x under the ARCH_BCM_IPROC architecture.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Desmond Liu <desmondl@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/Kconfig.debug         |    2 +-
 arch/arm/mach-bcm/Kconfig      |   68 +++++++++++++++++++++++++++-------------
 arch/arm/mach-bcm/Makefile     |    3 ++
 arch/arm/mach-bcm/bcm_cygnus.c |   26 +++++++++++++++
 4 files changed, 77 insertions(+), 22 deletions(-)
 create mode 100644 arch/arm/mach-bcm/bcm_cygnus.c

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index b11ad54..85363de 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -1051,7 +1051,7 @@ config DEBUG_UART_PL01X
 
 # Compatibility options for 8250
 config DEBUG_UART_8250
-	def_bool ARCH_DOVE || ARCH_EBSA110 || \
+	def_bool ARCH_BCM_IPROC || ARCH_DOVE || ARCH_EBSA110 || \
 		(FOOTBRIDGE && !DEBUG_DC21285_PORT) || \
 		ARCH_GEMINI || ARCH_IOP13XX || ARCH_IOP32X || \
 		ARCH_IOP33X || ARCH_IXP4XX || \
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index fc93800..b2b6752 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -5,6 +5,53 @@ menuconfig ARCH_BCM
 
 if ARCH_BCM
 
+menu "iProc SoC based Machine types"
+	config ARCH_BCM_IPROC
+		bool "Broadcom ARMv7 iProc boards" if ARCH_MULTI_V7
+		depends on ARCH_BCM_CYGNUS || ARCH_BCM_5301X
+		select ARM_GIC
+		select CACHE_L2X0
+		select HAVE_ARM_SCU if SMP
+		select HAVE_ARM_TWD if SMP
+		select ARM_GLOBAL_TIMER
+
+		select CLKSRC_MMIO
+		select ARCH_REQUIRE_GPIOLIB
+		select ARM_AMBA
+		select PINCTRL
+		help
+		  This enables support for systems based on Broadcom IPROC architected SoCs.
+		  The IPROC complex contains one or more ARM CPUs along with common
+		  core periperals. Application specific SoCs are created by adding a
+		  uArchitecture containing peripherals outside of the IPROC complex.
+		  Currently supported SoCs are Cygnus.
+
+	config ARCH_BCM_CYGNUS
+		bool "Broadcom Cygnus Support" if ARCH_MULTI_V7
+		select ARCH_BCM_IPROC
+		help
+			Enable support for the Cygnus family,
+			which includes the following variants:
+			BCM11300, BCM11320, BCM11350, BCM11360,
+			BCM58300, BCM58302, BCM58303, BCM58305.
+
+	config ARCH_BCM_5301X
+		bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
+		select ARCH_BCM_IPROC
+		help
+		  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
+
+		  This is a network SoC line mostly used in home routers and
+		  wifi access points, it's internal name is Northstar.
+		  This inclused the following SoC: BCM53010, BCM53011, BCM53012,
+		  BCM53014, BCM53015, BCM53016, BCM53017, BCM53018, BCM4707,
+		  BCM4708 and BCM4709.
+
+		  Do not confuse this with the BCM4760 which is a totally
+		  different SoC or with the older BCM47XX and BCM53XX based
+		  network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
+endmenu
+
 config ARCH_BCM_MOBILE
 	bool "Broadcom Mobile SoC Support" if ARCH_MULTI_V7
 	select ARCH_REQUIRE_GPIOLIB
@@ -78,27 +125,6 @@ config ARCH_BCM2835
 	  This enables support for the Broadcom BCM2835 SoC. This SoC is
 	  used in the Raspberry Pi and Roku 2 devices.
 
-config ARCH_BCM_5301X
-	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
-	select ARM_GIC
-	select CACHE_L2X0
-	select HAVE_ARM_SCU if SMP
-	select HAVE_ARM_TWD if SMP
-	select ARM_GLOBAL_TIMER
-	select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
-	help
-	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
-
-	  This is a network SoC line mostly used in home routers and
-	  wifi access points, it's internal name is Northstar.
-	  This inclused the following SoC: BCM53010, BCM53011, BCM53012,
-	  BCM53014, BCM53015, BCM53016, BCM53017, BCM53018, BCM4707,
-	  BCM4708 and BCM4709.
-
-	  Do not confuse this with the BCM4760 which is a totally
-	  different SoC or with the older BCM47XX and BCM53XX based
-	  network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
-
 config ARCH_BRCMSTB
 	bool "Broadcom BCM7XXX based boards" if ARCH_MULTI_V7
 	depends on MMU
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index b19a396..46e092a 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -10,6 +10,9 @@
 # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
 
+# Cygnus
+obj-$(CONFIG_ARCH_BCM_CYGNUS) +=  bcm_cygnus.o
+
 # BCM281XX
 obj-$(CONFIG_ARCH_BCM_281XX)	+= board_bcm281xx.o
 
diff --git a/arch/arm/mach-bcm/bcm_cygnus.c b/arch/arm/mach-bcm/bcm_cygnus.c
new file mode 100644
index 0000000..41b4933
--- /dev/null
+++ b/arch/arm/mach-bcm/bcm_cygnus.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <asm/mach/arch.h>
+
+static const char const *bcm_cygnus_dt_compat[] = {
+	"brcm,cygnus",
+	NULL,
+};
+
+DT_MACHINE_START(BCM_CYGNUS_DT, "Broadcom Cygnus SoC")
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
+	.dt_compat = bcm_cygnus_dt_compat,
+MACHINE_END
-- 
1.7.9.5

[PATCH V4 2/7] clk: Clock driver support for Broadcom Cygnus SoC

[Scott Branden]

From: Jonathan Richardson <jonathar@broadcom.com>

The iProc clock driver controls PLLs common across iProc chips. The
cygnus driver controls cygnus specific features and variations.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/clk/Makefile         |    1 +
 drivers/clk/bcm/Makefile     |    2 +
 drivers/clk/bcm/clk-cygnus.c | 1186 ++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/bcm/clk-iproc.c  |  451 ++++++++++++++++
 4 files changed, 1640 insertions(+)
 create mode 100644 drivers/clk/bcm/clk-cygnus.c
 create mode 100644 drivers/clk/bcm/clk-iproc.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index f537a0b..8ac0a31 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_ARCH_VT8500)		+= clk-vt8500.o
 obj-$(CONFIG_COMMON_CLK_WM831X)		+= clk-wm831x.o
 obj-$(CONFIG_COMMON_CLK_XGENE)		+= clk-xgene.o
 obj-$(CONFIG_COMMON_CLK_AT91)		+= at91/
+obj-$(CONFIG_ARCH_BCM_IPROC)	+= bcm/
 obj-$(CONFIG_ARCH_BCM_MOBILE)		+= bcm/
 obj-$(CONFIG_ARCH_BERLIN)		+= berlin/
 obj-$(CONFIG_ARCH_HI3xxx)		+= hisilicon/
diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
index 6297d05..f803919 100644
--- a/drivers/clk/bcm/Makefile
+++ b/drivers/clk/bcm/Makefile
@@ -2,3 +2,5 @@ obj-$(CONFIG_CLK_BCM_KONA)	+= clk-kona.o
 obj-$(CONFIG_CLK_BCM_KONA)	+= clk-kona-setup.o
 obj-$(CONFIG_CLK_BCM_KONA)	+= clk-bcm281xx.o
 obj-$(CONFIG_CLK_BCM_KONA)	+= clk-bcm21664.o
+obj-$(CONFIG_ARCH_BCM_IPROC)	+= clk-iproc.o
+obj-$(CONFIG_ARCH_BCM_CYGNUS)	+= clk-cygnus.o
diff --git a/drivers/clk/bcm/clk-cygnus.c b/drivers/clk/bcm/clk-cygnus.c
new file mode 100644
index 0000000..2a4f976
--- /dev/null
+++ b/drivers/clk/bcm/clk-cygnus.c
@@ -0,0 +1,1186 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/clkdev.h>
+#include <linux/of_address.h>
+
+/*
+ * The CRU contains two similar PLLs: LCPLL and GENPLL,
+ * both with several output channels divided from the PLL
+ * output.
+ */
+
+#define CRU_LCPLL_CONTROL1_OFFSET  0x04
+#define CRU_LCPLL_STATUS_OFFSET    0x18
+
+#define LCPLL0_PDIV_SHIFT       26
+#define LCPLL0_PDIV_MASK        0xf
+#define LCPLL0_NDIV_SHIFT       16
+#define LCPLL0_NDIV_MASK        0x3ff
+#define LCPLL_ENABLEB_CH_SHIFT  7
+#define LCPLL_ENABLEB_CH_MASK   0x3f
+#define LCPLL_MDIV_MASK         0xff
+#define LCPLL_STATUS_LOCK_SHIFT 12
+
+#define LCPLL0_CONTROL0_OFFSET  0x00
+#define LCPLL0_CONTROL1_OFFSET  0x04
+#define LCPLL0_CONTROL2_OFFSET  0x08
+#define LCPLL0_CONTROL3_OFFSET  0x0c
+
+#define GENPLL_CONTROL0_OFFSET 0x00
+#define GENPLL_CONTROL1_OFFSET 0x04
+#define GENPLL_CONTROL2_OFFSET 0x08
+#define GENPLL_CONTROL3_OFFSET 0x0c
+#define GENPLL_CONTROL4_OFFSET 0x10
+#define GENPLL_CONTROL5_OFFSET 0x14
+#define GENPLL_CONTROL6_OFFSET 0x18
+#define GENPLL_CONTROL7_OFFSET 0x1c
+#define GENPLL_CONTROL8_OFFSET 0x20
+#define GENPLL_CONTROL9_OFFSET 0x24
+#define GENPLL_STATUS_OFFSET   0x28
+
+#define GENPLL_ENABLEB_CH_SHIFT    0x6
+#define GENPLL_ENABLEB_CH_MASK     0x3f
+
+#define GENPLL_STATUS_LOCK_SHIFT           12
+#define GENPLL_STATUS_LOCK_MASK            1
+#define GENPLL_CONTROL4_NDIV_INT_SHIFT     20
+#define GENPLL_CONTROL4_NDIV_INT_MASK      0x3FF
+#define GENPLL_CONTROL4_NDIV_FRAC_SHIFT    0
+#define GENPLL_CONTROL4_NDIV_FRAC_MASK     0xFFFFF
+#define GENPLL_CONTROL5_PDIV_SHIFT         0
+#define GENPLL_CONTROL5_PDIV_MASK          0xF
+#define GENPLL_MDIV_MASK                   0xff
+
+#define MIPI_DSI_GENPLL_ENABLEB_CH_SHIFT   12
+#define NDIV_FRAC_DIVISOR                  0x100000
+
+#define ASIU_MIPI_GENPLL_PWRON_SHIFT      20
+#define ASIU_MIPI_GENPLL_PWRON_PLL_SHIFT  19
+#define ASIU_MIPI_GENPLL_PWRON_BG_SHIFT   18
+#define ASIU_MIPI_GENPLL_PWRON_LDO_SHIFT  17
+#define ASIU_MIPI_GENPLL_ISO_IN_SHIFT     16
+#define ASIU_AUDIO_GENPLL_PWRON_PLL_SHIFT 11
+#define ASIU_AUDIO_GENPLL_PWRON_BG_SHIFT  10
+#define ASIU_AUDIO_GENPLL_PWRON_LDO_SHIFT 9
+#define ASIU_AUDIO_GENPLL_ISO_IN          8
+
+#define CLK_RATE_NO_DIV                   -1
+
+/*
+ * The clock framework may call recalc even if a clock is is unused, and
+ * therefore before being prepared/enabled. State checking is done for the
+ * MIPI PLL to prevent reading from a MIPI DSI register before the PLL is
+ * powered up because it will cause corruption (imprecise external aborts)
+ * sometimer later on.
+ */
+enum clock_state {
+	CLK_ENABLED,
+	CLK_PREPARED,
+	CLK_DISABLED
+};
+
+struct cygnus_clk {
+	struct clk_hw   hw;
+	void __iomem    *regs_base;
+	void __iomem    *pll_ctrl_reg;
+	void __iomem    *clock_gate_ctrl_reg;
+	int             chan;
+	int             internal_div;
+	unsigned long   rate;
+	enum clock_state state;
+};
+
+#define to_cygnus_clk(p) container_of(p, struct cygnus_clk, hw)
+
+/* Identifies LCPLL clock channels. */
+enum cygnus_lcpll_clk_chan {
+	LCPLL_CH0_PCIE_PHY_REF_CLK      = 0,
+	LCPLL_CH1_DDR_CLK               = 1,
+	LCPLL_CH2_SDIO_CLK              = 2,
+	LCPLL_CH3_USB_PHY_REF_CLK       = 3,
+	LCPLL_CH4_ASIU_SMART_CARD_CLK   = 4,
+	LCPLL_CH5                       = 5
+};
+
+/* Identifies GENPLL clock channels. */
+enum cygnus_genpll_clk_chan {
+	GENPLL_CH0_AXI21_CLK      = 0,
+	GENPLL_CH1_25MHZ_CLK      = 1,
+	GENPLL_CH2_SYS_CLK        = 2,
+	GENPLL_CH3_ETHERNET_CLK   = 3,
+	GENPLL_CH4_ASIU_AUDIO_CLK = 4,
+	GENPLL_CH5_ASIU_CAN_CLK   = 5
+};
+
+/*
+ * Channels for Oscillator dervived clocks are values used to determine
+ * which clock to enable/disable from the top clock gating control.
+ */
+enum cygnus_osc_derived_clk_chan {
+	OSC_DERIVED_CH0_KEYPAD_CLK = 0,
+	OSC_DERIVED_CH1_ADC_CLK    = 1,
+	OSC_DERIVED_CH2_PWM_CLK    = 2,
+};
+
+enum cygnus_mipi_pll_clk_chan {
+	MIPI_PLL_CH0_MIPI_PHY_CLK    = 0,
+	MIPI_PLL_CH1_LCD_CLK         = 1,
+	MIPI_PLL_CH2_3D_GRAPHICS_CLK = 2,
+};
+
+/* Order of registers defined in DT. */
+enum cygnus_clk_dt_regs {
+	CYGNUS_CLK_BASE_REG = 0,
+	CYGNUS_CLK_GATE_CTRL_REG,
+	CYGNUS_PLL_CTRL_REG
+};
+
+enum cygnus_top_clk_gating_ctrl_offsets {
+	GFX_CLK_GATE_EN = 0,
+	AUD_CLK_GATE_EN,
+	CAM_CLK_GATE_EN,
+	MIPI_DSI_CLK_GATE_EN,
+	LCD_CLK_GATE_EN,
+	D1W_CLK_GATE_EN,
+	CAN_CLK_GATE_EN,
+	KEYPAD_CLK_GATE_EN,
+	SMARTCARD_CLK_GATE_EN,
+	ADC_CLK_GATE_EN,
+	CRYPTO_CLK_GATE_EN
+};
+
+/*
+ * Enable clocks controlled through the top clock gating control.
+ *
+ * @param enable true = enable clock, false = disable clock
+ */
+static void cygnus_clkgate_enable_disable(void __iomem *clkgate_reg,
+	enum cygnus_top_clk_gating_ctrl_offsets offset, bool enable)
+{
+	u32 val = readl(clkgate_reg);
+
+	/* Enable or disable the clock. */
+	if (enable)
+		val |= 1 << offset;
+	else
+		val &= ~(1 << offset);
+
+	writel(val, clkgate_reg);
+}
+
+/*
+ * Powers on/off the MIPI GENPLL using CRMU_PLL_AON_CTRL register.
+ *
+ * @param power_on true to power on PLL, false to power off
+ */
+static void cygnus_mipi_genpll_power_on_off(void __iomem *pll_ctrl_reg,
+	bool power_on)
+{
+	u32 val;
+	u32 pll_ldo_on = ((1 << ASIU_MIPI_GENPLL_PWRON_SHIFT) |
+		(1 << ASIU_MIPI_GENPLL_PWRON_PLL_SHIFT) |
+		(1 << ASIU_MIPI_GENPLL_PWRON_BG_SHIFT)  |
+		(1 << ASIU_MIPI_GENPLL_PWRON_LDO_SHIFT));
+
+	val = readl(pll_ctrl_reg);
+
+	/*
+	 * Set PLL on/off. Set input isolation mode to 1 when disabled, 0 when
+	 * enabled.
+	 */
+	if (power_on) {
+		val |= pll_ldo_on;
+		val &= ~(1 << ASIU_MIPI_GENPLL_ISO_IN_SHIFT);
+	} else {
+		val &= ~pll_ldo_on;
+		val |= 1 << ASIU_MIPI_GENPLL_ISO_IN_SHIFT;
+	}
+
+	writel(val, pll_ctrl_reg);
+}
+
+/*
+ * Powers on/off the audio PLL using CRMU_PLL_AON_CTRL register.
+ *
+ * @param power_on true to power on PLL, false to power off
+ */
+static void cygnus_audio_genpll_power_on_off(void __iomem *pll_ctrl_reg,
+	bool power_on)
+{
+	u32 val;
+	u32 pll_ldo_on = ((1 << ASIU_AUDIO_GENPLL_PWRON_PLL_SHIFT) |
+		(1 << ASIU_AUDIO_GENPLL_PWRON_BG_SHIFT) |
+		(1 << ASIU_AUDIO_GENPLL_PWRON_LDO_SHIFT));
+
+	val = readl(pll_ctrl_reg);
+
+	/*
+	 * Set PLL on/off. Set input isolation mode to 1 when disabled, 0 when
+	 * enabled.
+	 */
+	if (power_on) {
+		val |= pll_ldo_on;
+		val &= ~(1 << ASIU_AUDIO_GENPLL_ISO_IN);
+	} else {
+		val &= ~pll_ldo_on;
+		val |= 1 << ASIU_AUDIO_GENPLL_ISO_IN;
+	}
+
+	writel(val, pll_ctrl_reg);
+}
+
+/*
+ * Get PLL running status and calculate output frequency
+ */
+static unsigned long cygnus_lcpll_status(struct cygnus_clk *clk,
+	unsigned long parent_rate)
+{
+	u32 reg;
+	unsigned pdiv, ndiv;
+
+	/* read status register */
+	reg = readl(clk->regs_base + CRU_LCPLL_STATUS_OFFSET);
+
+	/* Must be locked for proper PLL operation. */
+	if ((reg & (1 << LCPLL_STATUS_LOCK_SHIFT)) == 0) {
+		clk->rate = 0;
+		return -EIO;
+	}
+
+	/*
+	 * Calculate PLL frequency based on LCPLL divider values:
+	 *	 pdiv = LCPLL pre-divider ratio
+	 *   ndiv = LCPLL feedback divider
+	 *
+	 * The frequency is calculated by:
+	 *   ndiv * (parent clock rate / pdiv)
+	 */
+
+	reg = readl(clk->regs_base + CRU_LCPLL_CONTROL1_OFFSET);
+
+	/* feedback divider integer and fraction parts */
+	pdiv = (reg >> LCPLL0_PDIV_SHIFT) & LCPLL0_PDIV_MASK;
+	ndiv = (reg >> LCPLL0_NDIV_SHIFT) & LCPLL0_NDIV_MASK;
+
+	if (pdiv == 0)
+		return -EIO;
+
+	clk->rate = ndiv * (parent_rate / pdiv);
+
+	return clk->rate;
+}
+
+static unsigned long cygnus_lcpll_clk_recalc_rate(struct clk_hw *hwclk,
+	unsigned long parent_rate)
+{
+	struct cygnus_clk *bcm_clk = to_cygnus_clk(hwclk);
+
+	return cygnus_lcpll_status(bcm_clk, parent_rate);
+}
+
+static const struct clk_ops cygnus_lcpll_ops = {
+	.recalc_rate = cygnus_lcpll_clk_recalc_rate,
+};
+
+static int cygnus_lcpll_chan_status(struct cygnus_clk *clk,
+	unsigned long parent_rate)
+{
+	void * __iomem base;
+	u32 reg;
+	unsigned enable;
+	unsigned mdiv;
+	int offset = 0;
+	int shift = 0;
+
+	/* Register address is only stored in PLL structure */
+	base = clk->regs_base;
+	BUG_ON(base == NULL);
+
+	/* enable bit is in enableb_ch[] inversed */
+	enable = ((readl(base + LCPLL0_CONTROL0_OFFSET) >>
+		LCPLL_ENABLEB_CH_SHIFT) & LCPLL_ENABLEB_CH_MASK) ^
+		LCPLL_ENABLEB_CH_MASK;
+
+	if ((enable & (1 << clk->chan)) == 0) {
+		clk->rate = 0;
+		return -EIO;
+	}
+
+	/* MDIV for the 6 channels is spread over two registers. */
+	switch (clk->chan) {
+	case LCPLL_CH0_PCIE_PHY_REF_CLK:
+		offset = LCPLL0_CONTROL2_OFFSET; shift = 0;
+		break;
+
+	case LCPLL_CH1_DDR_CLK:
+		offset = LCPLL0_CONTROL2_OFFSET; shift = 10;
+		break;
+
+	case LCPLL_CH2_SDIO_CLK:
+		offset = LCPLL0_CONTROL2_OFFSET; shift = 20;
+		break;
+
+	case LCPLL_CH3_USB_PHY_REF_CLK:
+		offset = LCPLL0_CONTROL3_OFFSET; shift = 0;
+		break;
+
+	case LCPLL_CH4_ASIU_SMART_CARD_CLK:
+		offset = LCPLL0_CONTROL3_OFFSET; shift = 10;
+		break;
+
+	case LCPLL_CH5:
+		offset = LCPLL0_CONTROL3_OFFSET; shift = 20;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	/* Read MDIV for requested channel. */
+	reg = readl(base + offset);
+	mdiv = (reg >> shift) & LCPLL_MDIV_MASK;
+
+	/* when divisor is 0, it behaves as max+1 */
+	if (mdiv == 0)
+		mdiv = 256;
+
+	clk->rate = parent_rate / mdiv;
+
+	pr_debug("LCPLL[%d] mdiv=%u Prate=%lu rate=%lu\n",
+		clk->chan, mdiv, parent_rate, clk->rate);
+
+	return clk->rate;
+}
+
+static unsigned long cygnus_lcpll_chan_recalc_rate(struct clk_hw *hwclk,
+	unsigned long parent_rate)
+{
+	struct cygnus_clk *bcm_clk = to_cygnus_clk(hwclk);
+
+	return cygnus_lcpll_chan_status(bcm_clk, parent_rate);
+}
+
+static const struct clk_ops cygnus_lcpll_chan_ops = {
+	.recalc_rate = cygnus_lcpll_chan_recalc_rate,
+};
+
+/*
+ * Get PLL running status and calculate output frequency
+ */
+static unsigned long cygnus_genpll_status(struct cygnus_clk *clk,
+	unsigned long parent_rate)
+{
+	u32 reg;
+	unsigned pdiv;
+	unsigned ndiv_int;
+	unsigned ndiv_frac;
+
+	/* Read PLL status register. It must be locked. */
+	reg = readl(clk->regs_base + GENPLL_STATUS_OFFSET);
+	if ((reg & (1 << GENPLL_STATUS_LOCK_SHIFT)) == 0) {
+		clk->rate = 0;
+		return -EIO;
+	}
+
+	/* Calculate PLL frequency */
+
+	/* Get PLL feedback divider values. */
+	reg = readl(clk->regs_base + GENPLL_CONTROL4_OFFSET);
+
+	/* feedback divider integer and fraction parts */
+	ndiv_int = reg >> GENPLL_CONTROL4_NDIV_INT_SHIFT;
+	ndiv_frac = reg & GENPLL_CONTROL4_NDIV_INT_MASK;
+	ndiv_int += ndiv_frac / NDIV_FRAC_DIVISOR;
+
+	/* Get pdiv - first 4 bits. */
+	reg = readl(clk->regs_base + GENPLL_CONTROL5_OFFSET);
+	pdiv = reg & GENPLL_CONTROL5_PDIV_MASK;
+	if (pdiv == 0)
+		return -EIO;
+
+	clk->rate = (parent_rate / pdiv) * ndiv_int;
+
+	return clk->rate;
+}
+
+static unsigned long cygnus_genpll_recalc_rate(struct clk_hw *hwclk,
+	unsigned long parent_rate)
+{
+	struct cygnus_clk *bcm_clk = to_cygnus_clk(hwclk);
+
+	return cygnus_genpll_status(bcm_clk, parent_rate);
+}
+
+static const struct clk_ops cygnus_genpll_ops = {
+	.recalc_rate = cygnus_genpll_recalc_rate,
+};
+
+/*
+ * Calculates clock rate of the GENPLL channel requested. The clock rate is
+ * calculated as: the configured clock rate
+ *     Parent clock rate / mdiv
+ */
+static unsigned long cygnus_genpll_chan_get_rate(struct cygnus_clk *clk,
+	unsigned long parent_rate, int enableb_ch_shift)
+{
+	u32 reg;
+	unsigned enable;
+	unsigned mdiv;
+	unsigned offset = 0;
+	unsigned shift = 0;
+
+	/*
+	 * Read ENABLEB_CH to determine which channels are enabled. The enable
+	 * bits are inversed: 0 = channel enabled, 1 = channel disabled.
+	 */
+	reg = readl(clk->regs_base + GENPLL_CONTROL1_OFFSET);
+	enable = ((reg >> enableb_ch_shift) &
+		GENPLL_ENABLEB_CH_MASK) ^ GENPLL_ENABLEB_CH_MASK;
+
+	/* If channel is disabled the rate is 0. */
+	if ((enable & (1 << clk->chan)) == 0) {
+		clk->rate = 0;
+		return -EIO;
+	}
+
+	/* MDIV for the 6 channels is spread over two registers. */
+	switch (clk->chan) {
+	case 0:
+		offset = GENPLL_CONTROL8_OFFSET; shift = 0;
+		break;
+
+	case 1:
+		offset = GENPLL_CONTROL8_OFFSET; shift = 10;
+		break;
+
+	case 2:
+		offset = GENPLL_CONTROL8_OFFSET; shift = 20;
+		break;
+
+	case 3:
+		offset = GENPLL_CONTROL9_OFFSET; shift = 0;
+		break;
+
+	case 4:
+		offset = GENPLL_CONTROL9_OFFSET; shift = 10;
+		break;
+
+	case 5:
+		offset = GENPLL_CONTROL9_OFFSET; shift = 20;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	/* Read MDIV (post divider ratio) for requested channel. */
+	reg = readl(clk->regs_base + offset);
+	mdiv = (reg >> shift) & GENPLL_MDIV_MASK;
+
+	/* When divisor is 0, it behaves as max+1. */
+	if (mdiv == 0)
+		mdiv = 256;
+
+	clk->rate = parent_rate / mdiv;
+
+	pr_debug("GENPLL[%d] mdiv=%u parent rate=%lu rate=%lu\n",
+		clk->chan, mdiv, parent_rate, clk->rate);
+
+	return clk->rate;
+}
+
+/*
+ * Powers on the audio PLL for the audio channel from the PLL. No other
+ * GENPLL channels require powering on.
+ */
+static int cygnus_genpll_chan_prepare(struct clk_hw *hwclk)
+{
+	struct cygnus_clk *clk = to_cygnus_clk(hwclk);
+	struct clk *parent_clk = clk_get_parent(hwclk->clk);
+	struct cygnus_clk *cyg_parent_clk =
+		to_cygnus_clk(__clk_get_hw(parent_clk));
+
+	if (WARN_ON(!cyg_parent_clk->pll_ctrl_reg))
+		return -EIO;
+
+	if (clk->chan == GENPLL_CH4_ASIU_AUDIO_CLK) {
+		pr_debug("GENPLL[%d]: Powering on audio PLL/LDO\n", clk->chan);
+		cygnus_audio_genpll_power_on_off(
+			cyg_parent_clk->pll_ctrl_reg, true);
+	}
+
+	return 0;
+}
+
+/*
+ * Powers off the audio PLL for the audio channel from the PLL. No other
+ * GENPLL channels require powering off.
+ */
+static void cygnus_genpll_chan_unprepare(struct clk_hw *hwclk)
+{
+	struct cygnus_clk *clk = to_cygnus_clk(hwclk);
+	struct clk *parent_clk = clk_get_parent(hwclk->clk);
+	struct cygnus_clk *cyg_parent_clk =
+		to_cygnus_clk(__clk_get_hw(parent_clk));
+
+	if (WARN_ON(!cyg_parent_clk->pll_ctrl_reg))
+		return;
+
+	if (clk->chan == GENPLL_CH4_ASIU_AUDIO_CLK) {
+		pr_debug("GENPLL[%d]: Powering down audio PLL and LDO\n",
+			clk->chan);
+		cygnus_audio_genpll_power_on_off(cyg_parent_clk->pll_ctrl_reg,
+			false);
+	}
+}
+
+static unsigned long cygnus_genpll_chan_recalc_rate(struct clk_hw *hwclk,
+	unsigned long parent_rate)
+{
+	struct cygnus_clk *bcm_clk = to_cygnus_clk(hwclk);
+
+	return cygnus_genpll_chan_get_rate(bcm_clk, parent_rate,
+		GENPLL_ENABLEB_CH_SHIFT);
+}
+
+/*
+ * Enables GENPLL channels. The only PLL channel that is controlled through
+ * the top clock gating control is the audio clock which requires enabling.
+ *
+ * Individual channels aren't enabled/disabled on the PLL because they are
+ * enabled by default and drivers don't always refer to them, meaning the
+ * clock framework would disable them. This can be added later when power
+ * saving is a concern.
+ */
+static int cygnus_genpll_chan_enable(struct clk_hw *hwclk)
+{
+	struct cygnus_clk *clk = to_cygnus_clk(hwclk);
+	struct clk *parent_clk = clk_get_parent(hwclk->clk);
+	struct cygnus_clk *cyg_parent_clk =
+		to_cygnus_clk(__clk_get_hw(parent_clk));
+	int parent_rate;
+
+	if (WARN_ON(!cyg_parent_clk->clock_gate_ctrl_reg))
+		return -EIO;
+
+	pr_debug("Enable GENPLL chan %d\n", clk->chan);
+
+	if (clk->chan == GENPLL_CH4_ASIU_AUDIO_CLK) {
+		cygnus_clkgate_enable_disable(
+			cyg_parent_clk->clock_gate_ctrl_reg,
+			AUD_CLK_GATE_EN, true);
+
+		/* Ensure parent's clock rate is calculated. */
+		parent_rate = clk_get_rate(parent_clk);
+		if (WARN_ON(!parent_rate))
+			return -EIO;
+	}
+
+	return 0;
+}
+
+static void cygnus_genpll_chan_disable(struct clk_hw *hwclk)
+{
+	struct cygnus_clk *clk = to_cygnus_clk(hwclk);
+	struct clk *parent_clk = clk_get_parent(hwclk->clk);
+	struct cygnus_clk *cyg_parent_clk =
+		to_cygnus_clk(__clk_get_hw(parent_clk));
+
+	if (WARN_ON(!cyg_parent_clk->clock_gate_ctrl_reg))
+		return;
+
+	pr_debug("GENPLL: disable chan %d\n", clk->chan);
+
+	/* Enable audio clock. */
+	if (clk->chan == GENPLL_CH4_ASIU_AUDIO_CLK)
+		cygnus_clkgate_enable_disable(
+			cyg_parent_clk->clock_gate_ctrl_reg,
+			AUD_CLK_GATE_EN, false);
+}
+
+static const struct clk_ops cygnus_genpll_chan_ops = {
+	.prepare = cygnus_genpll_chan_prepare,
+	.unprepare = cygnus_genpll_chan_unprepare,
+	.enable = cygnus_genpll_chan_enable,
+	.disable = cygnus_genpll_chan_disable,
+	.recalc_rate = cygnus_genpll_chan_recalc_rate,
+};
+
+static __init struct clk *cygnus_clock_init(struct device_node *node,
+	const struct clk_ops *ops)
+{
+	u32 channel = 0;
+	struct clk *clk;
+	struct cygnus_clk *cygnus_clk;
+	const char *clk_name = node->name;
+	const char *parent_name;
+	struct clk_init_data init;
+	int rc;
+
+	pr_debug("Clock name %s\n", node->name);
+
+	cygnus_clk = kzalloc(sizeof(*cygnus_clk), GFP_KERNEL);
+	if (WARN_ON(!cygnus_clk))
+		return NULL;
+
+	cygnus_clk->state = CLK_DISABLED;
+
+	/* Read base address from device tree and map to virtual address. */
+	cygnus_clk->regs_base = of_iomap(node, CYGNUS_CLK_BASE_REG);
+	if (WARN_ON(!cygnus_clk->regs_base))
+		goto err_alloc;
+
+	/* Read optional base addresses for PLL control and clock gating. */
+	cygnus_clk->clock_gate_ctrl_reg = of_iomap(node,
+		CYGNUS_CLK_GATE_CTRL_REG);
+	cygnus_clk->pll_ctrl_reg = of_iomap(node, CYGNUS_PLL_CTRL_REG);
+
+	of_property_read_u32(node, "channel", &channel);
+	cygnus_clk->chan = channel;
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	/*
+	 * Internal divider is optional and used for PLL derived clocks with
+	 * hardcoded dividers.
+	 */
+	cygnus_clk->internal_div = CLK_RATE_NO_DIV;
+	of_property_read_u32(node, "div", &cygnus_clk->internal_div);
+
+	init.name = clk_name;
+	init.ops = ops;
+	init.flags = CLK_GET_RATE_NOCACHE;
+	parent_name = of_clk_get_parent_name(node, 0);
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	cygnus_clk->hw.init = &init;
+
+	clk = clk_register(NULL, &cygnus_clk->hw);
+	if (WARN_ON(IS_ERR(clk)))
+		goto err_unmap;
+
+	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+	if (WARN_ON(IS_ERR_VALUE(rc)))
+		goto err_unregister;
+
+	rc = clk_register_clkdev(clk, clk_name, NULL);
+	if (WARN_ON(IS_ERR_VALUE(rc)))
+		goto err_provider;
+
+	return clk;
+
+err_provider:
+	of_clk_del_provider(node);
+
+err_unregister:
+	clk_unregister(clk);
+
+err_unmap:
+	iounmap(cygnus_clk->regs_base);
+	iounmap(cygnus_clk->clock_gate_ctrl_reg);
+	iounmap(cygnus_clk->pll_ctrl_reg);
+
+err_alloc:
+	kfree(cygnus_clk);
+
+	return NULL;
+}
+
+static void __init cygnus_lcpll_init(struct device_node *node)
+{
+	cygnus_clock_init(node, &cygnus_lcpll_ops);
+}
+CLK_OF_DECLARE(cygnus_lcpll, "brcm,cygnus-lcpll-clk", cygnus_lcpll_init);
+
+static void __init cygnus_genpll_init(struct device_node *node)
+{
+	cygnus_clock_init(node, &cygnus_genpll_ops);
+}
+CLK_OF_DECLARE(cygnus_genpll, "brcm,cygnus-genpll-clk", cygnus_genpll_init);
+
+static void __init cygnus_lcpll_ch_init(struct device_node *node)
+{
+	cygnus_clock_init(node, &cygnus_lcpll_chan_ops);
+}
+CLK_OF_DECLARE(cygnus_lcpll_ch, "brcm,cygnus-lcpll-ch", cygnus_lcpll_ch_init);
+
+static void __init cygnus_genpll_ch_init(struct device_node *node)
+{
+	cygnus_clock_init(node, &cygnus_genpll_chan_ops);
+}
+CLK_OF_DECLARE(cygnus_genpll_ch, "brcm,cygnus-genpll-ch",
+	cygnus_genpll_ch_init);
+
+/*
+ * Some clocks on Cygnus are derived from the oscillator directly without
+ * going through either the GENPLL or LCPLL. These clocks have specific
+ * registers for their dividers. The clocks included are: keypad, ADC, PWM.
+ */
+
+#define ASIU_CLK_DIV_ENABLE_SHIFT  31
+#define ASIU_CLK_DIV_ENABLE_MASK   0x1
+#define ASIU_CLK_DIV_HIGH_SHIFT    16
+#define ASIU_CLK_DIV_HIGH_MASK     0x3ff
+#define ASIU_CLK_DIV_LOW_SHIFT     0
+#define ASIU_CLK_DIV_LOW_MASK      0x3ff
+
+/*
+ * Calculate clock frequency for clocks derived from oscillator.
+ *
+ * @return The clock rate in Hz
+ */
+static int cygnus_osc_derived_clk_get_rate(struct cygnus_clk *clk,
+	unsigned long parent_rate)
+{
+	int reg_val;
+	int enabled;
+	int clk_div_high;
+	int clk_div_low;
+	unsigned long rate = 0;
+
+	reg_val = readl(clk->regs_base);
+
+	/* Ensure clock is enabled. */
+	enabled = (reg_val >> ASIU_CLK_DIV_ENABLE_SHIFT) &
+		ASIU_CLK_DIV_ENABLE_MASK;
+	if (!enabled)
+		return rate;
+
+	clk_div_high = (reg_val >> ASIU_CLK_DIV_HIGH_SHIFT) &
+		ASIU_CLK_DIV_HIGH_MASK;
+	clk_div_high += 1;
+
+	clk_div_low = (reg_val >> ASIU_CLK_DIV_LOW_SHIFT) &
+		ASIU_CLK_DIV_LOW_MASK;
+	clk_div_low += 1;
+
+	/*
+	 * Rate calculated as:
+	 *   (oscillator rate) / ((clk high + 1) + (clk_low + 1))
+	 */
+	rate = parent_rate / (clk_div_high + clk_div_low);
+
+	pr_debug("Osc derived clk: Prate=%lu div_high=%d div_low=%d rate=%lu\n",
+		parent_rate, clk_div_high, clk_div_low, rate);
+
+	return rate;
+}
+
+static unsigned long cygnus_osc_derived_clk_recalc_rate(struct clk_hw *hwclk,
+	unsigned long parent_rate)
+{
+	struct cygnus_clk *bcm_clk = to_cygnus_clk(hwclk);
+
+	return cygnus_osc_derived_clk_get_rate(bcm_clk, parent_rate);
+}
+
+/*
+ * Enables the top clock gating control for clocks that require it.
+ */
+static int cygnus_osc_derived_clk_enable(struct clk_hw *hwclk)
+{
+	struct cygnus_clk *clk = to_cygnus_clk(hwclk);
+	struct clk *parent_clk = clk_get_parent(hwclk->clk);
+	int parent_rate;
+	u32 val;
+
+	if (WARN_ON(!clk->clock_gate_ctrl_reg))
+		return 0;
+
+	pr_debug("OSC derived clk enable chan %d\n", clk->chan);
+
+	/* Enable top clock gating control if necessary. */
+	if (clk->chan == OSC_DERIVED_CH0_KEYPAD_CLK)
+		cygnus_clkgate_enable_disable(clk->clock_gate_ctrl_reg,
+			KEYPAD_CLK_GATE_EN, true);
+	else if (clk->chan == OSC_DERIVED_CH1_ADC_CLK)
+		cygnus_clkgate_enable_disable(clk->clock_gate_ctrl_reg,
+			ADC_CLK_GATE_EN, true);
+
+	/* Set and enable divider if specified. */
+	if (clk->internal_div != CLK_RATE_NO_DIV) {
+		val = (1 << ASIU_CLK_DIV_ENABLE_SHIFT) |
+			((clk->internal_div & ASIU_CLK_DIV_HIGH_MASK) <<
+			ASIU_CLK_DIV_HIGH_SHIFT) |
+			((clk->internal_div & ASIU_CLK_DIV_LOW_MASK) <<
+			ASIU_CLK_DIV_LOW_SHIFT);
+		writel(val, clk->regs_base);
+	}
+
+	/* Ensure parent's clock rate is calculated. */
+	parent_rate = clk_get_rate(parent_clk);
+	if (WARN_ON(!parent_rate))
+		return -EIO;
+
+	return 0;
+}
+
+/*
+ * Disables top clock gating control for clocks that were enabled.
+ */
+static void cygnus_osc_derived_clk_disable(struct clk_hw *hwclk)
+{
+	struct cygnus_clk *clk = to_cygnus_clk(hwclk);
+
+	if (WARN_ON(!clk->clock_gate_ctrl_reg))
+		return;
+
+	pr_debug("OSC derived clk disable chan %d\n", clk->chan);
+
+	/* Disable top clock gating control if necessary. */
+	if (clk->chan == OSC_DERIVED_CH0_KEYPAD_CLK)
+		cygnus_clkgate_enable_disable(clk->clock_gate_ctrl_reg,
+			KEYPAD_CLK_GATE_EN, false);
+	else if (clk->chan == OSC_DERIVED_CH1_ADC_CLK)
+		cygnus_clkgate_enable_disable(clk->clock_gate_ctrl_reg,
+			ADC_CLK_GATE_EN, false);
+}
+
+static const struct clk_ops cygnus_osc_derived_clk_ops = {
+	.enable = cygnus_osc_derived_clk_enable,
+	.disable = cygnus_osc_derived_clk_disable,
+	.recalc_rate = cygnus_osc_derived_clk_recalc_rate,
+};
+
+static void __init cygnus_osc_derived_init(struct device_node *node)
+{
+	cygnus_clock_init(node, &cygnus_osc_derived_clk_ops);
+}
+
+CLK_OF_DECLARE(cygnus_osc_derived, "brcm,cygnus-osc-derived",
+	cygnus_osc_derived_init);
+
+/*
+ * Some clocks are derived from a PLL. The dividers are internal and can't
+ * be read from a register. If the parent clock rate changes then the derived
+ * clock rates scale accordingly.
+ */
+
+ /*
+  * Calculate clock frequency for clocks derived from oscillator.
+  * Rate calculated as:  parent rate / internal divider
+  * The internal divider must be specified in DT.
+  *
+  * @return The clock rate in Hz.
+  */
+static unsigned long cygnus_pll_derived_clk_get_rate(struct cygnus_clk *clk,
+	unsigned long parent_rate)
+{
+	unsigned long rate = parent_rate / clk->internal_div;
+
+	pr_debug("PLL derived clk: Prate=%lu rate=%lu\n", parent_rate, rate);
+
+	return rate;
+}
+
+static unsigned long cygnus_pll_derived_clk_recalc_rate(struct clk_hw *hwclk,
+	unsigned long parent_rate)
+{
+	struct cygnus_clk *bcm_clk = to_cygnus_clk(hwclk);
+
+	return cygnus_pll_derived_clk_get_rate(bcm_clk, parent_rate);
+}
+
+static const struct clk_ops cygnus_pll_derived_clk_ops = {
+	.recalc_rate = cygnus_pll_derived_clk_recalc_rate,
+};
+
+static void __init cygnus_pll_derived_init(struct device_node *node)
+{
+	cygnus_clock_init(node, &cygnus_pll_derived_clk_ops);
+}
+
+CLK_OF_DECLARE(cygnus_pll_derived, "brcm,cygnus-pll-derived",
+	cygnus_pll_derived_init);
+
+/*
+ * MIPI DSI GENPLL
+ */
+
+/*
+ * Get PLL running status and calculate output frequency.
+ */
+static unsigned long cygnus_mipipll_get_rate(struct cygnus_clk *clk,
+	unsigned long parent_rate)
+{
+	u32 reg;
+	u32 rate;
+	u32 pdiv;
+	u32 ndiv_int;
+	u32 ndiv_frac;
+	int pll_locked;
+
+	/* Read lock field from PLL status register. It must be unlocked. */
+	reg = readl(clk->regs_base + GENPLL_STATUS_OFFSET);
+
+	pll_locked = (reg >> GENPLL_STATUS_LOCK_SHIFT) &
+		GENPLL_STATUS_LOCK_MASK;
+	if (pll_locked) {
+		clk->rate = 0;
+		return -EIO;
+	}
+	/*
+	 * Calculate PLL frequency:
+	 *   PLL freq = ((crystal clock / pdiv) * ndiv ) / mdiv
+	 */
+
+	/* Get PLL feedback divider values. */
+	reg = readl(clk->regs_base + GENPLL_CONTROL4_OFFSET);
+
+	/* Feedback divider integer and fractional parts. */
+	ndiv_int = (reg >> GENPLL_CONTROL4_NDIV_INT_SHIFT) &
+		GENPLL_CONTROL4_NDIV_INT_MASK;
+	ndiv_frac = (reg >> GENPLL_CONTROL4_NDIV_FRAC_SHIFT) &
+		GENPLL_CONTROL4_NDIV_FRAC_MASK;
+	ndiv_int += ndiv_frac / NDIV_FRAC_DIVISOR;
+
+	/* Get pdiv. */
+	reg = readl(clk->regs_base + GENPLL_CONTROL5_OFFSET);
+	pdiv = (reg >> GENPLL_CONTROL5_PDIV_SHIFT) &
+		GENPLL_CONTROL5_PDIV_MASK;
+
+	/* If pdiv is 0, divide by 0.5 - doubler. */
+	if (pdiv == 0)
+		rate = parent_rate * 2;
+	else
+		rate = parent_rate / pdiv;
+
+	clk->rate = rate * ndiv_int;
+
+	pr_debug("[MIPI PLL] parent rate=%lu, ndiv int=%d, pdiv=%d, rate=%lu\n",
+	    parent_rate, ndiv_int, pdiv, clk->rate);
+
+	return clk->rate;
+}
+
+/*
+ * Powers on the necessary PLL's and LDO for MIPI GEN PLL.
+ */
+static int cygnus_mipipll_prepare(struct clk_hw *hwclk)
+{
+	struct cygnus_clk *clk = to_cygnus_clk(hwclk);
+
+	if (WARN_ON(!clk->pll_ctrl_reg))
+		return -EIO;
+
+	pr_debug("Powering up MIPI PLL and LDO\n");
+
+	/* Power on the PLL. */
+	cygnus_mipi_genpll_power_on_off(clk->pll_ctrl_reg, true);
+
+	clk->state = CLK_PREPARED;
+
+	return 0;
+}
+
+/*
+ * Powers off the PLL's and LDO for MIPI GEN PLL.
+ */
+static void cygnus_mipipll_unprepare(struct clk_hw *hwclk)
+{
+	struct cygnus_clk *clk = to_cygnus_clk(hwclk);
+
+	if (WARN_ON(!clk->pll_ctrl_reg))
+		return;
+
+	pr_debug("Powering down MIPI PLL and LDO\n");
+
+	/* Power off the PLL. */
+	cygnus_mipi_genpll_power_on_off(clk->pll_ctrl_reg, false);
+
+	clk->state = CLK_DISABLED;
+}
+
+static unsigned long cygnus_mipipll_recalc_rate(struct clk_hw *hwclk,
+	unsigned long parent_rate)
+{
+	struct cygnus_clk *bcm_clk = to_cygnus_clk(hwclk);
+
+	if (bcm_clk->state != CLK_ENABLED)
+		return 0;
+
+	return cygnus_mipipll_get_rate(bcm_clk, parent_rate);
+}
+
+/*
+ * Enables the MIPI DSI clock gate through the top clock gating control.
+ */
+static int cygnus_mipipll_enable(struct clk_hw *hwclk)
+{
+	struct cygnus_clk *clk = to_cygnus_clk(hwclk);
+
+	if (WARN_ON(!clk->clock_gate_ctrl_reg))
+		return -EIO;
+
+	pr_debug("Enable MIPI PLL\n");
+
+	/* Enable MIPI DSI clock. */
+	cygnus_clkgate_enable_disable(clk->clock_gate_ctrl_reg,
+		MIPI_DSI_CLK_GATE_EN, true);
+
+	clk->state = CLK_ENABLED;
+
+	return 0;
+}
+
+/*
+ * Turns off the MIPI PLL clock.
+ */
+static void cygnus_mipipll_disable(struct clk_hw *hwclk)
+{
+	struct cygnus_clk *clk = to_cygnus_clk(hwclk);
+
+	if (WARN_ON(!clk->clock_gate_ctrl_reg))
+		return;
+
+	pr_debug("Disabling MIPI PLL and LDO\n");
+
+	/* Disable MIPI DSI clock through top clock gating control. */
+	cygnus_clkgate_enable_disable(clk->clock_gate_ctrl_reg,
+		MIPI_DSI_CLK_GATE_EN, false);
+
+	clk->state = CLK_DISABLED;
+}
+
+static const struct clk_ops cygnus_mipipll_ops = {
+	.prepare = cygnus_mipipll_prepare,
+	.unprepare = cygnus_mipipll_unprepare,
+	.enable = cygnus_mipipll_enable,
+	.disable = cygnus_mipipll_disable,
+	.recalc_rate = cygnus_mipipll_recalc_rate,
+};
+
+static void __init cygnus_mipipll_init(struct device_node *node)
+{
+	cygnus_clock_init(node, &cygnus_mipipll_ops);
+}
+CLK_OF_DECLARE(cygnus_mipipll, "brcm,cygnus-mipipll-clk", cygnus_mipipll_init);
+
+/*
+ * MIPI PLL clock channel management.
+ */
+
+/*
+ * Enables a MIPI PLL channel.
+ */
+static void mipi_pll_enable_chan(void __iomem *base, int chan, bool state)
+{
+	u32 val;
+
+	val = readl(base + GENPLL_CONTROL1_OFFSET);
+
+	/* ENABLEB_CH bit set to 0 to enable channel, 1 to disable. */
+	if (state)
+		val &= ~(1 << (chan + MIPI_DSI_GENPLL_ENABLEB_CH_SHIFT));
+	else
+		val |= (1 << (chan + MIPI_DSI_GENPLL_ENABLEB_CH_SHIFT));
+
+	writel(val, base + GENPLL_CONTROL1_OFFSET);
+}
+
+static unsigned long cygnus_mipipll_chan_recalc_rate(struct clk_hw *hwclk,
+	unsigned long parent_rate)
+{
+	struct cygnus_clk *clk = to_cygnus_clk(hwclk);
+
+	if (WARN_ON(!clk->clock_gate_ctrl_reg))
+		return 0;
+
+	if (clk->state != CLK_ENABLED)
+		return 0;
+
+	return cygnus_genpll_chan_get_rate(clk, parent_rate,
+		MIPI_DSI_GENPLL_ENABLEB_CH_SHIFT);
+}
+
+/*
+ * Enables the PLL channel and the top clock gating control for clocks that
+ * are controlled through it.
+ */
+static int cygnus_mipipll_chan_enable(struct clk_hw *hwclk)
+{
+	struct cygnus_clk *clk = to_cygnus_clk(hwclk);
+	struct clk *parent_clk = clk_get_parent(hwclk->clk);
+	int parent_rate;
+
+	if (WARN_ON(!clk->clock_gate_ctrl_reg))
+		return -EIO;
+
+	pr_debug("Enable MIPI PLL chan %d\n", clk->chan);
+
+	/*
+	 * Some MIPI PLL channels have to be enabled through the top clock
+	 * gating ctrl. Add support for other channels here.
+	 */
+	if (clk->chan == MIPI_PLL_CH1_LCD_CLK) {
+		cygnus_clkgate_enable_disable(clk->clock_gate_ctrl_reg,
+			LCD_CLK_GATE_EN, true);
+	}
+
+	/* Enable the PLL channel. */
+	mipi_pll_enable_chan(clk->regs_base, clk->chan, true);
+
+	clk->state = CLK_ENABLED;
+
+	/* Ensure parent's clock rate is calculated. */
+	parent_rate = clk_get_rate(parent_clk);
+	if (WARN_ON(!parent_rate))
+		return -EIO;
+
+	return 0;
+}
+
+/*
+ * Disables the PLL channel. Some channels also have to be shut down through
+ * the top clock gating control.
+ */
+static void cygnus_mipipll_chan_disable(struct clk_hw *hwclk)
+{
+	struct cygnus_clk *clk = to_cygnus_clk(hwclk);
+
+	if (WARN_ON(!clk->clock_gate_ctrl_reg))
+		return;
+
+	pr_debug("Disable MIPI PLL chan %d\n", clk->chan);
+
+	/* Disable LCD clock through top clock gating control. */
+	if (clk->chan == MIPI_PLL_CH1_LCD_CLK) {
+		cygnus_clkgate_enable_disable(clk->clock_gate_ctrl_reg,
+			LCD_CLK_GATE_EN, false);
+	}
+
+	/* Disable the PLL channel. */
+	mipi_pll_enable_chan(clk->regs_base, clk->chan, false);
+
+	clk->state = CLK_DISABLED;
+}
+
+static const struct clk_ops cygnus_mipipll_chan_ops = {
+	.enable = cygnus_mipipll_chan_enable,
+	.disable = cygnus_mipipll_chan_disable,
+	.recalc_rate = cygnus_mipipll_chan_recalc_rate,
+};
+
+static void __init cygnus_mipipll_ch_init(struct device_node *node)
+{
+	cygnus_clock_init(node, &cygnus_mipipll_chan_ops);
+}
+
+CLK_OF_DECLARE(cygnus_mipipll_ch, "brcm,cygnus-mipipll-ch",
+	cygnus_mipipll_ch_init);
diff --git a/drivers/clk/bcm/clk-iproc.c b/drivers/clk/bcm/clk-iproc.c
new file mode 100644
index 0000000..aca4851
--- /dev/null
+++ b/drivers/clk/bcm/clk-iproc.c
@@ -0,0 +1,451 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/clkdev.h>
+#include <linux/of_address.h>
+
+#define IPROC_CLK_POLICY_FREQ_OFFSET    0x008
+#define IPROC_CLK_POLICY0_MSK_OFFSET    0x010
+#define IPROC_CLK_APB_SW_DIV_OFFSET     0xA10
+#define IPROC_CLK_PLL_ARMA_OFFSET       0xC00
+#define IPROC_CLK_PLL_ARMB_OFFSET       0xC04
+#define IPROC_CLK_PLL_ARMC_OFFSET       0xC08
+#define IPROC_CLK_PLL_ARMCTL5_OFFSET    0xC20
+#define IPROC_CLK_PLL_ARM_OFFSET_OFFSET 0xC24
+#define IPROC_CLK_ARM_DIV_OFFSET        0xE00
+#define IPROC_CLK_POLICY_DBG_OFFSET     0xEC0
+
+#define IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_OVERRIDE_SHIFT        4
+#define IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_MASK                  0xf
+#define IPROC_CLK_POLICY_FREQ_OFFSET_POLICY_FREQ_MASK          0xf
+#define IPROC_CLK_POLICY_FREQ_OFFSET_POLICY_FREQ_SHIFT         8
+#define IPROC_CLK_POLICY_DBG_OFFSET_ACT_FREQ_SHIFT             12
+#define IPROC_CLK_POLICY_DBG_OFFSET_ACT_FREQ_MASK              7
+#define IPROC_CLK_PLL_ARM_OFFSET_PLLARM_OFFSET_SW_CTL_SHIFT    29
+#define CLK_PLL_ARM_OFFSET_PLLARM_NDIV_INT_OFFSET              20
+#define CLK_PLL_ARM_OFFSET_PLLARM_NDIV_INT_MASK                0xff
+#define CLK_PLL_ARM_OFFSET_PLLARM_NDIV_FRAC_OFFSET             0xfffff
+#define CLK_PLL_ARMA_PLLARM_NDIV_INT_SHIFT                     8
+#define CLK_PLL_ARMA_PLLARM_NDIV_INT_MASK                      0x3ff
+#define CLK_PLL_ARMB_PLLARM_NDIV_FRAC_MASK                     0xfffff
+#define CLK_PLL_ARMC_PLLARM_MDIV_MASK                          0xff
+#define CLK_PLL_ARMCTL5_PLLARM_H_MDIV_MASK                     0xff
+#define CLK_PLL_ARMC_PLLARM_BYPCLK_EN_SHIFT                    8
+#define CLK_PLL_ARMA_PLLARM_PDIV_SHIFT                         24
+#define CLK_PLL_ARMA_PLLARM_PDIV_MASK                          0xf
+#define CLK_PLL_ARMA_PLLARM_LOCK_SHIFT                         28
+#define CLK_ARM_DIV_APB0_FREE_DIV_SHIFT                        8
+#define CLK_ARM_DIV_APB0_FREE_DIV_MASK                         0x7
+#define CLK_ARM_DIV_ARM_SWITCH_DIV_SHIFT                       8
+#define CLK_ARM_DIV_ARM_SWITCH_DIV_MASK                        0x3
+#define CLK_APB_SW_DIV_APB_CLK_DIV_MASK                        0x3
+
+struct brcm_clk {
+	struct clk_hw   hw;
+	void __iomem    *regs_base;
+	int             chan;
+	unsigned long   rate;
+};
+
+/* Identifies derived clocks from ARM PLL. */
+enum {
+	ARMPLL_APB0_FREE_CLK   = 0,
+	ARMPLL_ARM_SWITCH_CLK  = 1,
+	ARMPLL_ARM_APB_CLK     = 2,
+	ARMPLL_ARM_PERIPH_CLK  = 3
+};
+
+/* Frequency id's from policy0_freq field of POLICY_FREQ register. */
+enum a9pll_policy_freq {
+	PLL_CRYSTAL_CLK   = 0,
+	PLL_SYS_CLK       = 2,
+	PLL_CH0_SLOW_CLK  = 6,
+	PLL_CH1_FAST_CLK  = 7
+};
+
+#define to_brcm_clk(p) container_of(p, struct brcm_clk, hw)
+
+static int iproc_cru_arm_freq_id(void __iomem *regs_base)
+{
+	u32 reg_f, reg;
+	unsigned policy = 0;
+	unsigned fid;
+	unsigned active_freq;
+
+	/* Read policy frequency. */
+	reg_f = readl(regs_base + IPROC_CLK_POLICY_FREQ_OFFSET);
+
+	/* Check for PLL policy software override. */
+	reg = readl(regs_base + IPROC_CLK_ARM_DIV_OFFSET);
+	if (reg & (1 << IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_OVERRIDE_SHIFT))
+		policy = reg & IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_MASK;
+
+	/* Get frequency ID based on policy. */
+	fid = (reg_f >>
+		(IPROC_CLK_POLICY_FREQ_OFFSET_POLICY_FREQ_SHIFT * policy)) &
+		IPROC_CLK_POLICY_FREQ_OFFSET_POLICY_FREQ_MASK;
+
+	/* Verify freq id from debug register. */
+	reg = readl(regs_base + IPROC_CLK_POLICY_DBG_OFFSET);
+	/* Read current active frequency id. */
+	active_freq = IPROC_CLK_POLICY_DBG_OFFSET_ACT_FREQ_MASK &
+		(reg >> IPROC_CLK_POLICY_DBG_OFFSET_ACT_FREQ_SHIFT);
+
+	if (fid != active_freq) {
+		pr_debug("IPROC CRU clock frequency id override %d->%d\n",
+			fid, active_freq);
+
+		fid = active_freq;
+	}
+
+	pr_debug("Active frequency ID %d\n", fid);
+
+	return fid;
+}
+
+/*
+ * Get ndiv integer and combine with fractional part to create 64 bit
+ * value.
+ */
+static u64 a9pll_get_ndiv(struct brcm_clk *clk)
+{
+	u32 arm_offset_reg;
+	u32 pllarma_reg;
+	u32 pllarmb_reg;
+	u32 ndiv_int;
+	u32 ndiv_frac;
+	u64 ndiv;
+
+	arm_offset_reg = readl(clk->regs_base +
+		IPROC_CLK_PLL_ARM_OFFSET_OFFSET);
+
+    /*
+	 * Check if offset mode is active to determine which register to
+	 * get ndiv from.
+	 */
+	if (arm_offset_reg &
+		(1 << IPROC_CLK_PLL_ARM_OFFSET_PLLARM_OFFSET_SW_CTL_SHIFT)) {
+		/* Offset mode active. Get integer divide from offset reg. */
+		ndiv_int = (arm_offset_reg >>
+			CLK_PLL_ARM_OFFSET_PLLARM_NDIV_INT_OFFSET) &
+			CLK_PLL_ARM_OFFSET_PLLARM_NDIV_INT_MASK;
+
+		if (ndiv_int == 0)
+			ndiv_int = 256;
+
+		/* Get ndiv fractional divider. */
+		ndiv_frac = arm_offset_reg &
+			CLK_PLL_ARM_OFFSET_PLLARM_NDIV_FRAC_OFFSET;
+	} else {
+		/* Offset mode not active so read PLL ndiv from PLLARMA. */
+		pllarma_reg = readl(clk->regs_base + IPROC_CLK_PLL_ARMA_OFFSET);
+		ndiv_int = (pllarma_reg >> CLK_PLL_ARMA_PLLARM_NDIV_INT_SHIFT) &
+			CLK_PLL_ARMA_PLLARM_NDIV_INT_MASK;
+
+		if (ndiv_int == 0)
+			ndiv_int = 1024;
+
+		/* Get ndiv fractional divider. */
+		pllarmb_reg = readl(clk->regs_base + IPROC_CLK_PLL_ARMB_OFFSET);
+		ndiv_frac = pllarmb_reg & CLK_PLL_ARMB_PLLARM_NDIV_FRAC_MASK;
+	}
+
+	ndiv = ((u64) ndiv_int << 20) | ndiv_frac;
+
+	return ndiv;
+}
+
+/*
+ * Determine mdiv (post divider) based on the frequency id being used.
+ * There are 4 clocks that can be used to derive the output clock rate:
+ *    - 25 MHz crystal
+ *    - sys_clk
+ *    - channel 0 (slow clock)
+ *    - channel 1 (fast clock)
+ *
+ * If the slow clock is being used then mdiv is read from PLLARMC. If
+ * the fast clock is being used then the channel 1 mdiv is used.
+ * Otherwise there is no post divider.
+ *
+ * @return The mdiv value. -EIO if an error occurred.
+ */
+static int a9pll_get_mdiv(struct brcm_clk *clk)
+{
+	u32 mdiv;
+	u32 pllarmc_reg;
+	u32 armctl5_reg;
+	u32 freq_id;
+
+	/* Get the policy frequency. */
+	freq_id = iproc_cru_arm_freq_id(clk->regs_base);
+
+	switch (freq_id) {
+	/* There is no divider for these frequency id's. */
+	case PLL_CRYSTAL_CLK:
+	case PLL_SYS_CLK:
+		mdiv = 1;
+		break;
+
+	case PLL_CH0_SLOW_CLK: {
+	    /* Read mdiv (post-divider) from PLLARMC bits 0:7 */
+	    pllarmc_reg = readl(clk->regs_base + IPROC_CLK_PLL_ARMC_OFFSET);
+	    mdiv = pllarmc_reg & CLK_PLL_ARMC_PLLARM_MDIV_MASK;
+	    if (mdiv == 0)
+			mdiv = 256;
+		break;
+	}
+
+	case PLL_CH1_FAST_CLK: {
+		/* Post divider for channel 1 is in CTL5 (pllarm_h_mdiv). */
+		armctl5_reg = readl(clk->regs_base +
+			IPROC_CLK_PLL_ARMCTL5_OFFSET);
+	    mdiv = armctl5_reg & CLK_PLL_ARMCTL5_PLLARM_H_MDIV_MASK;
+	    if (mdiv == 0)
+			mdiv = 256;
+		break;
+	}
+
+	default:
+		return -EIO;
+	}
+
+	return mdiv;
+}
+
+/*
+ * Calculate the output frequency of the ARM PLL. The main output clock
+ * is 'arm_clk'.
+ *
+ * The frequency is calculated based on the ARM PLL divider values:
+ *	 pdiv = ARM PLL input pre-divider
+ *   ndiv = ARM PLL feedback divider
+ *   mdiv = ARM PLL post divider
+ *
+ * The frequency is calculated by:
+ *   ((ndiv * parent clock rate) / pdiv) / mdiv
+ */
+static int a9pll_status(struct brcm_clk *clk, unsigned long parent_rate)
+{
+	u32 pllarma_reg;
+	u32 pllarmc_reg;
+	u32 pdiv;
+	u32 mdiv;
+	u64 ndiv;
+	u32 arm_clk_freq;
+
+	pr_debug("a9pll_status: clk 0x%x\n", (unsigned int)clk);
+
+	BUG_ON(!clk->regs_base);
+
+	pllarma_reg = readl(clk->regs_base + IPROC_CLK_PLL_ARMA_OFFSET);
+	pllarmc_reg = readl(clk->regs_base + IPROC_CLK_PLL_ARMC_OFFSET);
+
+	/* Check if PLL is in bypass mode - input frequency to output */
+	if (pllarmc_reg & (1 << CLK_PLL_ARMC_PLLARM_BYPCLK_EN_SHIFT)) {
+		clk->rate = parent_rate;
+		return 0;
+	}
+
+	/* Check if PLL is locked. It must be unlocked. */
+	if ((pllarma_reg &
+		(1 << CLK_PLL_ARMA_PLLARM_LOCK_SHIFT)) == 0) {
+		clk->rate = 0;
+		return -EIO;
+	}
+
+	/* Read pdiv from PLLARMA. */
+	pdiv = (pllarma_reg >> CLK_PLL_ARMA_PLLARM_PDIV_SHIFT) &
+		CLK_PLL_ARMA_PLLARM_PDIV_MASK;
+	if (pdiv == 0)
+		pdiv = 16;
+
+	/* Determine ndiv. */
+	ndiv = a9pll_get_ndiv(clk);
+
+	/* Determine mdiv (post divider). */
+	mdiv = a9pll_get_mdiv(clk);
+	if (mdiv == -EIO) {
+		clk->rate = 0;
+		return -EIO;
+	}
+
+	/* Calculate clock frequency. */
+	arm_clk_freq = (ndiv * parent_rate) >> 20;
+	arm_clk_freq = (arm_clk_freq / pdiv) / mdiv;
+
+	clk->rate = arm_clk_freq;
+
+	pr_debug("ARM PLL (arm_clk) rate %lu. parent rate = %lu, ",
+		clk->rate, parent_rate);
+	pr_debug("ndiv_int = %d, pdiv = %d, mdiv = %d\n",
+		 (u32)ndiv >> 20, pdiv, mdiv);
+
+	return clk->rate;
+}
+
+static unsigned long clk_a9pll_recalc_rate(struct clk_hw *hwclk,
+	unsigned long parent_rate)
+{
+	struct brcm_clk *bcm_clk = to_brcm_clk(hwclk);
+
+	return a9pll_status(bcm_clk, parent_rate);
+}
+
+static const struct clk_ops a9pll_ops = {
+	.recalc_rate = clk_a9pll_recalc_rate,
+};
+
+/*
+ * Get status of any of the ARMPLL output channels
+ */
+static int a9pll_chan_status(struct brcm_clk *clk, unsigned long parent_rate)
+{
+	u32 reg;
+	unsigned div;
+
+	BUG_ON(!clk->regs_base);
+
+	reg = readl(clk->regs_base + IPROC_CLK_ARM_DIV_OFFSET);
+	pr_debug("Clock Div = %#x\n", reg);
+
+	switch (clk->chan) {
+	case ARMPLL_APB0_FREE_CLK:
+		/* apb0_free_div bits 10:8 */
+		div = (reg >> CLK_ARM_DIV_APB0_FREE_DIV_SHIFT) &
+			CLK_ARM_DIV_APB0_FREE_DIV_MASK;
+		div++;
+		break;
+
+	case ARMPLL_ARM_SWITCH_CLK:
+		/* arm_switch_div bits 6:5 */
+		div = (reg >> CLK_ARM_DIV_ARM_SWITCH_DIV_SHIFT) &
+			CLK_ARM_DIV_ARM_SWITCH_DIV_MASK;
+		div++;
+		break;
+
+	case ARMPLL_ARM_APB_CLK:
+		/* IPROC_CLK_APB_SW_DIV_REG apb_clk_div bits 1:0 */
+		reg = readl(clk->regs_base + IPROC_CLK_APB_SW_DIV_OFFSET);
+		div = reg & CLK_APB_SW_DIV_APB_CLK_DIV_MASK;
+		div++;
+		break;
+
+	case ARMPLL_ARM_PERIPH_CLK:      /* periph_clk */
+		div = 2;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	clk->rate = parent_rate / div;
+	pr_debug("Clock rate A9PLL chan 0x%x: %lu, div: %d\n",
+		clk->chan, clk->rate, div);
+
+	return clk->rate;
+}
+
+static unsigned long clk_a9pll_chan_recalc_rate(struct clk_hw *hwclk,
+	unsigned long parent_rate)
+{
+	struct brcm_clk *bcm_clk = to_brcm_clk(hwclk);
+
+	return a9pll_chan_status(bcm_clk, parent_rate);
+}
+
+static const struct clk_ops a9pll_chan_ops = {
+	.recalc_rate = clk_a9pll_chan_recalc_rate,
+};
+
+static __init struct clk *iproc_clock_init(struct device_node *node,
+	const struct clk_ops *ops)
+{
+	u32 channel = 0;
+	struct clk *clk;
+	struct brcm_clk *brcm_clk;
+	const char *clk_name = node->name;
+	const char *parent_name;
+	struct clk_init_data init;
+	int rc;
+
+	pr_debug("Clock name %s\n", node->name);
+
+	rc = of_property_read_u32(node, "channel", &channel);
+	brcm_clk = kzalloc(sizeof(*brcm_clk), GFP_KERNEL);
+	if (WARN_ON(!brcm_clk))
+		return NULL;
+
+	/* Read base address from device tree and map to virtual address. */
+	brcm_clk->regs_base = of_iomap(node, 0);
+	if (WARN_ON(!brcm_clk->regs_base))
+		goto err_alloc;
+
+	brcm_clk->chan = channel;
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
+	init.name = clk_name;
+	init.ops = ops;
+	init.flags = 0;
+	parent_name = of_clk_get_parent_name(node, 0);
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	brcm_clk->hw.init = &init;
+
+	clk = clk_register(NULL, &brcm_clk->hw);
+	if (WARN_ON(IS_ERR(clk)))
+		goto err_unmap;
+
+	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+	if (WARN_ON(IS_ERR_VALUE(rc)))
+		goto err_unregister;
+
+	rc = clk_register_clkdev(clk, clk_name, NULL);
+	if (WARN_ON(IS_ERR_VALUE(rc)))
+		goto err_provider;
+
+	return clk;
+
+err_provider:
+	of_clk_del_provider(node);
+
+err_unregister:
+	clk_unregister(clk);
+
+err_unmap:
+	iounmap(brcm_clk->regs_base);
+
+err_alloc:
+	kfree(brcm_clk);
+
+	return NULL;
+}
+
+static void __init iproc_armpll_init(struct device_node *node)
+{
+	iproc_clock_init(node, &a9pll_ops);
+}
+CLK_OF_DECLARE(iproc_armpllx, "brcm,iproc-arm-a9pll", iproc_armpll_init);
+
+static void __init iproc_arm_ch_init(struct device_node *node)
+{
+	iproc_clock_init(node, &a9pll_chan_ops);
+}
+CLK_OF_DECLARE(iproc_arm_ch, "brcm,iproc-arm-ch", iproc_arm_ch_init);
-- 
1.7.9.5

[PATCH V4 3/7] dt-bindings: Document Broadcom Cygnus SoC and clock driver

[Scott Branden]

From: Jonathan Richardson <jonathar@broadcom.com>

Reviewed-by: Arun Parameswaran <aparames@broadcom.com>
Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 .../devicetree/bindings/arm/bcm/cygnus.txt         |   31 +++++
 .../devicetree/bindings/clock/clk-cygnus.txt       |  121 ++++++++++++++++++++
 .../devicetree/bindings/clock/clk-iproc.txt        |   48 ++++++++
 3 files changed, 200 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/cygnus.txt
 create mode 100644 Documentation/devicetree/bindings/clock/clk-cygnus.txt
 create mode 100644 Documentation/devicetree/bindings/clock/clk-iproc.txt

diff --git a/Documentation/devicetree/bindings/arm/bcm/cygnus.txt b/Documentation/devicetree/bindings/arm/bcm/cygnus.txt
new file mode 100644
index 0000000..4c77169
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/cygnus.txt
@@ -0,0 +1,31 @@
+Broadcom Cygnus device tree bindings
+------------------------------------
+
+
+Boards with Cygnus SoCs shall have the following properties:
+
+Required root node property:
+
+BCM11300
+compatible = "brcm,bcm11300", "brcm,cygnus";
+
+BCM11320
+compatible = "brcm,bcm11320", "brcm,cygnus";
+
+BCM11350
+compatible = "brcm,bcm11350", "brcm,cygnus";
+
+BCM11360
+compatible = "brcm,bcm11360", "brcm,cygnus";
+
+BCM58300
+compatible = "brcm,bcm58300", "brcm,cygnus";
+
+BCM58302
+compatible = "brcm,bcm58302", "brcm,cygnus";
+
+BCM58303
+compatible = "brcm,bcm58303", "brcm,cygnus";
+
+BCM58305
+compatible = "brcm,bcm58305", "brcm,cygnus";
diff --git a/Documentation/devicetree/bindings/clock/clk-cygnus.txt b/Documentation/devicetree/bindings/clock/clk-cygnus.txt
new file mode 100644
index 0000000..7e03837
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clk-cygnus.txt
@@ -0,0 +1,121 @@
+Broadcom Cygnus Clock Controller
+
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The Cygnus clock controller manages several PLL's and their channels, found only
+on the Cygnus chip. Clocks that are common to iProc can be found in the iProc
+clock controller. The controllers are split into a parent-child relationship
+where the parent is the PLL and the child controls the PLL's channels.
+
+All PLL's are derived from a 25MHz oscillator. The PLL's controlled are the
+GENPLL, LCPLL, the MIPI PLL. In addition, there are two clocks derived from
+GENPLL channel 0, and three that are derived directly from the oscillator.
+
+Required properties:
+- compatible: Must be one of the following:
+    "brcm,cygnus-lcpll-clk" - Controls LCPLL.
+    "brcm,cygnus-lcpll-ch" -  Controls LCPLL (parent) channels
+    "brcm,cygnus-genpll-clk" - Controls parent GENPLL
+    "brcm,cygnus-genpll-ch" - Controls GENPLL (parent) channels
+    "brcm,cygnus-mipipll-clk" - Controls MIPI PLL
+    "brcm,cygnus-mipipll-ch" - Controls parent MIPI PLL (parent) channels
+    "brcm,cygnus-osc-derived" - Controls oscillator (parent) derived channels
+        not controlled by any PLL.
+    "brcm,cygnus-pll-derived" - Controls clocks derived from GENPLL channel 0.
+	  These clocks have hard wired internal dividers and their clock rates
+	  scale according to the GENPLL channel.
+
+- reg: First register is the base address of the PLL. Register 2 and 3 are
+  required by some clocks. They are the top clock gating control used to
+  enable/disable clocks (ch 1), and the CRMU PLL AON CONTROL register which
+  powers on PLL/LDO's (ch 2).
+
+- clocks: The input parent clock phandle for the clock. This is either a PLL,
+  oscillator, or GENPLL channel 0.
+
+- channel: The PLL channel that the clock belongs to. This is used for
+  "brcm,cygnus-lcpll-ch", "brcm,cygnus-genpll-ch", "brcm,cygnus-mipipll-ch",
+  "brcm,cygnus-osc-derived" only.
+
+- div: Used by "brcm,cygnus-pll-derived" to define the hard coded internal
+  divider value. Used by "brcm,cygnus-osc-derived" to specify the programmable
+  divider.
+
+- #clock-cells: From common clock binding; shall be set to 0.
+
+Examples:
+
+		osc: oscillator {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <25000000>;
+		};
+
+		lcpll: lcpll@0301d02c {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-lcpll-clk";
+			reg = <0x0301d02c 0x1c>;
+			clocks = <&osc>;
+		};
+
+		genpll: genpll@0301d000 {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-genpll-clk";
+			reg = <0x0301d000 0x2c>,
+				  <0x180AA024 0x4>,
+				  <0x0301C020 0x4>;
+			clocks = <&osc>;
+		};
+
+		axi21_clk: genpll_ch0@0301d000 {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-genpll-ch";
+			reg = <0x0301d000 0x2c>;
+			clocks = <&genpll>;
+			channel = <0>;
+		};
+
+		pcie_clk: lcpll_ch0@0301d02c {
+			compatible = "brcm,cygnus-lcpll-ch";
+			reg = <0x0301d02c 0x1c>;
+			#clock-cells = <0>;
+			clocks = <&lcpll>;
+			channel = <0>;
+		};
+
+		axi41_clk: axi41_clk {
+			reg = <0x0301d000 0x2c>;
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-pll-derived";
+			clocks = <&axi21_clk>;
+			div = <2>;
+		};
+
+		keypad_clk: keypad_clk@0301D048 {
+			compatible = "brcm,cygnus-osc-derived";
+			reg = <0x0301D048 0x4>,
+				  <0x180AA024 0x4>;
+			#clock-cells = <0>;
+			clocks = <&osc>;
+			channel = <0>;
+			div = <392>;
+		};
+
+		mipipll: mipipll@180a9800 {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-mipipll-clk";
+			reg = <0x180a9800 0x2c>,
+				  top_clk_gating_ctrl: <0x180AA024 0x4>,
+				  crmu_pll_aon_ctrl: <0x0301C020 0x4>;
+			clocks = <&osc>;
+		};
+
+		lcd_clk: mipipll_ch1@180a9800 {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-mipipll-ch";
+			reg = <0x180a9800 0x2c>,
+				  <0x180AA024 0x4>;
+			clocks = <&mipipll>;
+			channel = <1>;
+		};
diff --git a/Documentation/devicetree/bindings/clock/clk-iproc.txt b/Documentation/devicetree/bindings/clock/clk-iproc.txt
new file mode 100644
index 0000000..b5d4f08
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clk-iproc.txt
@@ -0,0 +1,48 @@
+Broadcom iProc Clock Controller
+
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The iProc clock controller manages clocks that are common to iProc chips.
+The controllers are split into a parent-child relationship where the parent is
+the PLL and the child controls the PLL's channels.
+
+The only PLL controlled is the ARM PLL which is derived from a 25MHz crystal.
+
+Required properties:
+- compatible: Must be one of the following:
+    "brcm,iproc-arm-a9pll" - Controls ARM PLL.
+    "brcm,iproc-arm-ch" -  Controls ARM PLL (parent) channels
+
+- reg: The base address of the PLL.
+
+- clocks: The input parent clock phandle for the clock. This is either a PLL,
+  or oscillator.
+
+- channel: The PLL channel that the clock belongs to. This is used for
+  "brcm,iproc-arm-ch" only.
+
+- #clock-cells: From common clock binding; shall be set to 0.
+
+Example:
+
+	osc: oscillator {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <25000000>;
+	};
+
+	a9pll: arm_clk@19000000 {
+		compatible = "brcm,iproc-arm-a9pll";
+		reg = <0x19000000 0x1000>;
+		#clock-cells = <0>;
+		clocks = <&osc>;
+	};
+
+	periph_clk: periph_clk@19000000 {
+		compatible = "brcm,iproc-arm-ch";
+		reg = <0x19000000 0x1000>;
+		#clock-cells = <0>;
+		clocks = <&a9pll>;
+		channel = <3>;
+	};
-- 
1.7.9.5

[PATCH V4 4/7] ARM: cygnus defconfig : Initial defconfig for Broadcom Cygnus SoC

[Scott Branden]

From: Jonathan Richardson <jonathar@broadcom.com>

This defconfig is utilized so a customer or developer can understand
what kernel drivers are utilized by the Cygnus SoC.  It also enables
debug configs which should be disabled if optimal performance is
desired.

Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/configs/bcm_cygnus_defconfig |  221 +++++++++++++++++++++++++++++++++
 1 file changed, 221 insertions(+)
 create mode 100644 arch/arm/configs/bcm_cygnus_defconfig

diff --git a/arch/arm/configs/bcm_cygnus_defconfig b/arch/arm/configs/bcm_cygnus_defconfig
new file mode 100644
index 0000000..cf4c107
--- /dev/null
+++ b/arch/arm/configs/bcm_cygnus_defconfig
@@ -0,0 +1,221 @@
+CONFIG_KERNEL_XZ=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=19
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_BLK_CGROUP=y
+CONFIG_NAMESPACES=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BCM_CYGNUS=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+# CONFIG_COMPACTION is not set
+# CONFIG_ATAGS is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_TCP_CONG_ADVANCED=y
+# CONFIG_TCP_CONG_BIC is not set
+# CONFIG_TCP_CONG_WESTWOOD is not set
+# CONFIG_TCP_CONG_HTCP is not set
+CONFIG_IPV6=y
+# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET6_XFRM_MODE_BEET is not set
+# CONFIG_IPV6_SIT is not set
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+CONFIG_NETFILTER=y
+# CONFIG_BRIDGE_NETFILTER is not set
+CONFIG_NF_CONNTRACK=y
+# CONFIG_NF_CONNTRACK_PROCFS is not set
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_RAW=y
+CONFIG_NF_CONNTRACK_IPV6=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_MATCH_AH=y
+CONFIG_IP6_NF_MATCH_EUI64=y
+CONFIG_IP6_NF_MATCH_FRAG=y
+CONFIG_IP6_NF_MATCH_OPTS=y
+CONFIG_IP6_NF_MATCH_IPV6HEADER=y
+CONFIG_IP6_NF_MATCH_MH=y
+CONFIG_IP6_NF_MATCH_RT=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_IP6_NF_RAW=y
+CONFIG_BRIDGE=y
+# CONFIG_BRIDGE_IGMP_SNOOPING is not set
+CONFIG_VLAN_8021Q=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_FQ_CODEL=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+# CONFIG_BLK_DEV is not set
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_PHYLIB=y
+CONFIG_BROADCOM_PHY=y
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
+CONFIG_I2C_SMBUS=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_DEBUG=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_SOC=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_PWM=y
+CONFIG_EXT4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_UBIFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_REDUCED=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_OBJECTS=y
+CONFIG_DEBUG_OBJECTS_RCU_HEAD=y
+CONFIG_SLUB_DEBUG_ON=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=110
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_SCHEDSTATS=y
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_PROVE_LOCKING=y
+CONFIG_DEBUG_ATOMIC_SLEEP=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_SG=y
+CONFIG_DEBUG_NOTIFIERS=y
+CONFIG_DEBUG_CREDENTIALS=y
+CONFIG_PROVE_RCU=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_UART_8250=y
+CONFIG_DEBUG_UART_PHYS=0x18023000
+CONFIG_DEBUG_UART_VIRT=0xf1023000
+CONFIG_EARLY_PRINTK=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
-- 
1.7.9.5

[PATCH V4 5/7] ARM: dts: Enable Broadcom Cygnus SoC

[Scott Branden]

From: Jonathan Richardson <jonathar@broadcom.com>

DT files to enable cygnus consisting of the enterprise phone board
variant and cygnus core configuration.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Arun Parameswaran <aparames@broadcom.com>
Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/boot/dts/Makefile             |    1 +
 arch/arm/boot/dts/bcm-cygnus.dtsi      |  349 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/bcm911360_entphn.dts |   22 ++
 3 files changed, 372 insertions(+)
 create mode 100644 arch/arm/boot/dts/bcm-cygnus.dtsi
 create mode 100644 arch/arm/boot/dts/bcm911360_entphn.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b8c5cd3..b95d41d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -52,6 +52,7 @@ dtb-$(CONFIG_ARCH_AT91)	+= sama5d36ek.dtb
 dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
 dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
+dtb-$(CONFIG_ARCH_BCM_CYGNUS) += bcm911360_entphn.dtb
 dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
 dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
 	bcm21664-garnet.dtb
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
new file mode 100644
index 0000000..81da0d8
--- /dev/null
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -0,0 +1,349 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "brcm,cygnus";
+	model = "Broadcom Cygnus SoC";
+	interrupt-parent = <&gic>;
+
+	aliases {
+		serial0 = &uart3;
+		serial1 = &uart0;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200 earlyprintk debug";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <0x0>;
+		};
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		osc: oscillator {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <25000000>;
+		};
+
+		lcpll: lcpll@0301d02c {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-lcpll-clk";
+			reg = <0x0301d02c 0x1c>;
+			clocks = <&osc>;
+		};
+
+		genpll: genpll@0301d000 {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-genpll-clk";
+			reg = <0x0301d000 0x2c>,
+				  <0x180AA024 0x4>,
+				  <0x0301C020 0x4>;
+			clocks = <&osc>;
+		};
+
+		axi21_clk: genpll_ch0@0301d000 {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-genpll-ch";
+			reg = <0x0301d000 0x2c>;
+			clocks = <&genpll>;
+			channel = <0>;
+		};
+
+		clk_25MHz: genpll_ch1@0301d000 {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-genpll-ch";
+			reg = <0x0301d000 0x2c>;
+			clocks = <&genpll>;
+			channel = <1>;
+		};
+
+		sys_clk: genpll_ch2@0301d000 {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-genpll-ch";
+			reg = <0x0301d000 0x2c>;
+			clocks = <&genpll>;
+			channel = <2>;
+		};
+
+		ethernet_clk: genpll_ch3@0301d000 {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-genpll-ch";
+			reg = <0x0301d000 0x2c>;
+			clocks = <&genpll>;
+			channel = <3>;
+		};
+
+		asiu_audio_clk: genpll_ch4@0301d000 {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-genpll-ch";
+			reg = <0x0301d000 0x2c>;
+			clocks = <&genpll>;
+			channel = <4>;
+		};
+
+		asiu_can_clk: genpll_ch5@0301d000 {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-genpll-ch";
+			reg = <0x0301d000 0x2c>;
+			clocks = <&genpll>;
+			channel = <5>;
+		};
+
+		pcie_clk: lcpll_ch0@0301d02c {
+			compatible = "brcm,cygnus-lcpll-ch";
+			reg = <0x0301d02c 0x1c>;
+			#clock-cells = <0>;
+			clocks = <&lcpll>;
+			channel = <0>;
+		};
+
+		ddr_clk: lcpll_ch1@0301d02c {
+			compatible = "brcm,cygnus-lcpll-ch";
+			reg = <0x0301d02c 0x1c>;
+			#clock-cells = <0>;
+			clocks = <&lcpll>;
+			channel = <1>;
+		};
+
+		sdio_clk: lcpll_ch2@0301d02c {
+			compatible = "brcm,cygnus-lcpll-ch";
+			reg = <0x0301d02c 0x1c>;
+			#clock-cells = <0>;
+			clocks = <&lcpll>;
+			channel = <2>;
+		};
+
+		usb_clk: lcpll_ch3@0301d02c {
+		    compatible = "brcm,cygnus-lcpll-ch";
+			reg = <0x0301d02c 0x1c>;
+			#clock-cells = <0>;
+			clocks = <&lcpll>;
+			channel = <3>;
+		};
+
+		smart_card_clk: lcpll_ch4@0301d02c {
+			compatible = "brcm,cygnus-lcpll-ch";
+			reg = <0x0301d02c 0x1c>;
+			#clock-cells = <0>;
+			clocks = <&lcpll>;
+			channel = <4>;
+		};
+
+		ch5_unknown_clk: lcpll_ch5@0301d02c {
+			compatible = "brcm,cygnus-lcpll-ch";
+			reg = <0x0301d02c 0x1c>;
+			#clock-cells = <0>;
+			clocks = <&lcpll>;
+			channel = <5>;
+		};
+
+		/*
+		 * There are 2 clocks derived from genpll ch0 (axi21) which are
+		 * divided internally by 2 and 4. If axi21 clock rate changes, these
+		 * derived clock rates scale accordingly.
+		 */
+
+		axi41_clk: axi41_clk {
+			reg = <0x0301d000 0x2c>;
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-pll-derived";
+			clocks = <&axi21_clk>;
+			div = <2>;
+		};
+
+		axi81_clk: axi81_clk {
+			reg = <0x0301d000 0x2c>;
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-pll-derived";
+			clocks = <&axi21_clk>;
+			div = <4>;
+		};
+
+		/*
+		 * The main output of the ARM PLL is arm_clk with several derived
+		 * child clocks:
+		 * 		periph_clk
+		 * 		apb_clk
+		 * 		arm_switch
+		 * 		apb0_free
+		 */
+		a9pll: arm_clk@19000000 {
+			compatible = "brcm,iproc-arm-a9pll";
+			reg = <0x19000000 0x1000>;
+			#clock-cells = <0>;
+			clocks = <&osc>;
+		};
+
+		periph_clk: periph_clk@19000000 {
+			compatible = "brcm,iproc-arm-ch";
+			reg = <0x19000000 0x1000>;
+			#clock-cells = <0>;
+			clocks = <&a9pll>;
+			channel = <3>;
+		};
+
+		apb0_free: apb0_free@19000000 {
+			compatible = "brcm,iproc-arm-ch";
+			reg = <0x19000000 0x1000>;
+			#clock-cells = <0>;
+			clocks = <&a9pll>;
+			channel = <0>;
+		};
+
+		arm_switch: arm_switch@19000000 {
+			compatible = "brcm,iproc-arm-ch";
+			reg = <0x19000000 0x1000>;
+			#clock-cells = <0>;
+			clocks = <&a9pll>;
+			channel = <1>;
+		};
+
+		apb_clk: apb_clk@19000000 {
+			compatible = "brcm,iproc-arm-ch";
+			reg = <0x19000000 0x1000>;
+			#clock-cells = <0>;
+			clocks = <&a9pll>;
+			channel = <2>;
+		};
+
+		/*
+		 * Clocks derived from oscillator.
+		 */
+		keypad_clk: keypad_clk@0301D048 {
+			compatible = "brcm,cygnus-osc-derived";
+			reg = <0x0301D048 0x4>,
+				  <0x180AA024 0x4>;
+			#clock-cells = <0>;
+			clocks = <&osc>;
+			channel = <0>;
+			div = <392>;
+		};
+
+		adc_clk: adc_clk@0301D04C {
+			compatible = "brcm,cygnus-osc-derived";
+			reg = <0x0301D04C 0x4>,
+				  <0x180AA024 0x4>;
+			#clock-cells = <0>;
+			clocks = <&osc>;
+			channel = <1>;
+		};
+
+		pwm_clk: pwm_clk@0301D050 {
+			compatible = "brcm,cygnus-osc-derived";
+			reg = <0x0301D050 0x4>,
+				  <0x180AA024 0x4>;
+			#clock-cells = <0>;
+			clocks = <&osc>;
+			channel = <2>;
+		};
+
+		mipipll: mipipll@180a9800 {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-mipipll-clk";
+			reg = <0x180a9800 0x2c>,
+				  top_clk_gating_ctrl: <0x180AA024 0x4>,
+				  crmu_pll_aon_ctrl: <0x0301C020 0x4>;
+			clocks = <&osc>;
+		};
+
+		lcd_clk: mipipll_ch1@180a9800 {
+			#clock-cells = <0>;
+			compatible = "brcm,cygnus-mipipll-ch";
+			reg = <0x180a9800 0x2c>,
+				  <0x180AA024 0x4>;
+			clocks = <&mipipll>;
+			channel = <1>;
+		};
+	};
+
+	amba {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "arm,amba-bus", "simple-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		wdt@18009000 {
+			 compatible = "arm,sp805" , "arm,primecell";
+			 reg = <0x18009000 0x1000>;
+			 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+			 clocks = <&axi81_clk>;
+			 clock-names = "apb_pclk";
+		};
+	};
+
+	uart3: serial@18023000 {
+		compatible = "snps,dw-apb-uart";
+		reg = <0x18023000 0x100>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <100000000>;
+		clocks = <&axi81_clk>;
+		status = "okay";
+	};
+
+	uart0: serial@18020000 {
+		compatible = "snps,dw-apb-uart";
+		reg = <0x18020000 0x100>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&axi81_clk>;
+		clock-frequency = <100000000>;
+		status = "okay";
+	};
+
+	gic: interrupt-controller@19021000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+		interrupt-controller;
+		reg = <0x19021000 0x1000>,
+		      <0x19020100 0x100>;
+	};
+
+	L2: l2-cache {
+		compatible = "arm,pl310-cache";
+		reg = <0x19022000 0x1000>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	timer@19020200 {
+		compatible = "arm,cortex-a9-global-timer";
+		reg = <0x19020200 0x100>;
+		interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&periph_clk>;
+	};
+
+};
diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts
new file mode 100644
index 0000000..c5188d7
--- /dev/null
+++ b/arch/arm/boot/dts/bcm911360_entphn.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "bcm-cygnus.dtsi"
+
+/ {
+	model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)";
+	compatible = "brcm,bcm11360", "brcm,cygnus";
+};
-- 
1.7.9.5

[PATCH V4 6/7] MAINTAINERS: Entry for Cygnus/iproc arm architecture and clock drivers

[Scott Branden]

Acked-by: Jonathan Richardson <jonathar@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 MAINTAINERS |   17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index a12edf2..0900082 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2071,9 +2071,24 @@ L:	linux-scsi@vger.kernel.org
 S:	Supported
 F:	drivers/scsi/bnx2i/
 
-BROADCOM KONA GPIO DRIVER
+BROADCOM CYGNUS/IPROC ARM ARCHITECTURE
 M:	Ray Jui <rjui@broadcom.com>
+M:	Scott Branden <sbranden@broadcom.com>
+L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 L:	bcm-kernel-feedback-list@broadcom.com
+S:	Maintained
+F:	Documentation/devicetree/bindings/arm/bcm/cygnus.txt
+F:	arch/arm/boot/dts/bcm-cygnus.dtsi
+F:	arch/arm/boot/dts/bcm911360_entphn.dts
+F:	arch/arm/configs/bcm_cygnus_defconfig
+F:	arch/arm/mach-bcm/bcm_cygnus.c
+F:	Documentation/devicetree/bindings/clock/clk-cygnus.txt
+F:	Documentation/devicetree/bindings/clock/clk-iproc.txt
+F:	drivers/clk/bcm/clk-cygnus.c
+F:	drivers/clk/bcm/clk-iproc.c
+
+BROADCOM KONA GPIO DRIVER
+M:	Ray Jui <rjui@broadcom.com>
 S:	Supported
 F:	drivers/gpio/gpio-bcm-kona.c
 F:	Documentation/devicetree/bindings/gpio/gpio-bcm-kona.txt
-- 
1.7.9.5

[PATCH V4 7/7] ARM: multi_v7_defconfig: Enable ARCH_BCM_CYGNUS config

[Scott Branden]

Enabled Broadcom Cygnus SoC family in multi_v7_defconfig by using
CONFIG_ARCH_BCM_CYGNUS=y.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/configs/multi_v7_defconfig |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 5fb95fb..d02f56d 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -17,6 +17,7 @@ CONFIG_MACH_ARMADA_38X=y
 CONFIG_MACH_ARMADA_XP=y
 CONFIG_MACH_DOVE=y
 CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BCM_CYGNUS=y
 CONFIG_ARCH_BCM_MOBILE=y
 CONFIG_ARCH_BCM_5301X=y
 CONFIG_ARCH_BRCMSTB=y
-- 
1.7.9.5

Re: [PATCH V4 6/7] MAINTAINERS: Entry for Cygnus/iproc arm architecture and clock drivers

[Joe Perches]

On Thu, 2014-10-09 at 15:44 -0700, Scott Branden wrote:
> Acked-by: Jonathan Richardson <jonathar@broadcom.com>
> Signed-off-by: Scott Branden <sbranden@broadcom.com>
> ---
>  MAINTAINERS |   17 ++++++++++++++++-
>  1 file changed, 16 insertions(+), 1 deletion(-)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index a12edf2..0900082 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2071,9 +2071,24 @@ L:	linux-scsi@vger.kernel.org
>  S:	Supported
>  F:	drivers/scsi/bnx2i/
>  
> -BROADCOM KONA GPIO DRIVER
> +BROADCOM CYGNUS/IPROC ARM ARCHITECTURE
>  M:	Ray Jui <rjui@broadcom.com>
> +M:	Scott Branden <sbranden@broadcom.com>
> +L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
>  L:	bcm-kernel-feedback-list@broadcom.com
> +S:	Maintained
> +F:	Documentation/devicetree/bindings/arm/bcm/cygnus.txt
> +F:	arch/arm/boot/dts/bcm-cygnus.dtsi
> +F:	arch/arm/boot/dts/bcm911360_entphn.dts
> +F:	arch/arm/configs/bcm_cygnus_defconfig
> +F:	arch/arm/mach-bcm/bcm_cygnus.c
> +F:	Documentation/devicetree/bindings/clock/clk-cygnus.txt
> +F:	Documentation/devicetree/bindings/clock/clk-iproc.txt
> +F:	drivers/clk/bcm/clk-cygnus.c
> +F:	drivers/clk/bcm/clk-iproc.c
> +
> +BROADCOM KONA GPIO DRIVER
> +M:	Ray Jui <rjui@broadcom.com>
>  S:	Supported
>  F:	drivers/gpio/gpio-bcm-kona.c
>  F:	Documentation/devicetree/bindings/gpio/gpio-bcm-kona.txt

This drops this L line from BROADCOM KONA GPIO DRIVER
L:	bcm-kernel-feedback-list@broadcom.com

Is that what you want?

Re: [PATCH V4 6/7] MAINTAINERS: Entry for Cygnus/iproc arm architecture and clock drivers

[Scott Branden]

On 14-10-09 04:00 PM, Joe Perches wrote:
> On Thu, 2014-10-09 at 15:44 -0700, Scott Branden wrote:
>> Acked-by: Jonathan Richardson <jonathar@broadcom.com>
>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>> ---
>>   MAINTAINERS |   17 ++++++++++++++++-
>>   1 file changed, 16 insertions(+), 1 deletion(-)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index a12edf2..0900082 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -2071,9 +2071,24 @@ L:	linux-scsi@vger.kernel.org
>>   S:	Supported
>>   F:	drivers/scsi/bnx2i/
>>
>> -BROADCOM KONA GPIO DRIVER
>> +BROADCOM CYGNUS/IPROC ARM ARCHITECTURE
>>   M:	Ray Jui <rjui@broadcom.com>
>> +M:	Scott Branden <sbranden@broadcom.com>
>> +L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
>>   L:	bcm-kernel-feedback-list@broadcom.com
>> +S:	Maintained
>> +F:	Documentation/devicetree/bindings/arm/bcm/cygnus.txt
>> +F:	arch/arm/boot/dts/bcm-cygnus.dtsi
>> +F:	arch/arm/boot/dts/bcm911360_entphn.dts
>> +F:	arch/arm/configs/bcm_cygnus_defconfig
>> +F:	arch/arm/mach-bcm/bcm_cygnus.c
>> +F:	Documentation/devicetree/bindings/clock/clk-cygnus.txt
>> +F:	Documentation/devicetree/bindings/clock/clk-iproc.txt
>> +F:	drivers/clk/bcm/clk-cygnus.c
>> +F:	drivers/clk/bcm/clk-iproc.c
>> +
>> +BROADCOM KONA GPIO DRIVER
>> +M:	Ray Jui <rjui@broadcom.com>
>>   S:	Supported
>>   F:	drivers/gpio/gpio-bcm-kona.c
>>   F:	Documentation/devicetree/bindings/gpio/gpio-bcm-kona.txt
>
> This drops this L line from BROADCOM KONA GPIO DRIVER
> L:	bcm-kernel-feedback-list@broadcom.com
>
> Is that what you want?
Wow, sorry.  I'll correct after further comments.
>

Re: [PATCH V4 1/7] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Arnd Bergmann]

On Thursday 09 October 2014 15:44:25 Scott Branden wrote:
> From: Jonathan Richardson <jonathar@broadcom.com>
> 
> Adds initial support for the Cygnus SoC based on Broadcom’s iProc series.
> Move ARCH_BCM_5301x under the ARCH_BCM_IPROC architecture.
> 
> Reviewed-by: Ray Jui <rjui@broadcom.com>
> Reviewed-by: Desmond Liu <desmondl@broadcom.com>
> Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
> Tested-by: Jonathan Richardson <jonathar@broadcom.com>
> Signed-off-by: Scott Branden <sbranden@broadcom.com>

No signoff from the Author?

> diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
> index b11ad54..85363de 100644
> --- a/arch/arm/Kconfig.debug
> +++ b/arch/arm/Kconfig.debug
> @@ -1051,7 +1051,7 @@ config DEBUG_UART_PL01X
>  
>  # Compatibility options for 8250
>  config DEBUG_UART_8250
> -	def_bool ARCH_DOVE || ARCH_EBSA110 || \
> +	def_bool ARCH_BCM_IPROC || ARCH_DOVE || ARCH_EBSA110 || \
>  		(FOOTBRIDGE && !DEBUG_DC21285_PORT) || \
>  		ARCH_GEMINI || ARCH_IOP13XX || ARCH_IOP32X || \
>  		ARCH_IOP33X || ARCH_IXP4XX || \

As I mentioned before, this is the wrong option. Please use
DEBUG_LL_UART_8250 like all the modern platforms do.

> diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
> index fc93800..b2b6752 100644
> --- a/arch/arm/mach-bcm/Kconfig
> +++ b/arch/arm/mach-bcm/Kconfig
> @@ -5,6 +5,53 @@ menuconfig ARCH_BCM
>  
>  if ARCH_BCM
>  
> +menu "iProc SoC based Machine types"
> +	config ARCH_BCM_IPROC
> +		bool "Broadcom ARMv7 iProc boards" if ARCH_MULTI_V7
> +		depends on ARCH_BCM_CYGNUS || ARCH_BCM_5301X

Please make this a silent option by dropping the text after 'bool',
and the 'depends on' line.

> +		select ARM_GIC
> +		select CACHE_L2X0
> +		select HAVE_ARM_SCU if SMP
> +		select HAVE_ARM_TWD if SMP
> +		select ARM_GLOBAL_TIMER
> +
> +		select CLKSRC_MMIO
> +		select ARCH_REQUIRE_GPIOLIB
> +		select ARM_AMBA
> +		select PINCTRL

> +
> +static const char const *bcm_cygnus_dt_compat[] = {
> +	"brcm,cygnus",
> +	NULL,
> +};
> +
> +DT_MACHINE_START(BCM_CYGNUS_DT, "Broadcom Cygnus SoC")
> +	.l2c_aux_val	= 0,
> +	.l2c_aux_mask	= ~0,
> +	.dt_compat = bcm_cygnus_dt_compat,
> +MACHINE_END
> 

This looks good now.

	Arnd

Re: [PATCH V4 7/7] ARM: multi_v7_defconfig: Enable ARCH_BCM_CYGNUS config

[Arnd Bergmann]

On Thursday 09 October 2014 15:44:31 Scott Branden wrote:
> Enabled Broadcom Cygnus SoC family in multi_v7_defconfig by using
> CONFIG_ARCH_BCM_CYGNUS=y.
> 
> Signed-off-by: Scott Branden <sbranden@broadcom.com>
> ---
>  arch/arm/configs/multi_v7_defconfig |    1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
> index 5fb95fb..d02f56d 100644
> --- a/arch/arm/configs/multi_v7_defconfig
> +++ b/arch/arm/configs/multi_v7_defconfig
> @@ -17,6 +17,7 @@ CONFIG_MACH_ARMADA_38X=y
>  CONFIG_MACH_ARMADA_XP=y
>  CONFIG_MACH_DOVE=y
>  CONFIG_ARCH_BCM=y
> +CONFIG_ARCH_BCM_CYGNUS=y
>  CONFIG_ARCH_BCM_MOBILE=y
>  CONFIG_ARCH_BCM_5301X=y
>  CONFIG_ARCH_BRCMSTB=y
> 

Does this contain all the drivers you need that are enabled in cygnus_defconfig?

	Arnd

Re: [PATCH V4 5/7] ARM: dts: Enable Broadcom Cygnus SoC

[Arnd Bergmann]

On Thursday 09 October 2014 15:44:29 Scott Branden wrote:
> +
> +               lcpll: lcpll@0301d02c {
> +                       #clock-cells = <0>;
> +                       compatible = "brcm,cygnus-lcpll-clk";
> +                       reg = <0x0301d02c 0x1c>;
> +                       clocks = <&osc>;
> +               };
> +
> +               genpll: genpll@0301d000 {
> +                       #clock-cells = <0>;
> +                       compatible = "brcm,cygnus-genpll-clk";
> +                       reg = <0x0301d000 0x2c>,
> +                                 <0x180AA024 0x4>,
> +                                 <0x0301C020 0x4>;
> +                       clocks = <&osc>;
> +               };
> +

To be honest, I'm not too happy about the way you specify a single
register for each clock as a global 'reg' property.

Presumably each of these registers is part of an IP block that does
multiple things, so it would be better to start out with a binding
for each IP block. How many of these blocks are used for clocks, and
what do they do?

	Arnd

Re: [PATCH V4 1/7] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Scott Branden]

On 14-10-10 02:50 AM, Arnd Bergmann wrote:
> On Thursday 09 October 2014 15:44:25 Scott Branden wrote:
>> From: Jonathan Richardson <jonathar@broadcom.com>
>>
>> Adds initial support for the Cygnus SoC based on Broadcom’s iProc series.
>> Move ARCH_BCM_5301x under the ARCH_BCM_IPROC architecture.
>>
>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>> Reviewed-by: Desmond Liu <desmondl@broadcom.com>
>> Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
>> Tested-by: Jonathan Richardson <jonathar@broadcom.com>
>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>
> No signoff from the Author?
It is a collaborative effort.  Jonathan is on 2 month leave so I have 
taken over pushing this through or change Author.
>
>> diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
>> index b11ad54..85363de 100644
>> --- a/arch/arm/Kconfig.debug
>> +++ b/arch/arm/Kconfig.debug
>> @@ -1051,7 +1051,7 @@ config DEBUG_UART_PL01X
>>
>>   # Compatibility options for 8250
>>   config DEBUG_UART_8250
>> -	def_bool ARCH_DOVE || ARCH_EBSA110 || \
>> +	def_bool ARCH_BCM_IPROC || ARCH_DOVE || ARCH_EBSA110 || \
>>   		(FOOTBRIDGE && !DEBUG_DC21285_PORT) || \
>>   		ARCH_GEMINI || ARCH_IOP13XX || ARCH_IOP32X || \
>>   		ARCH_IOP33X || ARCH_IXP4XX || \
>
> As I mentioned before, this is the wrong option. Please use
> DEBUG_LL_UART_8250 like all the modern platforms do.
ok, will remove
>
>> diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
>> index fc93800..b2b6752 100644
>> --- a/arch/arm/mach-bcm/Kconfig
>> +++ b/arch/arm/mach-bcm/Kconfig
>> @@ -5,6 +5,53 @@ menuconfig ARCH_BCM
>>
>>   if ARCH_BCM
>>
>> +menu "iProc SoC based Machine types"
>> +	config ARCH_BCM_IPROC
>> +		bool "Broadcom ARMv7 iProc boards" if ARCH_MULTI_V7
>> +		depends on ARCH_BCM_CYGNUS || ARCH_BCM_5301X
>
> Please make this a silent option by dropping the text after 'bool',
> and the 'depends on' line.
>
ok, will change, thanks
>> +		select ARM_GIC
>> +		select CACHE_L2X0
>> +		select HAVE_ARM_SCU if SMP
>> +		select HAVE_ARM_TWD if SMP
>> +		select ARM_GLOBAL_TIMER
>> +
>> +		select CLKSRC_MMIO
>> +		select ARCH_REQUIRE_GPIOLIB
>> +		select ARM_AMBA
>> +		select PINCTRL
>
>> +
>> +static const char const *bcm_cygnus_dt_compat[] = {
>> +	"brcm,cygnus",
>> +	NULL,
>> +};
>> +
>> +DT_MACHINE_START(BCM_CYGNUS_DT, "Broadcom Cygnus SoC")
>> +	.l2c_aux_val	= 0,
>> +	.l2c_aux_mask	= ~0,
>> +	.dt_compat = bcm_cygnus_dt_compat,
>> +MACHINE_END
>>
>
> This looks good now.
>
> 	Arnd
>

Re: [PATCH V4 5/7] ARM: dts: Enable Broadcom Cygnus SoC

[Scott Branden]

On 14-10-10 03:08 AM, Arnd Bergmann wrote:
> On Thursday 09 October 2014 15:44:29 Scott Branden wrote:
>> +
>> +               lcpll: lcpll@0301d02c {
>> +                       #clock-cells = <0>;
>> +                       compatible = "brcm,cygnus-lcpll-clk";
>> +                       reg = <0x0301d02c 0x1c>;
>> +                       clocks = <&osc>;
>> +               };
>> +
>> +               genpll: genpll@0301d000 {
>> +                       #clock-cells = <0>;
>> +                       compatible = "brcm,cygnus-genpll-clk";
>> +                       reg = <0x0301d000 0x2c>,
>> +                                 <0x180AA024 0x4>,
>> +                                 <0x0301C020 0x4>;
>> +                       clocks = <&osc>;
>> +               };
>> +
>
> To be honest, I'm not too happy about the way you specify a single
> register for each clock as a global 'reg' property.
I'm not happy with this either.  Will rework.
>
> Presumably each of these registers is part of an IP block that does
> multiple things, so it would be better to start out with a binding
> for each IP block. How many of these blocks are used for clocks, and
> what do they do?
Clocks are a little scattered in the chip and don't make a lot of sense 
for easy software programming.  Will look at how to change bindings so 
they are flexible to work on other generations.
>
> 	Arnd
>

Re: [PATCH V4 7/7] ARM: multi_v7_defconfig: Enable ARCH_BCM_CYGNUS config

[Scott Branden]

On 14-10-10 02:59 AM, Arnd Bergmann wrote:
> On Thursday 09 October 2014 15:44:31 Scott Branden wrote:
>> Enabled Broadcom Cygnus SoC family in multi_v7_defconfig by using
>> CONFIG_ARCH_BCM_CYGNUS=y.
>>
>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>> ---
>>   arch/arm/configs/multi_v7_defconfig |    1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
>> index 5fb95fb..d02f56d 100644
>> --- a/arch/arm/configs/multi_v7_defconfig
>> +++ b/arch/arm/configs/multi_v7_defconfig
>> @@ -17,6 +17,7 @@ CONFIG_MACH_ARMADA_38X=y
>>   CONFIG_MACH_ARMADA_XP=y
>>   CONFIG_MACH_DOVE=y
>>   CONFIG_ARCH_BCM=y
>> +CONFIG_ARCH_BCM_CYGNUS=y
>>   CONFIG_ARCH_BCM_MOBILE=y
>>   CONFIG_ARCH_BCM_5301X=y
>>   CONFIG_ARCH_BRCMSTB=y
>>
>
> Does this contain all the drivers you need that are enabled in cygnus_defconfig?
Will enable more - thanks for reminding.
>
> 	Arnd
>

[PATCH 0/1] sdhci-bcm2835: added quirk and removed udelay in write ops

[Scott Branden]

This patch contains driver cleanup of sdhci-bcm2835.
Please note that this has not actually been tested on bcm2835 yet.
Testing comes from other devices with the same sdhci controller.

This patch is being put out for testing and acceptance on the 2835.
Please test and comment.

Scott Branden (1):
  mmc: sdhci-bcm2835: added quirk and removed udelay in write ops

 drivers/mmc/host/sdhci-bcm2835.c |  139 ++++++++++++++++++--------------------
 1 file changed, 66 insertions(+), 73 deletions(-)

-- 
1.7.9.5

[PATCH 1/1] mmc: sdhci-bcm2835: added quirk and removed udelay in write ops

[Scott Branden]

Added quirk SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 present in controller.
Removed udelay in write ops by using shadow registers for 16 bit
accesses to 32-bit registers (where necessary).
Optimized 32-bit operations when doing 8/16 register accesses.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/mmc/host/sdhci-bcm2835.c |  139 ++++++++++++++++++--------------------
 1 file changed, 66 insertions(+), 73 deletions(-)

diff --git a/drivers/mmc/host/sdhci-bcm2835.c b/drivers/mmc/host/sdhci-bcm2835.c
index 439d259..d967a4f 100644
--- a/drivers/mmc/host/sdhci-bcm2835.c
+++ b/drivers/mmc/host/sdhci-bcm2835.c
@@ -25,42 +25,28 @@
 #include "sdhci-pltfm.h"
 
 /*
- * 400KHz is max freq for card ID etc. Use that as min card clock. We need to
- * know the min to enable static calculation of max BCM2835_SDHCI_WRITE_DELAY.
- */
-#define MIN_FREQ 400000
-
-/*
  * The Arasan has a bugette whereby it may lose the content of successive
- * writes to registers that are within two SD-card clock cycles of each other
- * (a clock domain crossing problem). It seems, however, that the data
- * register does not have this problem, which is just as well - otherwise we'd
- * have to nobble the DMA engine too.
+ * writes to the same register that are within two SD-card clock cycles of
+ * each other (a clock domain crossing problem).  Problem does not happen with
+ * data.
+ * This wouldn't be a problem with the code except that we can only write the
+ * controller with 32-bit writes.  So two different 16-bit registers in the
+ * written back to back creates the problem.
  *
- * This should probably be dynamically calculated based on the actual card
- * frequency. However, this is the longest we'll have to wait, and doesn't
- * seem to slow access down too much, so the added complexity doesn't seem
- * worth it for now.
- *
- * 1/MIN_FREQ is (max) time per tick of eMMC clock.
- * 2/MIN_FREQ is time for two ticks.
- * Multiply by 1000000 to get uS per two ticks.
- * *1000000 for uSecs.
- * +1 for hack rounding.
+ * In reality, this only happens when a SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT
+ * are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND.
+ * The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so
+ * the work around can be further optimized. We can keep shadow values of
+ * BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued.
+ * Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed
+ * by the TRANSFER+COMMAND in another 32-bit write.
  */
-#define BCM2835_SDHCI_WRITE_DELAY	(((2 * 1000000) / MIN_FREQ) + 1)
 
-struct bcm2835_sdhci {
-	u32 shadow;
+struct bcm2835_sdhci_host {
+	u32 shadow_cmd;
+	u32 shadow_blk;
 };
 
-static void bcm2835_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
-{
-	writel(val, host->ioaddr + reg);
-
-	udelay(BCM2835_SDHCI_WRITE_DELAY);
-}
-
 static inline u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg)
 {
 	u32 val = readl(host->ioaddr + reg);
@@ -71,76 +57,83 @@ static inline u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg)
 	return val;
 }
 
-static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
-{
-	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
-	struct bcm2835_sdhci *bcm2835_host = pltfm_host->priv;
-	u32 oldval = (reg == SDHCI_COMMAND) ? bcm2835_host->shadow :
-		bcm2835_sdhci_readl(host, reg & ~3);
-	u32 word_num = (reg >> 1) & 1;
-	u32 word_shift = word_num * 16;
-	u32 mask = 0xffff << word_shift;
-	u32 newval = (oldval & ~mask) | (val << word_shift);
-
-	if (reg == SDHCI_TRANSFER_MODE)
-		bcm2835_host->shadow = newval;
-	else
-		bcm2835_sdhci_writel(host, newval, reg & ~3);
-}
-
 static u16 bcm2835_sdhci_readw(struct sdhci_host *host, int reg)
 {
-	u32 val = bcm2835_sdhci_readl(host, (reg & ~3));
-	u32 word_num = (reg >> 1) & 1;
-	u32 word_shift = word_num * 16;
-	u32 word = (val >> word_shift) & 0xffff;
-
+	u32 val = bcm2835_sdhci_readl(host->ioaddr, (reg & ~3));
+	u16 word = val >> (reg << 3 & 0x18) & 0xffff;
 	return word;
 }
 
-static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
+static u8 bcm2835_sdhci_readb(struct sdhci_host *host, int reg)
 {
-	u32 oldval = bcm2835_sdhci_readl(host, reg & ~3);
-	u32 byte_num = reg & 3;
-	u32 byte_shift = byte_num * 8;
-	u32 mask = 0xff << byte_shift;
-	u32 newval = (oldval & ~mask) | (val << byte_shift);
+	u32 val = bcm2835_sdhci_readl(host->ioaddr, (reg & ~3));
+	u8 byte = val >> (reg << 3 & 0x18) & 0xff;
+	return byte;
+}
 
-	bcm2835_sdhci_writel(host, newval, reg & ~3);
+static void bcm2835_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
+{
+	writel(val, host->ioaddr + reg);
 }
 
-static u8 bcm2835_sdhci_readb(struct sdhci_host *host, int reg)
+static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 {
-	u32 val = bcm2835_sdhci_readl(host, (reg & ~3));
-	u32 byte_num = reg & 3;
-	u32 byte_shift = byte_num * 8;
-	u32 byte = (val >> byte_shift) & 0xff;
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct bcm2835_sdhci_host *bcm2835_host = pltfm_host->priv;
+	u32 word_shift = reg << 3 & 0x18;
+	u32 mask = 0xffff << word_shift;
+	u32 oldval;
+	u32 newval;
+
+	if (reg == SDHCI_COMMAND) {
+		if (bcm2835_host->shadow_blk != 0) {
+			writel(bcm2835_host->shadow_blk,
+			       host->ioaddr + SDHCI_BLOCK_SIZE);
+			bcm2835_host->shadow_blk = 0;
+		}
+		oldval = bcm2835_host->shadow_cmd;
+	} else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
+		oldval = bcm2835_host->shadow_blk;
+	} else {
+		oldval = readl(host->ioaddr + (reg & ~3));
+	}
+	newval = (oldval & ~mask) | (val << word_shift);
 
-	return byte;
+	if (reg == SDHCI_TRANSFER_MODE)
+		bcm2835_host->shadow_cmd = newval;
+	else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT)
+		bcm2835_host->shadow_blk = newval;
+	else
+		writel(newval, host->ioaddr + (reg & ~3));
 }
 
-static unsigned int bcm2835_sdhci_get_min_clock(struct sdhci_host *host)
+static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 {
-	return MIN_FREQ;
+	u32 oldval = readl(host->ioaddr + (reg & ~3));
+	u32 byte_shift = reg << 3 & 0x18;
+	u32 mask = 0xff << byte_shift;
+	u32 newval = (oldval & ~mask) | (val << byte_shift);
+
+	writel(newval, host->ioaddr + (reg & ~3));
 }
 
 static const struct sdhci_ops bcm2835_sdhci_ops = {
-	.write_l = bcm2835_sdhci_writel,
-	.write_w = bcm2835_sdhci_writew,
-	.write_b = bcm2835_sdhci_writeb,
 	.read_l = bcm2835_sdhci_readl,
 	.read_w = bcm2835_sdhci_readw,
 	.read_b = bcm2835_sdhci_readb,
+	.write_l = bcm2835_sdhci_writel,
+	.write_w = bcm2835_sdhci_writew,
+	.write_b = bcm2835_sdhci_writeb,
 	.set_clock = sdhci_set_clock,
 	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
-	.get_min_clock = bcm2835_sdhci_get_min_clock,
 	.set_bus_width = sdhci_set_bus_width,
 	.reset = sdhci_reset,
 	.set_uhs_signaling = sdhci_set_uhs_signaling,
 };
 
 static const struct sdhci_pltfm_data bcm2835_sdhci_pdata = {
-	.quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
+	.quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 |
+		  SDHCI_QUIRK_BROKEN_CARD_DETECTION |
 		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
 	.ops = &bcm2835_sdhci_ops,
 };
@@ -148,7 +141,7 @@ static const struct sdhci_pltfm_data bcm2835_sdhci_pdata = {
 static int bcm2835_sdhci_probe(struct platform_device *pdev)
 {
 	struct sdhci_host *host;
-	struct bcm2835_sdhci *bcm2835_host;
+	struct bcm2835_sdhci_host *bcm2835_host;
 	struct sdhci_pltfm_host *pltfm_host;
 	int ret;
 
-- 
1.7.9.5

[PATCH v5 0/6] Add initial support for Broadcom Cygnus SoC

[Scott Branden]

This patchset contains initial support for Broadcom's Cygnus SoC based on our
iProc architecture. Initial support is minimal and includes just the mach
platform code, clock driver, and a basic device tree configuration. Peripheral
drivers will be submitted soon, as will device tree configurations for other
Cygnus board variants.

Changes from v4:
 - simple clock tree used. reworked clock driver will be submitted later
 - fixed MAINTAINERS patchset error
 - removed DEBUG_UART_8250 Kconfig.debug legacy support
 - made ARCH_BCM_IPROC a silent Kconfig option
 - removed multi_v7_defconfig as it is not needed at this time, can
   support in future patchset but does not seem optimal configs for our
   current usage.
 
Changes from v3:
 - restart functionality removed.  Will be added in a different patchset
   in drivers/power
 - removed NEON init sequence.  Will be moved to bootloader
 - cleaned up Kconfigs for ARCH_BCM_CYGNUS by removing unnecessary selects
 - consolidated ARCH_BCM_IPROC with select from ARCH_BCM_CYGNUS and
   ARCH_BCM5301X
 - removed bcm911360_entphn binding
 - added documentation for SoCs currently supported in Cygnus family

Changes from v2:
 - rebased to 3.17 kernel

Changes from v1:
 - Address code review comments as per previous responses.
 - Copyright headers updated to remove Broadcom URL.
 - mach platform code still contains hard coded addresses. These address are
   the same for all Cygnus variants. Could you please provide guidance on where
   they should go if you would still like them changed.  There does not seem to
   be a reason to change them to device tree as they do not change.

Jonathan Richardson (3):
  ARM: cygnus: Initial support for Broadcom Cygnus SoC
  dt-bindings: Document Broadcom Cygnus SoC and clocks
  ARM: cygnus defconfig : Initial defconfig for Broadcom Cygnus SoC

Scott Branden (3):
  ARM: dts: Enable Broadcom Cygnus SoC
  MAINTAINERS: Entry for Cygnus/iproc arm architecture
  ARM: mach-bcm: Consolidate currently supported IPROC SoCs

 .../devicetree/bindings/arm/bcm/cygnus.txt         |   31 +++
 .../devicetree/bindings/clock/bcm-cygnus-clock.txt |   34 +++
 MAINTAINERS                                        |   15 ++
 arch/arm/boot/dts/Makefile                         |    4 +
 arch/arm/boot/dts/bcm-cygnus-clock.dtsi            |   73 ++++++
 arch/arm/boot/dts/bcm-cygnus.dtsi                  |  109 +++++++++
 arch/arm/boot/dts/bcm911360_entphn.dts             |   22 ++
 arch/arm/boot/dts/bcm911360k.dts                   |   22 ++
 arch/arm/boot/dts/bcm958300k.dts                   |   22 ++
 arch/arm/configs/bcm_cygnus_defconfig              |  243 ++++++++++++++++++++
 arch/arm/mach-bcm/Kconfig                          |   67 ++++--
 arch/arm/mach-bcm/Makefile                         |    3 +
 arch/arm/mach-bcm/bcm_cygnus.c                     |   26 +++
 13 files changed, 650 insertions(+), 21 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/cygnus.txt
 create mode 100644 Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
 create mode 100644 arch/arm/boot/dts/bcm-cygnus-clock.dtsi
 create mode 100644 arch/arm/boot/dts/bcm-cygnus.dtsi
 create mode 100644 arch/arm/boot/dts/bcm911360_entphn.dts
 create mode 100644 arch/arm/boot/dts/bcm911360k.dts
 create mode 100644 arch/arm/boot/dts/bcm958300k.dts
 create mode 100644 arch/arm/configs/bcm_cygnus_defconfig
 create mode 100644 arch/arm/mach-bcm/bcm_cygnus.c

-- 
1.7.9.5

[PATCH v5 1/6] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Scott Branden]

From: Jonathan Richardson <jonathar@broadcom.com>

Adds initial support for the Cygnus SoC based on Broadcom’s iProc series.
Move ARCH_BCM_5301x under the ARCH_BCM_IPROC architecture.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Desmond Liu <desmondl@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/mach-bcm/Kconfig      |   30 ++++++++++++++++++++++++++++++
 arch/arm/mach-bcm/Makefile     |    3 +++
 arch/arm/mach-bcm/bcm_cygnus.c |   26 ++++++++++++++++++++++++++
 3 files changed, 59 insertions(+)
 create mode 100644 arch/arm/mach-bcm/bcm_cygnus.c

diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 2abad74..ecc544a 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -5,6 +5,36 @@ menuconfig ARCH_BCM
 
 if ARCH_BCM
 
+menu "iProc SoC based Machine types"
+	config ARCH_BCM_IPROC
+		bool
+		select ARM_GIC
+		select CACHE_L2X0
+		select HAVE_ARM_SCU if SMP
+		select HAVE_ARM_TWD if SMP
+		select ARM_GLOBAL_TIMER
+
+		select CLKSRC_MMIO
+		select ARCH_REQUIRE_GPIOLIB
+		select ARM_AMBA
+		select PINCTRL
+		help
+		  This enables support for systems based on Broadcom IPROC architected SoCs.
+		  The IPROC complex contains one or more ARM CPUs along with common
+		  core periperals. Application specific SoCs are created by adding a
+		  uArchitecture containing peripherals outside of the IPROC complex.
+		  Currently supported SoCs are Cygnus.
+
+	config ARCH_BCM_CYGNUS
+		bool "Broadcom Cygnus Support" if ARCH_MULTI_V7
+		select ARCH_BCM_IPROC
+		help
+		  Enable support for the Cygnus family,
+		  which includes the following variants:
+		  BCM11300, BCM11320, BCM11350, BCM11360,
+		  BCM58300, BCM58302, BCM58303, BCM58305.
+endmenu
+
 config ARCH_BCM_MOBILE
 	bool "Broadcom Mobile SoC Support" if ARCH_MULTI_V7
 	select ARCH_REQUIRE_GPIOLIB
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 300ae4b..34d45ba 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -10,6 +10,9 @@
 # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
 
+# Cygnus
+obj-$(CONFIG_ARCH_BCM_CYGNUS) +=  bcm_cygnus.o
+
 # BCM281XX
 obj-$(CONFIG_ARCH_BCM_281XX)	+= board_bcm281xx.o
 
diff --git a/arch/arm/mach-bcm/bcm_cygnus.c b/arch/arm/mach-bcm/bcm_cygnus.c
new file mode 100644
index 0000000..41b4933
--- /dev/null
+++ b/arch/arm/mach-bcm/bcm_cygnus.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <asm/mach/arch.h>
+
+static const char const *bcm_cygnus_dt_compat[] = {
+	"brcm,cygnus",
+	NULL,
+};
+
+DT_MACHINE_START(BCM_CYGNUS_DT, "Broadcom Cygnus SoC")
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
+	.dt_compat = bcm_cygnus_dt_compat,
+MACHINE_END
-- 
1.7.9.5

[PATCH v5 2/6] dt-bindings: Document Broadcom Cygnus SoC and clocks

[Scott Branden]

From: Jonathan Richardson <jonathar@broadcom.com>

Reviewed-by: Arun Parameswaran <aparames@broadcom.com>
Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 .../devicetree/bindings/arm/bcm/cygnus.txt         |   31 ++++++++++++++++++
 .../devicetree/bindings/clock/bcm-cygnus-clock.txt |   34 ++++++++++++++++++++
 2 files changed, 65 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/cygnus.txt
 create mode 100644 Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt

diff --git a/Documentation/devicetree/bindings/arm/bcm/cygnus.txt b/Documentation/devicetree/bindings/arm/bcm/cygnus.txt
new file mode 100644
index 0000000..4c77169
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/cygnus.txt
@@ -0,0 +1,31 @@
+Broadcom Cygnus device tree bindings
+------------------------------------
+
+
+Boards with Cygnus SoCs shall have the following properties:
+
+Required root node property:
+
+BCM11300
+compatible = "brcm,bcm11300", "brcm,cygnus";
+
+BCM11320
+compatible = "brcm,bcm11320", "brcm,cygnus";
+
+BCM11350
+compatible = "brcm,bcm11350", "brcm,cygnus";
+
+BCM11360
+compatible = "brcm,bcm11360", "brcm,cygnus";
+
+BCM58300
+compatible = "brcm,bcm58300", "brcm,cygnus";
+
+BCM58302
+compatible = "brcm,bcm58302", "brcm,cygnus";
+
+BCM58303
+compatible = "brcm,bcm58303", "brcm,cygnus";
+
+BCM58305
+compatible = "brcm,bcm58305", "brcm,cygnus";
diff --git a/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt b/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
new file mode 100644
index 0000000..00d26ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
@@ -0,0 +1,34 @@
+Broadcom Cygnus Clocks
+
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Currently various "fixed" clocks are declared for peripheral drivers that use
+the common clock framework to reference their core clocks. Proper support of
+these clocks will be added later
+
+Device tree example:
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		osc: oscillator {
+			compatible = "fixed-clock";
+			#clock-cells = <1>;
+			clock-frequency = <25000000>;
+		};
+
+		apb_clk: apb_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <1000000000>;
+		};
+
+		periph_clk: periph_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <500000000>;
+		};
+	};
-- 
1.7.9.5

[PATCH v5 3/6] ARM: cygnus defconfig : Initial defconfig for Broadcom Cygnus SoC

[Scott Branden]

From: Jonathan Richardson <jonathar@broadcom.com>

This defconfig is utilized so a customer or developer can understand
what kernel drivers are utilized by the Cygnus SoC.  It also enables
debug configs which should be disabled if optimal performance is
desired.

Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/configs/bcm_cygnus_defconfig |  243 +++++++++++++++++++++++++++++++++
 1 file changed, 243 insertions(+)
 create mode 100644 arch/arm/configs/bcm_cygnus_defconfig

diff --git a/arch/arm/configs/bcm_cygnus_defconfig b/arch/arm/configs/bcm_cygnus_defconfig
new file mode 100644
index 0000000..c8d6158
--- /dev/null
+++ b/arch/arm/configs/bcm_cygnus_defconfig
@@ -0,0 +1,243 @@
+CONFIG_KERNEL_XZ=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_FHANDLE=y
+CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=19
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_BLK_CGROUP=y
+CONFIG_NAMESPACES=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_JUMP_LABEL=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BCM_CYGNUS=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_PCI=y
+CONFIG_PCI_DEBUG=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+# CONFIG_COMPACTION is not set
+# CONFIG_ATAGS is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_TCP_CONG_ADVANCED=y
+# CONFIG_TCP_CONG_BIC is not set
+# CONFIG_TCP_CONG_WESTWOOD is not set
+# CONFIG_TCP_CONG_HTCP is not set
+CONFIG_IPV6=y
+# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET6_XFRM_MODE_BEET is not set
+# CONFIG_IPV6_SIT is not set
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+CONFIG_NETFILTER=y
+# CONFIG_BRIDGE_NETFILTER is not set
+CONFIG_NF_CONNTRACK=y
+# CONFIG_NF_CONNTRACK_PROCFS is not set
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_RAW=y
+CONFIG_NF_CONNTRACK_IPV6=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_MATCH_AH=y
+CONFIG_IP6_NF_MATCH_EUI64=y
+CONFIG_IP6_NF_MATCH_FRAG=y
+CONFIG_IP6_NF_MATCH_OPTS=y
+CONFIG_IP6_NF_MATCH_IPV6HEADER=y
+CONFIG_IP6_NF_MATCH_MH=y
+CONFIG_IP6_NF_MATCH_RT=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_IP6_NF_RAW=y
+CONFIG_BRIDGE=y
+# CONFIG_BRIDGE_IGMP_SNOOPING is not set
+CONFIG_VLAN_8021Q=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_FQ_CODEL=y
+CONFIG_CFG80211=y
+# CONFIG_CFG80211_DEFAULT_PS is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_RFKILL=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_PHYLIB=y
+CONFIG_BROADCOM_PHY=y
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
+CONFIG_I2C_SMBUS=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=y
+# CONFIG_USB_GSPCA is not set
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_DEBUG=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_SOC=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_RTC_CLASS=y
+CONFIG_PWM=y
+CONFIG_EXT4_FS=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_UBIFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_INFO=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_OBJECTS=y
+CONFIG_DEBUG_OBJECTS_RCU_HEAD=y
+CONFIG_SLUB_DEBUG_ON=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=110
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_SCHEDSTATS=y
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_PROVE_LOCKING=y
+CONFIG_DEBUG_ATOMIC_SLEEP=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_SG=y
+CONFIG_DEBUG_NOTIFIERS=y
+CONFIG_DEBUG_CREDENTIALS=y
+CONFIG_PROVE_RCU=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_UART_8250=y
+CONFIG_DEBUG_UART_PHYS=0x18023000
+CONFIG_DEBUG_UART_VIRT=0xf1023000
+CONFIG_EARLY_PRINTK=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
-- 
1.7.9.5

[PATCH v5 4/6] ARM: dts: Enable Broadcom Cygnus SoC

[Scott Branden]

DT files to enable cygnus consisting on reference designs
and cygnus core configuration.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Arun Parameswaran <aparames@broadcom.com>
Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/boot/dts/Makefile              |    4 ++
 arch/arm/boot/dts/bcm-cygnus-clock.dtsi |   73 +++++++++++++++++++++
 arch/arm/boot/dts/bcm-cygnus.dtsi       |  109 +++++++++++++++++++++++++++++++
 arch/arm/boot/dts/bcm911360_entphn.dts  |   22 +++++++
 arch/arm/boot/dts/bcm911360k.dts        |   22 +++++++
 arch/arm/boot/dts/bcm958300k.dts        |   22 +++++++
 6 files changed, 252 insertions(+)
 create mode 100644 arch/arm/boot/dts/bcm-cygnus-clock.dtsi
 create mode 100644 arch/arm/boot/dts/bcm-cygnus.dtsi
 create mode 100644 arch/arm/boot/dts/bcm911360_entphn.dts
 create mode 100644 arch/arm/boot/dts/bcm911360k.dts
 create mode 100644 arch/arm/boot/dts/bcm958300k.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7c80af9..a6b734a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -54,6 +54,10 @@ dtb-$(CONFIG_ARCH_AT91)	+= at91-sama5d4ek.dtb
 dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
 dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
+dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
+	bcm911360_entphn.dtb \
+	bcm911360k.dtb \
+	bcm958300k.dtb
 dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
 dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb
 dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
diff --git a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
new file mode 100644
index 0000000..d06172b
--- /dev/null
+++ b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+clocks {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges;
+
+	osc: oscillator {
+		compatible = "fixed-clock";
+		#clock-cells = <1>;
+		clock-frequency = <25000000>;
+	};
+
+	apb_clk: apb_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1000000000>;
+	};
+
+	periph_clk: periph_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <500000000>;
+	};
+
+	sdio_clk: lcpll_ch2 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <200000000>;
+	};
+
+	axi81_clk: axi81_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	keypad_clk: keypad_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <31806>;
+	};
+
+	adc_clk: adc_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1562500>;
+	};
+
+	pwm_clk: pwm_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1000000>;
+	};
+
+	lcd_clk: mipipll_ch1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+};
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
new file mode 100644
index 0000000..a377ab2
--- /dev/null
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "brcm,cygnus";
+	model = "Broadcom Cygnus SoC";
+	interrupt-parent = <&gic>;
+
+	aliases {
+		serial0 = &uart3;
+		serial1 = &uart0;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200 earlyprintk debug";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <0x0>;
+		};
+	};
+
+	/include/ "bcm-cygnus-clock.dtsi"
+
+	amba {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "arm,amba-bus", "simple-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		wdt@18009000 {
+			 compatible = "arm,sp805" , "arm,primecell";
+			 reg = <0x18009000 0x1000>;
+			 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+			 clocks = <&axi81_clk>;
+			 clock-names = "apb_pclk";
+		};
+	};
+
+	uart3: serial@18023000 {
+		compatible = "snps,dw-apb-uart";
+		reg = <0x18023000 0x100>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <100000000>;
+		clocks = <&axi81_clk>;
+		status = "okay";
+	};
+
+	uart0: serial@18020000 {
+		compatible = "snps,dw-apb-uart";
+		reg = <0x18020000 0x100>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&axi81_clk>;
+		clock-frequency = <100000000>;
+		status = "okay";
+	};
+
+	gic: interrupt-controller@19021000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+		interrupt-controller;
+		reg = <0x19021000 0x1000>,
+		      <0x19020100 0x100>;
+	};
+
+	L2: l2-cache {
+		compatible = "arm,pl310-cache";
+		reg = <0x19022000 0x1000>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	timer@19020200 {
+		compatible = "arm,cortex-a9-global-timer";
+		reg = <0x19020200 0x100>;
+		interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&periph_clk>;
+	};
+
+};
diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts
new file mode 100644
index 0000000..c5188d7
--- /dev/null
+++ b/arch/arm/boot/dts/bcm911360_entphn.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "bcm-cygnus.dtsi"
+
+/ {
+	model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)";
+	compatible = "brcm,bcm11360", "brcm,cygnus";
+};
diff --git a/arch/arm/boot/dts/bcm911360k.dts b/arch/arm/boot/dts/bcm911360k.dts
new file mode 100644
index 0000000..866d1e1
--- /dev/null
+++ b/arch/arm/boot/dts/bcm911360k.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "bcm-cygnus.dtsi"
+
+/ {
+	model = "Cygnus SVK (BCM911360K)";
+	compatible = "brcm,bcm11360", "brcm,cygnus";
+};
diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts
new file mode 100644
index 0000000..8739751
--- /dev/null
+++ b/arch/arm/boot/dts/bcm958300k.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "bcm-cygnus.dtsi"
+
+/ {
+	model = "Cygnus SVK (BCM958300K)";
+	compatible = "brcm,bcm58300", "brcm,cygnus";
+};
-- 
1.7.9.5

[PATCH v5 5/6] MAINTAINERS: Entry for Cygnus/iproc arm architecture

[Scott Branden]

Acked-by: Jonathan Richardson <jonathar@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 MAINTAINERS |   15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index ee1bc5b..794804a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2125,6 +2125,21 @@ L:	linux-scsi@vger.kernel.org
 S:	Supported
 F:	drivers/scsi/bnx2i/
 
+BROADCOM CYGNUS/IPROC ARM ARCHITECTURE
+M:	Ray Jui <rjui@broadcom.com>
+M:	Scott Branden <sbranden@broadcom.com>
+L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L:	bcm-kernel-feedback-list@broadcom.com
+T:	git git://git.github.com/brcm/linux.git
+S:	Maintained
+F:	Documentation/devicetree/bindings/arm/bcm/cygnus.txt
+F:	Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
+F:	arch/arm/boot/dts/*cygnus*
+F:	arch/arm/boot/dts/bcm9113*
+F:	arch/arm/boot/dts/bcm9583*
+F:	arch/arm/configs/bcm_cygnus_defconfig
+F:	arch/arm/mach-bcm/bcm_cygnus.c
+
 BROADCOM KONA GPIO DRIVER
 M:	Ray Jui <rjui@broadcom.com>
 L:	bcm-kernel-feedback-list@broadcom.com
-- 
1.7.9.5

[PATCH v5 6/6] ARM: mach-bcm: Consolidate currently supported IPROC SoCs

[Scott Branden]

Move ARCH_BCM_5301X subarch under ARCH_IPROC architecture.
Additional IPROC chipsets that share a lot of commonality should be
added under ARCH_IPROC as well.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/mach-bcm/Kconfig |   37 ++++++++++++++++---------------------
 1 file changed, 16 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index ecc544a..08e7103 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -33,6 +33,22 @@ menu "iProc SoC based Machine types"
 		  which includes the following variants:
 		  BCM11300, BCM11320, BCM11350, BCM11360,
 		  BCM58300, BCM58302, BCM58303, BCM58305.
+
+	config ARCH_BCM_5301X
+		bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
+		select ARCH_BCM_IPROC
+		help
+		  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
+
+		  This is a network SoC line mostly used in home routers and
+		  wifi access points, it's internal name is Northstar.
+		  This inclused the following SoC: BCM53010, BCM53011, BCM53012,
+		  BCM53014, BCM53015, BCM53016, BCM53017, BCM53018, BCM4707,
+		  BCM4708 and BCM4709.
+
+		  Do not confuse this with the BCM4760 which is a totally
+		  different SoC or with the older BCM47XX and BCM53XX based
+		  network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
 endmenu
 
 config ARCH_BCM_MOBILE
@@ -108,27 +124,6 @@ config ARCH_BCM2835
 	  This enables support for the Broadcom BCM2835 SoC. This SoC is
 	  used in the Raspberry Pi and Roku 2 devices.
 
-config ARCH_BCM_5301X
-	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
-	select ARM_GIC
-	select CACHE_L2X0
-	select HAVE_ARM_SCU if SMP
-	select HAVE_ARM_TWD if SMP
-	select ARM_GLOBAL_TIMER
-	select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
-	help
-	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
-
-	  This is a network SoC line mostly used in home routers and
-	  wifi access points, it's internal name is Northstar.
-	  This inclused the following SoC: BCM53010, BCM53011, BCM53012,
-	  BCM53014, BCM53015, BCM53016, BCM53017, BCM53018, BCM4707,
-	  BCM4708 and BCM4709.
-
-	  Do not confuse this with the BCM4760 which is a totally
-	  different SoC or with the older BCM47XX and BCM53XX based
-	  network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
-
 config ARCH_BCM_63XX
 	bool "Broadcom BCM63xx DSL SoC" if ARCH_MULTI_V7
 	depends on MMU
-- 
1.7.9.5

[PATCH 1/1] MAINTAINERS: corrected bcm2835 search

[Scott Branden]

Corrected bcm2835 maintainer info by using N: to specify any files with
bcm2835 in are directed to the proper maintainer.
Also corrected minor mispelling of ARCHITECTURE in 2 comment locations.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 MAINTAINERS |    9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index b0cf8c9..801beb1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2056,17 +2056,14 @@ F:	arch/arm/configs/bcm_defconfig
 F:	drivers/mmc/host/sdhci-bcm-kona.c
 F:	drivers/clocksource/bcm_kona_timer.c
 
-BROADCOM BCM2835 ARM ARCHICTURE
+BROADCOM BCM2835 ARM ARCHITECTURE
 M:	Stephen Warren <swarren@wwwdotorg.org>
 L:	linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers)
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-rpi.git
 S:	Maintained
-F:	arch/arm/mach-bcm/board_bcm2835.c
-F:	arch/arm/boot/dts/bcm2835*
-F:	arch/arm/configs/bcm2835_defconfig
-F:	drivers/*/*bcm2835*
+N:	bcm2835
 
-BROADCOM BCM5301X ARM ARCHICTURE
+BROADCOM BCM5301X ARM ARCHITECTURE
 M:	Hauke Mehrtens <hauke@hauke-m.de>
 L:	linux-arm-kernel@lists.infradead.org
 S:	Maintained
-- 
1.7.9.5

[PATCH 1/1] mmc: sdhci-bcm2835: added quirk and removed udelay in write ops

[Scott Branden]

Added quirk SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 present in controller.
Removed udelay in write ops by using shadow registers for 16 bit
accesses to 32-bit registers (where necessary).
Optimized 32-bit operations when doing 8/16 register accesses.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/mmc/host/sdhci-bcm2835.c |  139 ++++++++++++++++++--------------------
 1 file changed, 66 insertions(+), 73 deletions(-)

diff --git a/drivers/mmc/host/sdhci-bcm2835.c b/drivers/mmc/host/sdhci-bcm2835.c
index 439d259..d967a4f 100644
--- a/drivers/mmc/host/sdhci-bcm2835.c
+++ b/drivers/mmc/host/sdhci-bcm2835.c
@@ -25,42 +25,28 @@
 #include "sdhci-pltfm.h"
 
 /*
- * 400KHz is max freq for card ID etc. Use that as min card clock. We need to
- * know the min to enable static calculation of max BCM2835_SDHCI_WRITE_DELAY.
- */
-#define MIN_FREQ 400000
-
-/*
  * The Arasan has a bugette whereby it may lose the content of successive
- * writes to registers that are within two SD-card clock cycles of each other
- * (a clock domain crossing problem). It seems, however, that the data
- * register does not have this problem, which is just as well - otherwise we'd
- * have to nobble the DMA engine too.
+ * writes to the same register that are within two SD-card clock cycles of
+ * each other (a clock domain crossing problem).  Problem does not happen with
+ * data.
+ * This wouldn't be a problem with the code except that we can only write the
+ * controller with 32-bit writes.  So two different 16-bit registers in the
+ * written back to back creates the problem.
  *
- * This should probably be dynamically calculated based on the actual card
- * frequency. However, this is the longest we'll have to wait, and doesn't
- * seem to slow access down too much, so the added complexity doesn't seem
- * worth it for now.
- *
- * 1/MIN_FREQ is (max) time per tick of eMMC clock.
- * 2/MIN_FREQ is time for two ticks.
- * Multiply by 1000000 to get uS per two ticks.
- * *1000000 for uSecs.
- * +1 for hack rounding.
+ * In reality, this only happens when a SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT
+ * are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND.
+ * The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so
+ * the work around can be further optimized. We can keep shadow values of
+ * BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued.
+ * Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed
+ * by the TRANSFER+COMMAND in another 32-bit write.
  */
-#define BCM2835_SDHCI_WRITE_DELAY	(((2 * 1000000) / MIN_FREQ) + 1)
 
-struct bcm2835_sdhci {
-	u32 shadow;
+struct bcm2835_sdhci_host {
+	u32 shadow_cmd;
+	u32 shadow_blk;
 };
 
-static void bcm2835_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
-{
-	writel(val, host->ioaddr + reg);
-
-	udelay(BCM2835_SDHCI_WRITE_DELAY);
-}
-
 static inline u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg)
 {
 	u32 val = readl(host->ioaddr + reg);
@@ -71,76 +57,83 @@ static inline u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg)
 	return val;
 }
 
-static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
-{
-	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
-	struct bcm2835_sdhci *bcm2835_host = pltfm_host->priv;
-	u32 oldval = (reg == SDHCI_COMMAND) ? bcm2835_host->shadow :
-		bcm2835_sdhci_readl(host, reg & ~3);
-	u32 word_num = (reg >> 1) & 1;
-	u32 word_shift = word_num * 16;
-	u32 mask = 0xffff << word_shift;
-	u32 newval = (oldval & ~mask) | (val << word_shift);
-
-	if (reg == SDHCI_TRANSFER_MODE)
-		bcm2835_host->shadow = newval;
-	else
-		bcm2835_sdhci_writel(host, newval, reg & ~3);
-}
-
 static u16 bcm2835_sdhci_readw(struct sdhci_host *host, int reg)
 {
-	u32 val = bcm2835_sdhci_readl(host, (reg & ~3));
-	u32 word_num = (reg >> 1) & 1;
-	u32 word_shift = word_num * 16;
-	u32 word = (val >> word_shift) & 0xffff;
-
+	u32 val = bcm2835_sdhci_readl(host->ioaddr, (reg & ~3));
+	u16 word = val >> (reg << 3 & 0x18) & 0xffff;
 	return word;
 }
 
-static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
+static u8 bcm2835_sdhci_readb(struct sdhci_host *host, int reg)
 {
-	u32 oldval = bcm2835_sdhci_readl(host, reg & ~3);
-	u32 byte_num = reg & 3;
-	u32 byte_shift = byte_num * 8;
-	u32 mask = 0xff << byte_shift;
-	u32 newval = (oldval & ~mask) | (val << byte_shift);
+	u32 val = bcm2835_sdhci_readl(host->ioaddr, (reg & ~3));
+	u8 byte = val >> (reg << 3 & 0x18) & 0xff;
+	return byte;
+}
 
-	bcm2835_sdhci_writel(host, newval, reg & ~3);
+static void bcm2835_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
+{
+	writel(val, host->ioaddr + reg);
 }
 
-static u8 bcm2835_sdhci_readb(struct sdhci_host *host, int reg)
+static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 {
-	u32 val = bcm2835_sdhci_readl(host, (reg & ~3));
-	u32 byte_num = reg & 3;
-	u32 byte_shift = byte_num * 8;
-	u32 byte = (val >> byte_shift) & 0xff;
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct bcm2835_sdhci_host *bcm2835_host = pltfm_host->priv;
+	u32 word_shift = reg << 3 & 0x18;
+	u32 mask = 0xffff << word_shift;
+	u32 oldval;
+	u32 newval;
+
+	if (reg == SDHCI_COMMAND) {
+		if (bcm2835_host->shadow_blk != 0) {
+			writel(bcm2835_host->shadow_blk,
+			       host->ioaddr + SDHCI_BLOCK_SIZE);
+			bcm2835_host->shadow_blk = 0;
+		}
+		oldval = bcm2835_host->shadow_cmd;
+	} else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
+		oldval = bcm2835_host->shadow_blk;
+	} else {
+		oldval = readl(host->ioaddr + (reg & ~3));
+	}
+	newval = (oldval & ~mask) | (val << word_shift);
 
-	return byte;
+	if (reg == SDHCI_TRANSFER_MODE)
+		bcm2835_host->shadow_cmd = newval;
+	else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT)
+		bcm2835_host->shadow_blk = newval;
+	else
+		writel(newval, host->ioaddr + (reg & ~3));
 }
 
-static unsigned int bcm2835_sdhci_get_min_clock(struct sdhci_host *host)
+static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 {
-	return MIN_FREQ;
+	u32 oldval = readl(host->ioaddr + (reg & ~3));
+	u32 byte_shift = reg << 3 & 0x18;
+	u32 mask = 0xff << byte_shift;
+	u32 newval = (oldval & ~mask) | (val << byte_shift);
+
+	writel(newval, host->ioaddr + (reg & ~3));
 }
 
 static const struct sdhci_ops bcm2835_sdhci_ops = {
-	.write_l = bcm2835_sdhci_writel,
-	.write_w = bcm2835_sdhci_writew,
-	.write_b = bcm2835_sdhci_writeb,
 	.read_l = bcm2835_sdhci_readl,
 	.read_w = bcm2835_sdhci_readw,
 	.read_b = bcm2835_sdhci_readb,
+	.write_l = bcm2835_sdhci_writel,
+	.write_w = bcm2835_sdhci_writew,
+	.write_b = bcm2835_sdhci_writeb,
 	.set_clock = sdhci_set_clock,
 	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
-	.get_min_clock = bcm2835_sdhci_get_min_clock,
 	.set_bus_width = sdhci_set_bus_width,
 	.reset = sdhci_reset,
 	.set_uhs_signaling = sdhci_set_uhs_signaling,
 };
 
 static const struct sdhci_pltfm_data bcm2835_sdhci_pdata = {
-	.quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
+	.quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 |
+		  SDHCI_QUIRK_BROKEN_CARD_DETECTION |
 		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
 	.ops = &bcm2835_sdhci_ops,
 };
@@ -148,7 +141,7 @@ static const struct sdhci_pltfm_data bcm2835_sdhci_pdata = {
 static int bcm2835_sdhci_probe(struct platform_device *pdev)
 {
 	struct sdhci_host *host;
-	struct bcm2835_sdhci *bcm2835_host;
+	struct bcm2835_sdhci_host *bcm2835_host;
 	struct sdhci_pltfm_host *pltfm_host;
 	int ret;
 
-- 
1.7.9.5

Re: [PATCH 1/1] MAINTAINERS: corrected bcm2835 search

[Stephen Warren]

On 10/15/2014 09:54 AM, Scott Branden wrote:
> Corrected bcm2835 maintainer info by using N: to specify any files with
> bcm2835 in are directed to the proper maintainer.
> Also corrected minor mispelling of ARCHITECTURE in 2 comment locations.

Acked-by: Stephen Warren <swarren@wwwdotorg.org>

Who should apply this? I guess I can forward it to arm-soc if you want 
me to take it.

Re: [PATCH 1/1] mmc: sdhci-bcm2835: added quirk and removed udelay in write ops

[Stephen Warren]

On 10/14/2014 08:01 PM, Scott Branden wrote:
> Added quirk SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 present in controller.
> Removed udelay in write ops by using shadow registers for 16 bit
> accesses to 32-bit registers (where necessary).
> Optimized 32-bit operations when doing 8/16 register accesses.

I'm going to assume this is identical to the patch you sent 8/15? So,
I'll ignore this copy...

Re: [PATCH 1/1] mmc: sdhci-bcm2835: added quirk and removed udelay in write ops

[Stephen Warren]

On 10/15/2014 10:43 AM, Scott Branden wrote:
> Added quirk SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 present in controller.
> Removed udelay in write ops by using shadow registers for 16 bit
> accesses to 32-bit registers (where necessary).
> Optimized 32-bit operations when doing 8/16 register accesses.

That's 2 or 3 unrelated changes. They'd be better as separate patches,
so that any issues that arise can be bisected down to the smaller changes.

> diff --git a/drivers/mmc/host/sdhci-bcm2835.c b/drivers/mmc/host/sdhci-bcm2835.c

>  /*
>   * The Arasan has a bugette whereby it may lose the content of successive
> + * writes to the same register that are within two SD-card clock cycles of
> + * each other (a clock domain crossing problem).  Problem does not happen with
                                                    ^ The?
See right >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> ^

> + * data.

Blank line to separate the paragraphs here, to be consistent with the
other paragraph break below?

> + * This wouldn't be a problem with the code except that we can only write the
> + * controller with 32-bit writes.  So two different 16-bit registers in the
> + * written back to back creates the problem.
>   *
> + * In reality, this only happens when a SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT
> + * are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND.

That seems like a rather risky assertion. Even if it's perfectly true
with the MMC core code right now, does the MMC core document a guarantee
that this will always be true? Even if we optimize the WAR for the issue
as you've done, I think we should still have code that validates that
the same register is never written back-to-back to detect this likely
very hard-to-debug problem.

> + * The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so
> + * the work around can be further optimized. We can keep shadow values of
> + * BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued.
> + * Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed
> + * by the TRANSFER+COMMAND in another 32-bit write.
>   */

After this patch, the entire WAR for this issue is contained within
bcm2835_sdhci_writew(). It might be a good idea to move the comment next
to that function so it's more at hand to explain the code that's there.
Or at least add a comment to that function the to mention the location
of the explanation for the complex code.

>  static inline u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg)
>  {
>  	u32 val = readl(host->ioaddr + reg);
> @@ -71,76 +57,83 @@ static inline u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg)
>  	return val;
>  }
>  
> -static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
> -{
... (entire function deleted)
> -}

This patch could be a lot smaller if it didn't re-order the functions at
the same time. It makes the patch harder to understand. If you must
re-order the functions, perhaps make that a separate patch that does
nothing else, so that the actual code changes are easier to see?

>  static u16 bcm2835_sdhci_readw(struct sdhci_host *host, int reg)
>  {
> -	u32 val = bcm2835_sdhci_readl(host, (reg & ~3));
> -	u32 word_num = (reg >> 1) & 1;
> -	u32 word_shift = word_num * 16;
> -	u32 word = (val >> word_shift) & 0xffff;
> -
> +	u32 val = bcm2835_sdhci_readl(host->ioaddr, (reg & ~3));

The change from host to host->ioaddr ends up passing the wrong value to
bcm2835_sdhci_readl(). This causes the kernel to crash during boot.

The compiler doesn't warn about this because host->ioaddr is void, so
can be automatically converted to struct sdhci_host *.

> +	u16 word = val >> (reg << 3 & 0x18) & 0xffff;
>  	return word;
>  }

To be honest, I think the existing code is a bit clearer, since it uses
variables with names to explain all the intermediate values. Assuming
the compiler is competent (which admittedly I haven't checked) I would
expect the same code to be generated either way, or at least something
pretty similar. Did you measure the benefit of the optimization?

> +static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
>  {
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct bcm2835_sdhci_host *bcm2835_host = pltfm_host->priv;
> +	u32 word_shift = reg << 3 & 0x18;
> +	u32 mask = 0xffff << word_shift;
> +	u32 oldval;
> +	u32 newval;
> +
> +	if (reg == SDHCI_COMMAND) {
> +		if (bcm2835_host->shadow_blk != 0) {
> +			writel(bcm2835_host->shadow_blk,
> +			       host->ioaddr + SDHCI_BLOCK_SIZE);
> +			bcm2835_host->shadow_blk = 0;
> +		}

Is it absolutely guaranteed that there's never a need to write 0 to that
register? I can see that no data transfer command is likely to transfer
0 blocks. I assume no other type of command uses that register as a
parameter?

Re: [PATCH 1/1] mmc: sdhci-bcm2835: added quirk and removed udelay in write ops

[Scott Branden]

Great review - thanks.

On 14-10-17 07:37 PM, Stephen Warren wrote:
> On 10/15/2014 10:43 AM, Scott Branden wrote:
>> Added quirk SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 present in controller.
>> Removed udelay in write ops by using shadow registers for 16 bit
>> accesses to 32-bit registers (where necessary).
>> Optimized 32-bit operations when doing 8/16 register accesses.
>
> That's 2 or 3 unrelated changes. They'd be better as separate patches,
> so that any issues that arise can be bisected down to the smaller changes.
OK - I will split into smaller patches to bisect and understand better.
>
>> diff --git a/drivers/mmc/host/sdhci-bcm2835.c b/drivers/mmc/host/sdhci-bcm2835.c
>
>>   /*
>>    * The Arasan has a bugette whereby it may lose the content of successive
>> + * writes to the same register that are within two SD-card clock cycles of
>> + * each other (a clock domain crossing problem).  Problem does not happen with
>                                                      ^ The?
> See right >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> ^
>
>> + * data.
>
> Blank line to separate the paragraphs here, to be consistent with the
> other paragraph break below?
I'll clean up the comment some more.
>
>> + * This wouldn't be a problem with the code except that we can only write the
>> + * controller with 32-bit writes.  So two different 16-bit registers in the
>> + * written back to back creates the problem.
>>    *
>> + * In reality, this only happens when a SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT
>> + * are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND.
>
> That seems like a rather risky assertion. Even if it's perfectly true
> with the MMC core code right now, does the MMC core document a guarantee
> that this will always be true? Even if we optimize the WAR for the issue
> as you've done, I think we should still have code that validates that
> the same register is never written back-to-back to detect this likely
> very hard-to-debug problem.
You're right - nothing in life is guaranteed.  We had test code for 
this.  I'll add a config option (default on) that verifies back to back 
writes do not occur.
>
>> + * The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so
>> + * the work around can be further optimized. We can keep shadow values of
>> + * BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued.
>> + * Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed
>> + * by the TRANSFER+COMMAND in another 32-bit write.
>>    */
>
> After this patch, the entire WAR for this issue is contained within
> bcm2835_sdhci_writew(). It might be a good idea to move the comment next
> to that function so it's more at hand to explain the code that's there.
> Or at least add a comment to that function the to mention the location
> of the explanation for the complex code.
ok, I'll clean up the comment a little more too.
>
>>   static inline u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg)
>>   {
>>   	u32 val = readl(host->ioaddr + reg);
>> @@ -71,76 +57,83 @@ static inline u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg)
>>   	return val;
>>   }
>>
>> -static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
>> -{
> ... (entire function deleted)
>> -}
>
> This patch could be a lot smaller if it didn't re-order the functions at
> the same time. It makes the patch harder to understand. If you must
> re-order the functions, perhaps make that a separate patch that does
> nothing else, so that the actual code changes are easier to see?
ok
>
>>   static u16 bcm2835_sdhci_readw(struct sdhci_host *host, int reg)
>>   {
>> -	u32 val = bcm2835_sdhci_readl(host, (reg & ~3));
>> -	u32 word_num = (reg >> 1) & 1;
>> -	u32 word_shift = word_num * 16;
>> -	u32 word = (val >> word_shift) & 0xffff;
>> -
>> +	u32 val = bcm2835_sdhci_readl(host->ioaddr, (reg & ~3));
>
> The change from host to host->ioaddr ends up passing the wrong value to
> bcm2835_sdhci_readl(). This causes the kernel to crash during boot.
I see that now.  Will fix - unfortunately I ported from an existing 
driver that doesn't need the bcm2835_shdci_readl function.
>
> The compiler doesn't warn about this because host->ioaddr is void, so
> can be automatically converted to struct sdhci_host *.
>
>> +	u16 word = val >> (reg << 3 & 0x18) & 0xffff;
>>   	return word;
>>   }
>
> To be honest, I think the existing code is a bit clearer, since it uses
> variables with names to explain all the intermediate values. Assuming
> the compiler is competent (which admittedly I haven't checked) I would
> expect the same code to be generated either way, or at least something
> pretty similar. Did you measure the benefit of the optimization?
By optimize I meant use the same bit calculation instead of doing 
different calculations for the same operation.  I'll create a macro to 
make it clearer to see.
>
>> +static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
>>   {
>> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>> +	struct bcm2835_sdhci_host *bcm2835_host = pltfm_host->priv;
>> +	u32 word_shift = reg << 3 & 0x18;
>> +	u32 mask = 0xffff << word_shift;
>> +	u32 oldval;
>> +	u32 newval;
>> +
>> +	if (reg == SDHCI_COMMAND) {
>> +		if (bcm2835_host->shadow_blk != 0) {
>> +			writel(bcm2835_host->shadow_blk,
>> +			       host->ioaddr + SDHCI_BLOCK_SIZE);
>> +			bcm2835_host->shadow_blk = 0;
>> +		}
>
> Is it absolutely guaranteed that there's never a need to write 0 to that
> register? I can see that no data transfer command is likely to transfer
> 0 blocks. I assume no other type of command uses that register as a
> parameter?
Correct.
>

Re: [PATCH v5 1/6] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Arnd Bergmann]

On Tuesday 14 October 2014 19:58:51 Scott Branden wrote:
>  if ARCH_BCM
>  
> +menu "iProc SoC based Machine types"
> +       config ARCH_BCM_IPROC
> +               bool
> +               select ARM_GIC
> +               select CACHE_L2X0
> +               select HAVE_ARM_SCU if SMP
> +               select HAVE_ARM_TWD if SMP
> +               select ARM_GLOBAL_TIMER
> +
> +               select CLKSRC_MMIO
> +               select ARCH_REQUIRE_GPIOLIB
> +               select ARM_AMBA
> +               select PINCTRL
> +               help
> +                 This enables support for systems based on Broadcom IPROC architected SoCs.
> +                 The IPROC complex contains one or more ARM CPUs along with common
> +                 core periperals. Application specific SoCs are created by adding a
> +                 uArchitecture containing peripherals outside of the IPROC complex.
> +                 Currently supported SoCs are Cygnus.
> +
> +       config ARCH_BCM_CYGNUS
> +               bool "Broadcom Cygnus Support" if ARCH_MULTI_V7

You still have a three-level menu structure. Please fix.

> +static const char const *bcm_cygnus_dt_compat[] = {
> +       "brcm,cygnus",
> +       NULL,
> +};
> +
> +DT_MACHINE_START(BCM_CYGNUS_DT, "Broadcom Cygnus SoC")
> +       .l2c_aux_val    = 0,
> +       .l2c_aux_mask   = ~0,
> +       .dt_compat = bcm_cygnus_dt_compat,
> +MACHINE_END
> 
This looks good.

	Arnd

Re: [PATCH v5 1/6] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Scott Branden]

On 14-10-20 12:55 PM, Arnd Bergmann wrote:
> On Tuesday 14 October 2014 19:58:51 Scott Branden wrote:
>>   if ARCH_BCM
>>
>> +menu "iProc SoC based Machine types"
>> +       config ARCH_BCM_IPROC
>> +               bool
>> +               select ARM_GIC
>> +               select CACHE_L2X0
>> +               select HAVE_ARM_SCU if SMP
>> +               select HAVE_ARM_TWD if SMP
>> +               select ARM_GLOBAL_TIMER
>> +
>> +               select CLKSRC_MMIO
>> +               select ARCH_REQUIRE_GPIOLIB
>> +               select ARM_AMBA
>> +               select PINCTRL
>> +               help
>> +                 This enables support for systems based on Broadcom IPROC architected SoCs.
>> +                 The IPROC complex contains one or more ARM CPUs along with common
>> +                 core periperals. Application specific SoCs are created by adding a
>> +                 uArchitecture containing peripherals outside of the IPROC complex.
>> +                 Currently supported SoCs are Cygnus.
>> +
>> +       config ARCH_BCM_CYGNUS
>> +               bool "Broadcom Cygnus Support" if ARCH_MULTI_V7
>
> You still have a three-level menu structure. Please fix.

Hi Arnd, we have ARCH_BCM->ARCH_BCM_CYGNUS.

ARCH_BCM_IPROC is silent and selected by ARCH_BCM_CYGNUS.  This was the 
change made between v3 and v5.

Is there something else to be done here?
>
>> +static const char const *bcm_cygnus_dt_compat[] = {
>> +       "brcm,cygnus",
>> +       NULL,
>> +};
>> +
>> +DT_MACHINE_START(BCM_CYGNUS_DT, "Broadcom Cygnus SoC")
>> +       .l2c_aux_val    = 0,
>> +       .l2c_aux_mask   = ~0,
>> +       .dt_compat = bcm_cygnus_dt_compat,
>> +MACHINE_END
>>
> This looks good.
>
> 	Arnd
>

Re: [PATCH v5 1/6] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Arnd Bergmann]

On Monday 20 October 2014 15:59:45 Scott Branden wrote:
> On 14-10-20 12:55 PM, Arnd Bergmann wrote:
> > On Tuesday 14 October 2014 19:58:51 Scott Branden wrote:
> >>   if ARCH_BCM
> >>
> >> +menu "iProc SoC based Machine types"
> >> +       config ARCH_BCM_IPROC
> >> +               bool
> >> +               select ARM_GIC
> >> +               select CACHE_L2X0
> >> +               select HAVE_ARM_SCU if SMP
> >> +               select HAVE_ARM_TWD if SMP
> >> +               select ARM_GLOBAL_TIMER
> >> +
> >> +               select CLKSRC_MMIO
> >> +               select ARCH_REQUIRE_GPIOLIB
> >> +               select ARM_AMBA
> >> +               select PINCTRL
> >> +               help
> >> +                 This enables support for systems based on Broadcom IPROC architected SoCs.
> >> +                 The IPROC complex contains one or more ARM CPUs along with common
> >> +                 core periperals. Application specific SoCs are created by adding a
> >> +                 uArchitecture containing peripherals outside of the IPROC complex.
> >> +                 Currently supported SoCs are Cygnus.
> >> +
> >> +       config ARCH_BCM_CYGNUS
> >> +               bool "Broadcom Cygnus Support" if ARCH_MULTI_V7
> >
> > You still have a three-level menu structure. Please fix.
> 
> Hi Arnd, we have ARCH_BCM->ARCH_BCM_CYGNUS.
> 
> ARCH_BCM_IPROC is silent and selected by ARCH_BCM_CYGNUS.  This was the 
> change made between v3 and v5.
> 
> Is there something else to be done here?
> 

You have

	"Broadcom SoC Support" 
		"iProc SoC based Machine types"
			 "Broadcom Cygnus Support"

Get rid of one of them.

	Arnd

Re: [PATCH v5 1/6] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Scott Branden]

On 14-10-20 10:48 PM, Arnd Bergmann wrote:
> On Monday 20 October 2014 15:59:45 Scott Branden wrote:
>> On 14-10-20 12:55 PM, Arnd Bergmann wrote:
>>> On Tuesday 14 October 2014 19:58:51 Scott Branden wrote:
>>>>    if ARCH_BCM
>>>>
>>>> +menu "iProc SoC based Machine types"
>>>> +       config ARCH_BCM_IPROC
>>>> +               bool
>>>> +               select ARM_GIC
>>>> +               select CACHE_L2X0
>>>> +               select HAVE_ARM_SCU if SMP
>>>> +               select HAVE_ARM_TWD if SMP
>>>> +               select ARM_GLOBAL_TIMER
>>>> +
>>>> +               select CLKSRC_MMIO
>>>> +               select ARCH_REQUIRE_GPIOLIB
>>>> +               select ARM_AMBA
>>>> +               select PINCTRL
>>>> +               help
>>>> +                 This enables support for systems based on Broadcom IPROC architected SoCs.
>>>> +                 The IPROC complex contains one or more ARM CPUs along with common
>>>> +                 core periperals. Application specific SoCs are created by adding a
>>>> +                 uArchitecture containing peripherals outside of the IPROC complex.
>>>> +                 Currently supported SoCs are Cygnus.
>>>> +
>>>> +       config ARCH_BCM_CYGNUS
>>>> +               bool "Broadcom Cygnus Support" if ARCH_MULTI_V7
>>>
>>> You still have a three-level menu structure. Please fix.
>>
>> Hi Arnd, we have ARCH_BCM->ARCH_BCM_CYGNUS.
>>
>> ARCH_BCM_IPROC is silent and selected by ARCH_BCM_CYGNUS.  This was the
>> change made between v3 and v5.
>>
>> Is there something else to be done here?
>>
>
> You have
>
> 	"Broadcom SoC Support"
> 		"iProc SoC based Machine types"
> 			 "Broadcom Cygnus Support"
OK, I will remove the "iProc SoC based Machine types".  This was 
grouping all iProc based SoCs under one menu and parallels what the 
existing "Broadcom Mobile Soc Support" menu does.
I can create another patch removing the "Broadcom Mobile SoC Support" 
menu if the ARM Maintainer now want all Broadcom devices are supposed to 
be contained in a single level?
>
> Get rid of one of them.
>
> 	Arnd
>

[PATCH v6 0/6] Add initial support for Broadcom Cygnus SoC

[Scott Branden]

This patchset contains initial support for Broadcom's Cygnus SoC based on our
iProc architecture. Initial support is minimal and includes just the mach
platform code, clock driver, and a basic device tree configuration. Peripheral
drivers will be submitted soon, as will device tree configurations for other
Cygnus board variants.

Changes from v5:
 - removed one level of menu used in mach-bcm/Kconfig
 - changed MAINTAINERS to use N: to support all files associated with iproc
   and cygnus going forward
 - updated bcm_cygnus_defconfig to remove some DEBUG options that greatly
   hamper performance

Changes from v4:
 - simple clock tree used. reworked clock driver will be submitted later
 - fixed MAINTAINERS patchset error
 - removed DEBUG_UART_8250 Kconfig.debug legacy support
 - made ARCH_BCM_IPROC a silent Kconfig option
 - removed multi_v7_defconfig as it is not needed at this time, can
   support in future patchset but does not seem optimal configs for our
   current usage.
 
Changes from v3:
 - restart functionality removed.  Will be added in a different patchset
   in drivers/power
 - removed NEON init sequence.  Will be moved to bootloader
 - cleaned up Kconfigs for ARCH_BCM_CYGNUS by removing unnecessary selects
 - consolidated ARCH_BCM_IPROC with select from ARCH_BCM_CYGNUS and
   ARCH_BCM5301X
 - removed bcm911360_entphn binding
 - added documentation for SoCs currently supported in Cygnus family

Changes from v2:
 - rebased to 3.17 kernel

Changes from v1:
 - Address code review comments as per previous responses.
 - Copyright headers updated to remove Broadcom URL.
 - mach platform code still contains hard coded addresses. These address are
   the same for all Cygnus variants. Could you please provide guidance on where
   they should go if you would still like them changed.  There does not seem to
   be a reason to change them to device tree as they do not change.

Jonathan Richardson (3):
  ARM: cygnus: Initial support for Broadcom Cygnus SoC
  dt-bindings: Document Broadcom Cygnus SoC and clocks
  ARM: cygnus defconfig : Initial defconfig for Broadcom Cygnus SoC

Scott Branden (3):
  ARM: dts: Enable Broadcom Cygnus SoC
  MAINTAINERS: Entry for Cygnus/iproc arm architecture
  ARM: mach-bcm: Consolidate currently supported IPROC SoCs

 .../devicetree/bindings/arm/bcm/cygnus.txt         |   31 +++
 .../devicetree/bindings/clock/bcm-cygnus-clock.txt |   34 +++
 MAINTAINERS                                        |   14 ++
 arch/arm/boot/dts/Makefile                         |    4 +
 arch/arm/boot/dts/bcm-cygnus-clock.dtsi            |   73 ++++++
 arch/arm/boot/dts/bcm-cygnus.dtsi                  |  109 +++++++++
 arch/arm/boot/dts/bcm911360_entphn.dts             |   22 ++
 arch/arm/boot/dts/bcm911360k.dts                   |   22 ++
 arch/arm/boot/dts/bcm958300k.dts                   |   22 ++
 arch/arm/configs/bcm_cygnus_defconfig              |  237 ++++++++++++++++++++
 arch/arm/mach-bcm/Kconfig                          |   65 ++++--
 arch/arm/mach-bcm/Makefile                         |    3 +
 arch/arm/mach-bcm/bcm_cygnus.c                     |   26 +++
 13 files changed, 641 insertions(+), 21 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/cygnus.txt
 create mode 100644 Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
 create mode 100644 arch/arm/boot/dts/bcm-cygnus-clock.dtsi
 create mode 100644 arch/arm/boot/dts/bcm-cygnus.dtsi
 create mode 100644 arch/arm/boot/dts/bcm911360_entphn.dts
 create mode 100644 arch/arm/boot/dts/bcm911360k.dts
 create mode 100644 arch/arm/boot/dts/bcm958300k.dts
 create mode 100644 arch/arm/configs/bcm_cygnus_defconfig
 create mode 100644 arch/arm/mach-bcm/bcm_cygnus.c

-- 
1.7.9.5

[PATCH v6 1/6] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Scott Branden]

From: Jonathan Richardson <jonathar@broadcom.com>

Adds initial support for the Cygnus SoC based on Broadcom’s iProc series.
Move ARCH_BCM_5301x under the ARCH_BCM_IPROC architecture.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Desmond Liu <desmondl@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/mach-bcm/Kconfig      |   28 ++++++++++++++++++++++++++++
 arch/arm/mach-bcm/Makefile     |    3 +++
 arch/arm/mach-bcm/bcm_cygnus.c |   26 ++++++++++++++++++++++++++
 3 files changed, 57 insertions(+)
 create mode 100644 arch/arm/mach-bcm/bcm_cygnus.c

diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 2abad74..f5e638e 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -5,6 +5,34 @@ menuconfig ARCH_BCM
 
 if ARCH_BCM
 
+config ARCH_BCM_IPROC
+	bool
+	select ARM_GIC
+	select CACHE_L2X0
+	select HAVE_ARM_SCU if SMP
+	select HAVE_ARM_TWD if SMP
+	select ARM_GLOBAL_TIMER
+
+	select CLKSRC_MMIO
+	select ARCH_REQUIRE_GPIOLIB
+	select ARM_AMBA
+	select PINCTRL
+	help
+	  This enables support for systems based on Broadcom IPROC architected SoCs.
+	  The IPROC complex contains one or more ARM CPUs along with common
+	  core periperals. Application specific SoCs are created by adding a
+	  uArchitecture containing peripherals outside of the IPROC complex.
+	  Currently supported SoCs are Cygnus.
+
+config ARCH_BCM_CYGNUS
+	bool "Broadcom Cygnus Support" if ARCH_MULTI_V7
+	select ARCH_BCM_IPROC
+	help
+	  Enable support for the Cygnus family,
+	  which includes the following variants:
+	  BCM11300, BCM11320, BCM11350, BCM11360,
+	  BCM58300, BCM58302, BCM58303, BCM58305.
+
 config ARCH_BCM_MOBILE
 	bool "Broadcom Mobile SoC Support" if ARCH_MULTI_V7
 	select ARCH_REQUIRE_GPIOLIB
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 300ae4b..34d45ba 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -10,6 +10,9 @@
 # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
 
+# Cygnus
+obj-$(CONFIG_ARCH_BCM_CYGNUS) +=  bcm_cygnus.o
+
 # BCM281XX
 obj-$(CONFIG_ARCH_BCM_281XX)	+= board_bcm281xx.o
 
diff --git a/arch/arm/mach-bcm/bcm_cygnus.c b/arch/arm/mach-bcm/bcm_cygnus.c
new file mode 100644
index 0000000..41b4933
--- /dev/null
+++ b/arch/arm/mach-bcm/bcm_cygnus.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <asm/mach/arch.h>
+
+static const char const *bcm_cygnus_dt_compat[] = {
+	"brcm,cygnus",
+	NULL,
+};
+
+DT_MACHINE_START(BCM_CYGNUS_DT, "Broadcom Cygnus SoC")
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
+	.dt_compat = bcm_cygnus_dt_compat,
+MACHINE_END
-- 
1.7.9.5

[PATCH v6 2/6] dt-bindings: Document Broadcom Cygnus SoC and clocks

[Scott Branden]

From: Jonathan Richardson <jonathar@broadcom.com>

Reviewed-by: Arun Parameswaran <aparames@broadcom.com>
Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 .../devicetree/bindings/arm/bcm/cygnus.txt         |   31 ++++++++++++++++++
 .../devicetree/bindings/clock/bcm-cygnus-clock.txt |   34 ++++++++++++++++++++
 2 files changed, 65 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/cygnus.txt
 create mode 100644 Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt

diff --git a/Documentation/devicetree/bindings/arm/bcm/cygnus.txt b/Documentation/devicetree/bindings/arm/bcm/cygnus.txt
new file mode 100644
index 0000000..4c77169
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/cygnus.txt
@@ -0,0 +1,31 @@
+Broadcom Cygnus device tree bindings
+------------------------------------
+
+
+Boards with Cygnus SoCs shall have the following properties:
+
+Required root node property:
+
+BCM11300
+compatible = "brcm,bcm11300", "brcm,cygnus";
+
+BCM11320
+compatible = "brcm,bcm11320", "brcm,cygnus";
+
+BCM11350
+compatible = "brcm,bcm11350", "brcm,cygnus";
+
+BCM11360
+compatible = "brcm,bcm11360", "brcm,cygnus";
+
+BCM58300
+compatible = "brcm,bcm58300", "brcm,cygnus";
+
+BCM58302
+compatible = "brcm,bcm58302", "brcm,cygnus";
+
+BCM58303
+compatible = "brcm,bcm58303", "brcm,cygnus";
+
+BCM58305
+compatible = "brcm,bcm58305", "brcm,cygnus";
diff --git a/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt b/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
new file mode 100644
index 0000000..00d26ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
@@ -0,0 +1,34 @@
+Broadcom Cygnus Clocks
+
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Currently various "fixed" clocks are declared for peripheral drivers that use
+the common clock framework to reference their core clocks. Proper support of
+these clocks will be added later
+
+Device tree example:
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		osc: oscillator {
+			compatible = "fixed-clock";
+			#clock-cells = <1>;
+			clock-frequency = <25000000>;
+		};
+
+		apb_clk: apb_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <1000000000>;
+		};
+
+		periph_clk: periph_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <500000000>;
+		};
+	};
-- 
1.7.9.5

[PATCH v6 3/6] ARM: cygnus defconfig : Initial defconfig for Broadcom Cygnus SoC

[Scott Branden]

From: Jonathan Richardson <jonathar@broadcom.com>

This defconfig is utilized so a customer or developer can understand
what kernel drivers are utilized by the Cygnus SoC.  It also enables
debug configs which should be disabled if optimal performance is
desired.

Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/configs/bcm_cygnus_defconfig |  237 +++++++++++++++++++++++++++++++++
 1 file changed, 237 insertions(+)
 create mode 100644 arch/arm/configs/bcm_cygnus_defconfig

diff --git a/arch/arm/configs/bcm_cygnus_defconfig b/arch/arm/configs/bcm_cygnus_defconfig
new file mode 100644
index 0000000..9ad77a8
--- /dev/null
+++ b/arch/arm/configs/bcm_cygnus_defconfig
@@ -0,0 +1,237 @@
+CONFIG_KERNEL_XZ=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_FHANDLE=y
+CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=19
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_BLK_CGROUP=y
+CONFIG_NAMESPACES=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_JUMP_LABEL=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BCM_CYGNUS=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_PCI=y
+CONFIG_PCI_DEBUG=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+# CONFIG_COMPACTION is not set
+# CONFIG_ATAGS is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_TCP_CONG_ADVANCED=y
+# CONFIG_TCP_CONG_BIC is not set
+# CONFIG_TCP_CONG_WESTWOOD is not set
+# CONFIG_TCP_CONG_HTCP is not set
+CONFIG_IPV6=y
+# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET6_XFRM_MODE_BEET is not set
+# CONFIG_IPV6_SIT is not set
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+CONFIG_NETFILTER=y
+# CONFIG_BRIDGE_NETFILTER is not set
+CONFIG_NF_CONNTRACK=y
+# CONFIG_NF_CONNTRACK_PROCFS is not set
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_RAW=y
+CONFIG_NF_CONNTRACK_IPV6=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_MATCH_AH=y
+CONFIG_IP6_NF_MATCH_EUI64=y
+CONFIG_IP6_NF_MATCH_FRAG=y
+CONFIG_IP6_NF_MATCH_OPTS=y
+CONFIG_IP6_NF_MATCH_IPV6HEADER=y
+CONFIG_IP6_NF_MATCH_MH=y
+CONFIG_IP6_NF_MATCH_RT=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_IP6_NF_RAW=y
+CONFIG_BRIDGE=y
+# CONFIG_BRIDGE_IGMP_SNOOPING is not set
+CONFIG_VLAN_8021Q=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_FQ_CODEL=y
+CONFIG_CFG80211=y
+# CONFIG_CFG80211_DEFAULT_PS is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_RFKILL=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_PHYLIB=y
+CONFIG_BROADCOM_PHY=y
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
+CONFIG_I2C_SMBUS=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=y
+# CONFIG_USB_GSPCA is not set
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_DEBUG=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_SOC=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_RTC_CLASS=y
+CONFIG_PWM=y
+CONFIG_EXT4_FS=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_UBIFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_INFO=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_OBJECTS=y
+CONFIG_DEBUG_OBJECTS_RCU_HEAD=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=110
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_SCHEDSTATS=y
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_ATOMIC_SLEEP=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_UART_8250=y
+CONFIG_DEBUG_UART_PHYS=0x18023000
+CONFIG_DEBUG_UART_VIRT=0xf1023000
+CONFIG_EARLY_PRINTK=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
-- 
1.7.9.5

[PATCH v6 4/6] ARM: dts: Enable Broadcom Cygnus SoC

[Scott Branden]

DT files to enable cygnus consisting on reference designs
and cygnus core configuration.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Arun Parameswaran <aparames@broadcom.com>
Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/boot/dts/Makefile              |    4 ++
 arch/arm/boot/dts/bcm-cygnus-clock.dtsi |   73 +++++++++++++++++++++
 arch/arm/boot/dts/bcm-cygnus.dtsi       |  109 +++++++++++++++++++++++++++++++
 arch/arm/boot/dts/bcm911360_entphn.dts  |   22 +++++++
 arch/arm/boot/dts/bcm911360k.dts        |   22 +++++++
 arch/arm/boot/dts/bcm958300k.dts        |   22 +++++++
 6 files changed, 252 insertions(+)
 create mode 100644 arch/arm/boot/dts/bcm-cygnus-clock.dtsi
 create mode 100644 arch/arm/boot/dts/bcm-cygnus.dtsi
 create mode 100644 arch/arm/boot/dts/bcm911360_entphn.dts
 create mode 100644 arch/arm/boot/dts/bcm911360k.dts
 create mode 100644 arch/arm/boot/dts/bcm958300k.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7c80af9..a6b734a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -54,6 +54,10 @@ dtb-$(CONFIG_ARCH_AT91)	+= at91-sama5d4ek.dtb
 dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
 dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
+dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
+	bcm911360_entphn.dtb \
+	bcm911360k.dtb \
+	bcm958300k.dtb
 dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
 dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb
 dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
diff --git a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
new file mode 100644
index 0000000..d06172b
--- /dev/null
+++ b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+clocks {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges;
+
+	osc: oscillator {
+		compatible = "fixed-clock";
+		#clock-cells = <1>;
+		clock-frequency = <25000000>;
+	};
+
+	apb_clk: apb_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1000000000>;
+	};
+
+	periph_clk: periph_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <500000000>;
+	};
+
+	sdio_clk: lcpll_ch2 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <200000000>;
+	};
+
+	axi81_clk: axi81_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	keypad_clk: keypad_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <31806>;
+	};
+
+	adc_clk: adc_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1562500>;
+	};
+
+	pwm_clk: pwm_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1000000>;
+	};
+
+	lcd_clk: mipipll_ch1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+};
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
new file mode 100644
index 0000000..a377ab2
--- /dev/null
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "brcm,cygnus";
+	model = "Broadcom Cygnus SoC";
+	interrupt-parent = <&gic>;
+
+	aliases {
+		serial0 = &uart3;
+		serial1 = &uart0;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200 earlyprintk debug";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <0x0>;
+		};
+	};
+
+	/include/ "bcm-cygnus-clock.dtsi"
+
+	amba {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "arm,amba-bus", "simple-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		wdt@18009000 {
+			 compatible = "arm,sp805" , "arm,primecell";
+			 reg = <0x18009000 0x1000>;
+			 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+			 clocks = <&axi81_clk>;
+			 clock-names = "apb_pclk";
+		};
+	};
+
+	uart3: serial@18023000 {
+		compatible = "snps,dw-apb-uart";
+		reg = <0x18023000 0x100>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <100000000>;
+		clocks = <&axi81_clk>;
+		status = "okay";
+	};
+
+	uart0: serial@18020000 {
+		compatible = "snps,dw-apb-uart";
+		reg = <0x18020000 0x100>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&axi81_clk>;
+		clock-frequency = <100000000>;
+		status = "okay";
+	};
+
+	gic: interrupt-controller@19021000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+		interrupt-controller;
+		reg = <0x19021000 0x1000>,
+		      <0x19020100 0x100>;
+	};
+
+	L2: l2-cache {
+		compatible = "arm,pl310-cache";
+		reg = <0x19022000 0x1000>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	timer@19020200 {
+		compatible = "arm,cortex-a9-global-timer";
+		reg = <0x19020200 0x100>;
+		interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&periph_clk>;
+	};
+
+};
diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts
new file mode 100644
index 0000000..c5188d7
--- /dev/null
+++ b/arch/arm/boot/dts/bcm911360_entphn.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "bcm-cygnus.dtsi"
+
+/ {
+	model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)";
+	compatible = "brcm,bcm11360", "brcm,cygnus";
+};
diff --git a/arch/arm/boot/dts/bcm911360k.dts b/arch/arm/boot/dts/bcm911360k.dts
new file mode 100644
index 0000000..866d1e1
--- /dev/null
+++ b/arch/arm/boot/dts/bcm911360k.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "bcm-cygnus.dtsi"
+
+/ {
+	model = "Cygnus SVK (BCM911360K)";
+	compatible = "brcm,bcm11360", "brcm,cygnus";
+};
diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts
new file mode 100644
index 0000000..8739751
--- /dev/null
+++ b/arch/arm/boot/dts/bcm958300k.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "bcm-cygnus.dtsi"
+
+/ {
+	model = "Cygnus SVK (BCM958300K)";
+	compatible = "brcm,bcm58300", "brcm,cygnus";
+};
-- 
1.7.9.5

[PATCH v6 5/6] MAINTAINERS: Entry for Cygnus/iproc arm architecture

[Scott Branden]

Acked-by: Jonathan Richardson <jonathar@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 MAINTAINERS |   14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index b0f17d5..dfe255f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2125,6 +2125,20 @@ L:	linux-scsi@vger.kernel.org
 S:	Supported
 F:	drivers/scsi/bnx2i/
 
+BROADCOM CYGNUS/IPROC ARM ARCHITECTURE
+M:	Ray Jui <rjui@broadcom.com>
+M:	Scott Branden <sbranden@broadcom.com>
+L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L:	bcm-kernel-feedback-list@broadcom.com
+T:	git git://git.github.com/brcm/linux.git
+S:	Maintained
+N:	iproc
+N:	cygnus
+N:	bcm9113*
+N:	bcm9583*
+N:	bcm583*
+N:	bcm113*
+
 BROADCOM KONA GPIO DRIVER
 M:	Ray Jui <rjui@broadcom.com>
 L:	bcm-kernel-feedback-list@broadcom.com
-- 
1.7.9.5

[PATCH v6 6/6] ARM: mach-bcm: Consolidate currently supported IPROC SoCs

[Scott Branden]

Move ARCH_BCM_5301X subarch under ARCH_IPROC architecture.
Additional IPROC chipsets that share a lot of commonality should be
added under ARCH_IPROC as well.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/mach-bcm/Kconfig |   37 ++++++++++++++++---------------------
 1 file changed, 16 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index f5e638e..a51f191 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -33,6 +33,22 @@ config ARCH_BCM_CYGNUS
 	  BCM11300, BCM11320, BCM11350, BCM11360,
 	  BCM58300, BCM58302, BCM58303, BCM58305.
 
+config ARCH_BCM_5301X
+	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
+	select ARCH_BCM_IPROC
+	help
+	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
+
+	  This is a network SoC line mostly used in home routers and
+	  wifi access points, it's internal name is Northstar.
+	  This inclused the following SoC: BCM53010, BCM53011, BCM53012,
+	  BCM53014, BCM53015, BCM53016, BCM53017, BCM53018, BCM4707,
+	  BCM4708 and BCM4709.
+
+	  Do not confuse this with the BCM4760 which is a totally
+	  different SoC or with the older BCM47XX and BCM53XX based
+	  network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
+
 config ARCH_BCM_MOBILE
 	bool "Broadcom Mobile SoC Support" if ARCH_MULTI_V7
 	select ARCH_REQUIRE_GPIOLIB
@@ -106,27 +122,6 @@ config ARCH_BCM2835
 	  This enables support for the Broadcom BCM2835 SoC. This SoC is
 	  used in the Raspberry Pi and Roku 2 devices.
 
-config ARCH_BCM_5301X
-	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
-	select ARM_GIC
-	select CACHE_L2X0
-	select HAVE_ARM_SCU if SMP
-	select HAVE_ARM_TWD if SMP
-	select ARM_GLOBAL_TIMER
-	select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
-	help
-	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
-
-	  This is a network SoC line mostly used in home routers and
-	  wifi access points, it's internal name is Northstar.
-	  This inclused the following SoC: BCM53010, BCM53011, BCM53012,
-	  BCM53014, BCM53015, BCM53016, BCM53017, BCM53018, BCM4707,
-	  BCM4708 and BCM4709.
-
-	  Do not confuse this with the BCM4760 which is a totally
-	  different SoC or with the older BCM47XX and BCM53XX based
-	  network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
-
 config ARCH_BCM_63XX
 	bool "Broadcom BCM63xx DSL SoC" if ARCH_MULTI_V7
 	depends on MMU
-- 
1.7.9.5

Re: [PATCH v5 1/6] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Arnd Bergmann]

On Tuesday 21 October 2014 17:11:08 Scott Branden wrote:
> OK, I will remove the "iProc SoC based Machine types".  This was 
> grouping all iProc based SoCs under one menu and parallels what the 
> existing "Broadcom Mobile Soc Support" menu does.
>
> I can create another patch removing the "Broadcom Mobile SoC Support" 
> menu if the ARM Maintainer now want all Broadcom devices are supposed to 
> be contained in a single level?

Sounds good, I missed that other menu going in.

It can make sense to add 'comment' statements if you want to separate the
families.

I also noticed that there are a few configuration options that at first
seem pointless: ARCH_BCM_MOBILE_L2_CACHE and ARCH_BCM_MOBILE_SMP. I wonder
if it ever makes sense to disable these when the common options (CACHE_L2X0
and SMP) are enabled for another SoC. I'd normally like to see these as
hidden options that are always on whenever the core support for those
features is enabled, to avoid confusing users as well as bugs from the
combinatorial explosion.

	Arnd

Re: [PATCH v5 1/6] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Scott Branden]

On 14-10-22 01:22 AM, Arnd Bergmann wrote:
> On Tuesday 21 October 2014 17:11:08 Scott Branden wrote:
>> OK, I will remove the "iProc SoC based Machine types".  This was
>> grouping all iProc based SoCs under one menu and parallels what the
>> existing "Broadcom Mobile Soc Support" menu does.
>>
>> I can create another patch removing the "Broadcom Mobile SoC Support"
>> menu if the ARM Maintainer now want all Broadcom devices are supposed to
>> be contained in a single level?
>
> Sounds good, I missed that other menu going in.
I will add another patch to my set to correct this.
>
> It can make sense to add 'comment' statements if you want to separate the
> families.
Thanks - I will add this to my patchset.
>
> I also noticed that there are a few configuration options that at first
> seem pointless: ARCH_BCM_MOBILE_L2_CACHE and ARCH_BCM_MOBILE_SMP. I wonder
> if it ever makes sense to disable these when the common options (CACHE_L2X0
> and SMP) are enabled for another SoC. I'd normally like to see these as
> hidden options that are always on whenever the core support for those
> features is enabled, to avoid confusing users as well as bugs from the
> combinatorial explosion.
I can clean up all but ARCH_BCM_MOBILE_L2_CACHE.  This one is 
intertwined with SMC support and it looks like they want the option to 
turn on and off this feature.  This L2/Trustzone support will need to be 
cleaned up at a later time.  I heard Russell King says the PL310 cache 
code will be changing again soon.  When I add PL310 Trustzone support 
for the Cygnus SoC I can have a look at cleaning it up for the 
Mobile/Kona base SoCs at the same time.
>
> 	Arnd
>

[PATCH v7 0/7] Add initial support for Broadcom Cygnus SoC

[Scott Branden]

This patchset contains initial support for Broadcom's Cygnus SoC based on our
iProc architecture. Initial support is minimal and includes just the mach
platform code, clock driver, and a basic device tree configuration. Peripheral
drivers will be submitted soon, as will device tree configurations for other
Cygnus board variants.

Changes from v6:
 - Additional patch added for cleanup of other areas of mach-bcm/Kconfig
   discovered during Cygnus submission review to:
   - removed one level of menu for ARCH_BCM_MOBILE in mach-bcm-Kconfig based
     on feedback from Arnd
   - added comment sections to Kconfig to identify SoC architecture groupings

Changes from v5:
 - removed one level of menu used in mach-bcm/Kconfig
 - changed MAINTAINERS to use N: to support all files associated with iproc
   and cygnus going forward
 - updated bcm_cygnus_defconfig to remove some DEBUG options that greatly
   hamper performance

Changes from v4:
 - simple clock tree used. reworked clock driver will be submitted later
 - fixed MAINTAINERS patchset error
 - removed DEBUG_UART_8250 Kconfig.debug legacy support
 - made ARCH_BCM_IPROC a silent Kconfig option
 - removed multi_v7_defconfig as it is not needed at this time, can
   support in future patchset but does not seem optimal configs for our
   current usage.
 
Changes from v3:
 - restart functionality removed.  Will be added in a different patchset
   in drivers/power
 - removed NEON init sequence.  Will be moved to bootloader
 - cleaned up Kconfigs for ARCH_BCM_CYGNUS by removing unnecessary selects
 - consolidated ARCH_BCM_IPROC with select from ARCH_BCM_CYGNUS and
   ARCH_BCM5301X
 - removed bcm911360_entphn binding
 - added documentation for SoCs currently supported in Cygnus family

Changes from v2:
 - rebased to 3.17 kernel

Changes from v1:
 - Address code review comments as per previous responses.
 - Copyright headers updated to remove Broadcom URL.
 - mach platform code still contains hard coded addresses. These address are
   the same for all Cygnus variants. Could you please provide guidance on where
   they should go if you would still like them changed.  There does not seem to
   be a reason to change them to device tree as they do not change.

Jonathan Richardson (3):
  ARM: cygnus: Initial support for Broadcom Cygnus SoC
  dt-bindings: Document Broadcom Cygnus SoC and clocks
  ARM: cygnus defconfig : Initial defconfig for Broadcom Cygnus SoC

Scott Branden (4):
  ARM: dts: Enable Broadcom Cygnus SoC
  MAINTAINERS: Entry for Cygnus/iproc arm architecture
  ARM: mach-bcm: Consolidate currently supported IPROC SoCs
  ARM: mach-bcm: ARCH_BCM_MOBILE: remove one level of menu from Kconfig

 .../devicetree/bindings/arm/bcm/cygnus.txt         |   31 +++
 .../devicetree/bindings/clock/bcm-cygnus-clock.txt |   34 +++
 MAINTAINERS                                        |   14 ++
 arch/arm/boot/dts/Makefile                         |    4 +
 arch/arm/boot/dts/bcm-cygnus-clock.dtsi            |   73 ++++++
 arch/arm/boot/dts/bcm-cygnus.dtsi                  |  109 +++++++++
 arch/arm/boot/dts/bcm911360_entphn.dts             |   22 ++
 arch/arm/boot/dts/bcm911360k.dts                   |   22 ++
 arch/arm/boot/dts/bcm958300k.dts                   |   22 ++
 arch/arm/configs/bcm_cygnus_defconfig              |  237 ++++++++++++++++++++
 arch/arm/configs/bcm_defconfig                     |    3 +-
 arch/arm/configs/multi_v7_defconfig                |    3 +-
 arch/arm/mach-bcm/Kconfig                          |   93 +++++---
 arch/arm/mach-bcm/Makefile                         |    3 +
 arch/arm/mach-bcm/bcm_cygnus.c                     |   26 +++
 15 files changed, 658 insertions(+), 38 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/cygnus.txt
 create mode 100644 Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
 create mode 100644 arch/arm/boot/dts/bcm-cygnus-clock.dtsi
 create mode 100644 arch/arm/boot/dts/bcm-cygnus.dtsi
 create mode 100644 arch/arm/boot/dts/bcm911360_entphn.dts
 create mode 100644 arch/arm/boot/dts/bcm911360k.dts
 create mode 100644 arch/arm/boot/dts/bcm958300k.dts
 create mode 100644 arch/arm/configs/bcm_cygnus_defconfig
 create mode 100644 arch/arm/mach-bcm/bcm_cygnus.c

-- 
1.7.9.5

[PATCH v7 1/7] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Scott Branden]

From: Jonathan Richardson <jonathar@broadcom.com>

Adds initial support for the Cygnus SoC based on Broadcom’s iProc series.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Desmond Liu <desmondl@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/mach-bcm/Kconfig      |   32 ++++++++++++++++++++++++++++++++
 arch/arm/mach-bcm/Makefile     |    3 +++
 arch/arm/mach-bcm/bcm_cygnus.c |   26 ++++++++++++++++++++++++++
 3 files changed, 61 insertions(+)
 create mode 100644 arch/arm/mach-bcm/bcm_cygnus.c

diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 2abad74..73d95c2 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -5,6 +5,36 @@ menuconfig ARCH_BCM
 
 if ARCH_BCM
 
+comment "IPROC architected SoCs"
+
+config ARCH_BCM_IPROC
+	bool
+	select ARM_GIC
+	select CACHE_L2X0
+	select HAVE_ARM_SCU if SMP
+	select HAVE_ARM_TWD if SMP
+	select ARM_GLOBAL_TIMER
+
+	select CLKSRC_MMIO
+	select ARCH_REQUIRE_GPIOLIB
+	select ARM_AMBA
+	select PINCTRL
+	help
+	  This enables support for systems based on Broadcom IPROC architected SoCs.
+	  The IPROC complex contains one or more ARM CPUs along with common
+	  core periperals. Application specific SoCs are created by adding a
+	  uArchitecture containing peripherals outside of the IPROC complex.
+	  Currently supported SoCs are Cygnus.
+
+config ARCH_BCM_CYGNUS
+	bool "Broadcom Cygnus Support" if ARCH_MULTI_V7
+	select ARCH_BCM_IPROC
+	help
+	  Enable support for the Cygnus family,
+	  which includes the following variants:
+	  BCM11300, BCM11320, BCM11350, BCM11360,
+	  BCM58300, BCM58302, BCM58303, BCM58305.
+
 config ARCH_BCM_MOBILE
 	bool "Broadcom Mobile SoC Support" if ARCH_MULTI_V7
 	select ARCH_REQUIRE_GPIOLIB
@@ -65,6 +95,8 @@ endmenu
 
 endif
 
+comment "Other Architectures"
+
 config ARCH_BCM2835
 	bool "Broadcom BCM2835 family" if ARCH_MULTI_V6
 	select ARCH_REQUIRE_GPIOLIB
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 300ae4b..34d45ba 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -10,6 +10,9 @@
 # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
 
+# Cygnus
+obj-$(CONFIG_ARCH_BCM_CYGNUS) +=  bcm_cygnus.o
+
 # BCM281XX
 obj-$(CONFIG_ARCH_BCM_281XX)	+= board_bcm281xx.o
 
diff --git a/arch/arm/mach-bcm/bcm_cygnus.c b/arch/arm/mach-bcm/bcm_cygnus.c
new file mode 100644
index 0000000..41b4933
--- /dev/null
+++ b/arch/arm/mach-bcm/bcm_cygnus.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <asm/mach/arch.h>
+
+static const char const *bcm_cygnus_dt_compat[] = {
+	"brcm,cygnus",
+	NULL,
+};
+
+DT_MACHINE_START(BCM_CYGNUS_DT, "Broadcom Cygnus SoC")
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
+	.dt_compat = bcm_cygnus_dt_compat,
+MACHINE_END
-- 
1.7.9.5

[PATCH v7 2/7] dt-bindings: Document Broadcom Cygnus SoC and clocks

[Scott Branden]

From: Jonathan Richardson <jonathar@broadcom.com>

Reviewed-by: Arun Parameswaran <aparames@broadcom.com>
Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 .../devicetree/bindings/arm/bcm/cygnus.txt         |   31 ++++++++++++++++++
 .../devicetree/bindings/clock/bcm-cygnus-clock.txt |   34 ++++++++++++++++++++
 2 files changed, 65 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/cygnus.txt
 create mode 100644 Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt

diff --git a/Documentation/devicetree/bindings/arm/bcm/cygnus.txt b/Documentation/devicetree/bindings/arm/bcm/cygnus.txt
new file mode 100644
index 0000000..4c77169
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/cygnus.txt
@@ -0,0 +1,31 @@
+Broadcom Cygnus device tree bindings
+------------------------------------
+
+
+Boards with Cygnus SoCs shall have the following properties:
+
+Required root node property:
+
+BCM11300
+compatible = "brcm,bcm11300", "brcm,cygnus";
+
+BCM11320
+compatible = "brcm,bcm11320", "brcm,cygnus";
+
+BCM11350
+compatible = "brcm,bcm11350", "brcm,cygnus";
+
+BCM11360
+compatible = "brcm,bcm11360", "brcm,cygnus";
+
+BCM58300
+compatible = "brcm,bcm58300", "brcm,cygnus";
+
+BCM58302
+compatible = "brcm,bcm58302", "brcm,cygnus";
+
+BCM58303
+compatible = "brcm,bcm58303", "brcm,cygnus";
+
+BCM58305
+compatible = "brcm,bcm58305", "brcm,cygnus";
diff --git a/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt b/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
new file mode 100644
index 0000000..00d26ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
@@ -0,0 +1,34 @@
+Broadcom Cygnus Clocks
+
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Currently various "fixed" clocks are declared for peripheral drivers that use
+the common clock framework to reference their core clocks. Proper support of
+these clocks will be added later
+
+Device tree example:
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		osc: oscillator {
+			compatible = "fixed-clock";
+			#clock-cells = <1>;
+			clock-frequency = <25000000>;
+		};
+
+		apb_clk: apb_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <1000000000>;
+		};
+
+		periph_clk: periph_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <500000000>;
+		};
+	};
-- 
1.7.9.5

[PATCH v7 3/7] ARM: cygnus defconfig : Initial defconfig for Broadcom Cygnus SoC

[Scott Branden]

From: Jonathan Richardson <jonathar@broadcom.com>

This defconfig is utilized so a customer or developer can understand
what kernel drivers are utilized by the Cygnus SoC.  It also enables
debug configs which should be disabled if optimal performance is
desired.

Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/configs/bcm_cygnus_defconfig |  237 +++++++++++++++++++++++++++++++++
 1 file changed, 237 insertions(+)
 create mode 100644 arch/arm/configs/bcm_cygnus_defconfig

diff --git a/arch/arm/configs/bcm_cygnus_defconfig b/arch/arm/configs/bcm_cygnus_defconfig
new file mode 100644
index 0000000..9ad77a8
--- /dev/null
+++ b/arch/arm/configs/bcm_cygnus_defconfig
@@ -0,0 +1,237 @@
+CONFIG_KERNEL_XZ=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_FHANDLE=y
+CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=19
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_BLK_CGROUP=y
+CONFIG_NAMESPACES=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_JUMP_LABEL=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BCM_CYGNUS=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_PCI=y
+CONFIG_PCI_DEBUG=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+# CONFIG_COMPACTION is not set
+# CONFIG_ATAGS is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_TCP_CONG_ADVANCED=y
+# CONFIG_TCP_CONG_BIC is not set
+# CONFIG_TCP_CONG_WESTWOOD is not set
+# CONFIG_TCP_CONG_HTCP is not set
+CONFIG_IPV6=y
+# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET6_XFRM_MODE_BEET is not set
+# CONFIG_IPV6_SIT is not set
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+CONFIG_NETFILTER=y
+# CONFIG_BRIDGE_NETFILTER is not set
+CONFIG_NF_CONNTRACK=y
+# CONFIG_NF_CONNTRACK_PROCFS is not set
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_RAW=y
+CONFIG_NF_CONNTRACK_IPV6=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_MATCH_AH=y
+CONFIG_IP6_NF_MATCH_EUI64=y
+CONFIG_IP6_NF_MATCH_FRAG=y
+CONFIG_IP6_NF_MATCH_OPTS=y
+CONFIG_IP6_NF_MATCH_IPV6HEADER=y
+CONFIG_IP6_NF_MATCH_MH=y
+CONFIG_IP6_NF_MATCH_RT=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_IP6_NF_RAW=y
+CONFIG_BRIDGE=y
+# CONFIG_BRIDGE_IGMP_SNOOPING is not set
+CONFIG_VLAN_8021Q=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_FQ_CODEL=y
+CONFIG_CFG80211=y
+# CONFIG_CFG80211_DEFAULT_PS is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_RFKILL=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_PHYLIB=y
+CONFIG_BROADCOM_PHY=y
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
+CONFIG_I2C_SMBUS=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=y
+# CONFIG_USB_GSPCA is not set
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_DEBUG=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_SOC=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_RTC_CLASS=y
+CONFIG_PWM=y
+CONFIG_EXT4_FS=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_UBIFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_INFO=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_OBJECTS=y
+CONFIG_DEBUG_OBJECTS_RCU_HEAD=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=110
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_SCHEDSTATS=y
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_ATOMIC_SLEEP=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_UART_8250=y
+CONFIG_DEBUG_UART_PHYS=0x18023000
+CONFIG_DEBUG_UART_VIRT=0xf1023000
+CONFIG_EARLY_PRINTK=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
-- 
1.7.9.5

[PATCH v7 4/7] ARM: dts: Enable Broadcom Cygnus SoC

[Scott Branden]

DT files to enable cygnus consisting on reference designs
and cygnus core configuration.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Arun Parameswaran <aparames@broadcom.com>
Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/boot/dts/Makefile              |    4 ++
 arch/arm/boot/dts/bcm-cygnus-clock.dtsi |   73 +++++++++++++++++++++
 arch/arm/boot/dts/bcm-cygnus.dtsi       |  109 +++++++++++++++++++++++++++++++
 arch/arm/boot/dts/bcm911360_entphn.dts  |   22 +++++++
 arch/arm/boot/dts/bcm911360k.dts        |   22 +++++++
 arch/arm/boot/dts/bcm958300k.dts        |   22 +++++++
 6 files changed, 252 insertions(+)
 create mode 100644 arch/arm/boot/dts/bcm-cygnus-clock.dtsi
 create mode 100644 arch/arm/boot/dts/bcm-cygnus.dtsi
 create mode 100644 arch/arm/boot/dts/bcm911360_entphn.dts
 create mode 100644 arch/arm/boot/dts/bcm911360k.dts
 create mode 100644 arch/arm/boot/dts/bcm958300k.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7c80af9..a6b734a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -54,6 +54,10 @@ dtb-$(CONFIG_ARCH_AT91)	+= at91-sama5d4ek.dtb
 dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
 dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
+dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
+	bcm911360_entphn.dtb \
+	bcm911360k.dtb \
+	bcm958300k.dtb
 dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
 dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb
 dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
diff --git a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
new file mode 100644
index 0000000..d06172b
--- /dev/null
+++ b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+clocks {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges;
+
+	osc: oscillator {
+		compatible = "fixed-clock";
+		#clock-cells = <1>;
+		clock-frequency = <25000000>;
+	};
+
+	apb_clk: apb_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1000000000>;
+	};
+
+	periph_clk: periph_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <500000000>;
+	};
+
+	sdio_clk: lcpll_ch2 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <200000000>;
+	};
+
+	axi81_clk: axi81_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	keypad_clk: keypad_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <31806>;
+	};
+
+	adc_clk: adc_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1562500>;
+	};
+
+	pwm_clk: pwm_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1000000>;
+	};
+
+	lcd_clk: mipipll_ch1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+};
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
new file mode 100644
index 0000000..a377ab2
--- /dev/null
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "brcm,cygnus";
+	model = "Broadcom Cygnus SoC";
+	interrupt-parent = <&gic>;
+
+	aliases {
+		serial0 = &uart3;
+		serial1 = &uart0;
+	};
+
+	chosen {
+		bootargs = "console=ttyS0,115200 earlyprintk debug";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <0x0>;
+		};
+	};
+
+	/include/ "bcm-cygnus-clock.dtsi"
+
+	amba {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "arm,amba-bus", "simple-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		wdt@18009000 {
+			 compatible = "arm,sp805" , "arm,primecell";
+			 reg = <0x18009000 0x1000>;
+			 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+			 clocks = <&axi81_clk>;
+			 clock-names = "apb_pclk";
+		};
+	};
+
+	uart3: serial@18023000 {
+		compatible = "snps,dw-apb-uart";
+		reg = <0x18023000 0x100>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <100000000>;
+		clocks = <&axi81_clk>;
+		status = "okay";
+	};
+
+	uart0: serial@18020000 {
+		compatible = "snps,dw-apb-uart";
+		reg = <0x18020000 0x100>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&axi81_clk>;
+		clock-frequency = <100000000>;
+		status = "okay";
+	};
+
+	gic: interrupt-controller@19021000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+		interrupt-controller;
+		reg = <0x19021000 0x1000>,
+		      <0x19020100 0x100>;
+	};
+
+	L2: l2-cache {
+		compatible = "arm,pl310-cache";
+		reg = <0x19022000 0x1000>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	timer@19020200 {
+		compatible = "arm,cortex-a9-global-timer";
+		reg = <0x19020200 0x100>;
+		interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&periph_clk>;
+	};
+
+};
diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts
new file mode 100644
index 0000000..c5188d7
--- /dev/null
+++ b/arch/arm/boot/dts/bcm911360_entphn.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "bcm-cygnus.dtsi"
+
+/ {
+	model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)";
+	compatible = "brcm,bcm11360", "brcm,cygnus";
+};
diff --git a/arch/arm/boot/dts/bcm911360k.dts b/arch/arm/boot/dts/bcm911360k.dts
new file mode 100644
index 0000000..866d1e1
--- /dev/null
+++ b/arch/arm/boot/dts/bcm911360k.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "bcm-cygnus.dtsi"
+
+/ {
+	model = "Cygnus SVK (BCM911360K)";
+	compatible = "brcm,bcm11360", "brcm,cygnus";
+};
diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts
new file mode 100644
index 0000000..8739751
--- /dev/null
+++ b/arch/arm/boot/dts/bcm958300k.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "bcm-cygnus.dtsi"
+
+/ {
+	model = "Cygnus SVK (BCM958300K)";
+	compatible = "brcm,bcm58300", "brcm,cygnus";
+};
-- 
1.7.9.5

[PATCH v7 5/7] MAINTAINERS: Entry for Cygnus/iproc arm architecture

[Scott Branden]

Acked-by: Jonathan Richardson <jonathar@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 MAINTAINERS |   14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index b0f17d5..dfe255f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2125,6 +2125,20 @@ L:	linux-scsi@vger.kernel.org
 S:	Supported
 F:	drivers/scsi/bnx2i/
 
+BROADCOM CYGNUS/IPROC ARM ARCHITECTURE
+M:	Ray Jui <rjui@broadcom.com>
+M:	Scott Branden <sbranden@broadcom.com>
+L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L:	bcm-kernel-feedback-list@broadcom.com
+T:	git git://git.github.com/brcm/linux.git
+S:	Maintained
+N:	iproc
+N:	cygnus
+N:	bcm9113*
+N:	bcm9583*
+N:	bcm583*
+N:	bcm113*
+
 BROADCOM KONA GPIO DRIVER
 M:	Ray Jui <rjui@broadcom.com>
 L:	bcm-kernel-feedback-list@broadcom.com
-- 
1.7.9.5

[PATCH v7 6/7] ARM: mach-bcm: Consolidate currently supported IPROC SoCs

[Scott Branden]

Move ARCH_BCM_5301X subarch under ARCH_IPROC architecture.
Additional IPROC chipsets that share a lot of commonality should be
added under ARCH_IPROC as well.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/mach-bcm/Kconfig |   37 ++++++++++++++++---------------------
 1 file changed, 16 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 73d95c2..6e79696 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -35,6 +35,22 @@ config ARCH_BCM_CYGNUS
 	  BCM11300, BCM11320, BCM11350, BCM11360,
 	  BCM58300, BCM58302, BCM58303, BCM58305.
 
+config ARCH_BCM_5301X
+	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
+	select ARCH_BCM_IPROC
+	help
+	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
+
+	  This is a network SoC line mostly used in home routers and
+	  wifi access points, it's internal name is Northstar.
+	  This inclused the following SoC: BCM53010, BCM53011, BCM53012,
+	  BCM53014, BCM53015, BCM53016, BCM53017, BCM53018, BCM4707,
+	  BCM4708 and BCM4709.
+
+	  Do not confuse this with the BCM4760 which is a totally
+	  different SoC or with the older BCM47XX and BCM53XX based
+	  network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
+
 config ARCH_BCM_MOBILE
 	bool "Broadcom Mobile SoC Support" if ARCH_MULTI_V7
 	select ARCH_REQUIRE_GPIOLIB
@@ -110,27 +126,6 @@ config ARCH_BCM2835
 	  This enables support for the Broadcom BCM2835 SoC. This SoC is
 	  used in the Raspberry Pi and Roku 2 devices.
 
-config ARCH_BCM_5301X
-	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
-	select ARM_GIC
-	select CACHE_L2X0
-	select HAVE_ARM_SCU if SMP
-	select HAVE_ARM_TWD if SMP
-	select ARM_GLOBAL_TIMER
-	select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
-	help
-	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
-
-	  This is a network SoC line mostly used in home routers and
-	  wifi access points, it's internal name is Northstar.
-	  This inclused the following SoC: BCM53010, BCM53011, BCM53012,
-	  BCM53014, BCM53015, BCM53016, BCM53017, BCM53018, BCM4707,
-	  BCM4708 and BCM4709.
-
-	  Do not confuse this with the BCM4760 which is a totally
-	  different SoC or with the older BCM47XX and BCM53XX based
-	  network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
-
 config ARCH_BCM_63XX
 	bool "Broadcom BCM63xx DSL SoC" if ARCH_MULTI_V7
 	depends on MMU
-- 
1.7.9.5

[PATCH v7 7/7] ARM: mach-bcm: ARCH_BCM_MOBILE: remove one level of menu from Kconfig

[Scott Branden]

remove menu "Broadcom Mobile SoC Selection"
This requires:
- selecting ARCH_BCM_MOBILE based on SoC selections
- fixup bcm_defconfig to work with new menu levels.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/configs/bcm_defconfig      |    3 ++-
 arch/arm/configs/multi_v7_defconfig |    3 ++-
 arch/arm/mach-bcm/Kconfig           |   26 ++++++++++----------------
 3 files changed, 14 insertions(+), 18 deletions(-)

diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
index bc614f4..83a87e4 100644
--- a/arch/arm/configs/bcm_defconfig
+++ b/arch/arm/configs/bcm_defconfig
@@ -25,7 +25,8 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_ARCH_BCM=y
-CONFIG_ARCH_BCM_MOBILE=y
+CONFIG_ARCH_BCM_21664=y
+CONFIG_ARCH_BCM_281XX=y
 CONFIG_ARM_THUMBEE=y
 CONFIG_SMP=y
 CONFIG_PREEMPT=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 491b7d5..e8f79fd 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -17,7 +17,8 @@ CONFIG_MACH_ARMADA_38X=y
 CONFIG_MACH_ARMADA_XP=y
 CONFIG_MACH_DOVE=y
 CONFIG_ARCH_BCM=y
-CONFIG_ARCH_BCM_MOBILE=y
+CONFIG_ARCH_BCM_21664=y
+CONFIG_ARCH_BCM_281XX=y
 CONFIG_ARCH_BCM_5301X=y
 CONFIG_ARCH_BRCMSTB=y
 CONFIG_ARCH_BERLIN=y
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 6e79696..cceb69f 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -51,8 +51,10 @@ config ARCH_BCM_5301X
 	  different SoC or with the older BCM47XX and BCM53XX based
 	  network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
 
+comment "KONA architected SoCs"
+
 config ARCH_BCM_MOBILE
-	bool "Broadcom Mobile SoC Support" if ARCH_MULTI_V7
+	bool
 	select ARCH_REQUIRE_GPIOLIB
 	select ARM_ERRATA_754322
 	select ARM_ERRATA_775420
@@ -61,16 +63,13 @@ config ARCH_BCM_MOBILE
 	select TICK_ONESHOT
 	select HAVE_ARM_ARCH_TIMER
 	select PINCTRL
+	select ARCH_BCM_MOBILE_SMP if SMP
 	help
 	  This enables support for systems based on Broadcom mobile SoCs.
 
-if ARCH_BCM_MOBILE
-
-menu "Broadcom Mobile SoC Selection"
-
 config ARCH_BCM_281XX
 	bool "Broadcom BCM281XX SoC family"
-	default y
+	select ARCH_BCM_MOBILE
 	select HAVE_SMP
 	help
 	  Enable support for the BCM281XX family, which includes
@@ -79,7 +78,7 @@ config ARCH_BCM_281XX
 
 config ARCH_BCM_21664
 	bool "Broadcom BCM21664 SoC family"
-	default y
+	select ARCH_BCM_MOBILE
 	select HAVE_SMP
 	help
 	  Enable support for the BCM21664 family, which includes
@@ -87,19 +86,18 @@ config ARCH_BCM_21664
 
 config ARCH_BCM_MOBILE_L2_CACHE
 	bool "Broadcom mobile SoC level 2 cache support"
-	depends on (ARCH_BCM_281XX || ARCH_BCM_21664)
+	depends on ARCH_BCM_MOBILE
 	default y
 	select CACHE_L2X0
 	select ARCH_BCM_MOBILE_SMC
 
 config ARCH_BCM_MOBILE_SMC
 	bool
-	depends on ARCH_BCM_281XX || ARCH_BCM_21664
+	depends on ARCH_BCM_MOBILE
 
 config ARCH_BCM_MOBILE_SMP
-	bool "Broadcom mobile SoC SMP support"
-	depends on (ARCH_BCM_281XX || ARCH_BCM_21664) && SMP
-	default y
+	bool
+	depends on ARCH_BCM_MOBILE
 	select HAVE_ARM_SCU
 	select ARM_ERRATA_764369
 	help
@@ -107,10 +105,6 @@ config ARCH_BCM_MOBILE_SMP
 	  Provided as an option so SMP support for SoCs of this type
 	  can be disabled for an SMP-enabled kernel.
 
-endmenu
-
-endif
-
 comment "Other Architectures"
 
 config ARCH_BCM2835
-- 
1.7.9.5

Re: [PATCH v7 4/7] ARM: dts: Enable Broadcom Cygnus SoC

[Arnd Bergmann]

On Wednesday 22 October 2014 13:57:51 Scott Branden wrote:
> +
> +       aliases {
> +               serial0 = &uart3;
> +               serial1 = &uart0;
> +       };
> +
> +       chosen {
> +               bootargs = "console=ttyS0,115200 earlyprintk debug";
> +       };
> 

Please move the 'aliases' and 'chosen' node into the .dts files, these
are board specific, not SoC specific.

For chosen, please remove earlyprintk and debug, which don't normally
make sense unless you are debugging, and which will break in a multiplatform
kernel.

Please also add an "stdout-path = &uart3" property in chosen so that
earlycon can work. Note that earlycon is currently broken on arm32,
but we'll get there.

	Arnd

Re: [PATCH v7 4/7] ARM: dts: Enable Broadcom Cygnus SoC

[Scott Branden]

Thanks for the review.  Will send out v8 version.  Hopefully for finally 
approval.

On 14-10-28 09:10 AM, Arnd Bergmann wrote:
> On Wednesday 22 October 2014 13:57:51 Scott Branden wrote:
>> +
>> +       aliases {
>> +               serial0 = &uart3;
>> +               serial1 = &uart0;
>> +       };
>> +
>> +       chosen {
>> +               bootargs = "console=ttyS0,115200 earlyprintk debug";
>> +       };
>>
>
> Please move the 'aliases' and 'chosen' node into the .dts files, these
> are board specific, not SoC specific.
ok.
>
> For chosen, please remove earlyprintk and debug, which don't normally
> make sense unless you are debugging, and which will break in a multiplatform
> kernel.
ok.
>
> Please also add an "stdout-path = &uart3" property in chosen so that
> earlycon can work. Note that earlycon is currently broken on arm32,
> but we'll get there.
ok.
>
> 	Arnd
>

[PATCH v8 0/8] Add initial support for Broadcom Cygnus SoC

[Scott Branden]

This patchset contains initial support for Broadcom's Cygnus SoC based on our
iProc architecture. Initial support is minimal and includes just the mach
platform code, clock driver, and a basic device tree configuration. Peripheral
drivers will be submitted soon, as will device tree configurations for other
Cygnus board variants.

Changes from v7:
 - Fixed dts to move uart code to board specific dts files
 - Add Cygnus to multi_v7_defconfig. It boots.

Changes from v6:
 - Additional patch added for cleanup of other areas of mach-bcm/Kconfig
   discovered during Cygnus submission review to:
   - removed one level of menu for ARCH_BCM_MOBILE in mach-bcm-Kconfig based
     on feedback from Arnd
   - added comment sections to Kconfig to identify SoC architecture groupings

Changes from v5:
 - removed one level of menu used in mach-bcm/Kconfig
 - changed MAINTAINERS to use N: to support all files associated with iproc
   and cygnus going forward
 - updated bcm_cygnus_defconfig to remove some DEBUG options that greatly
   hamper performance

Changes from v4:
 - simple clock tree used. reworked clock driver will be submitted later
 - fixed MAINTAINERS patchset error
 - removed DEBUG_UART_8250 Kconfig.debug legacy support
 - made ARCH_BCM_IPROC a silent Kconfig option
 - removed multi_v7_defconfig as it is not needed at this time, can
   support in future patchset but does not seem optimal configs for our
   current usage.
 
Changes from v3:
 - restart functionality removed.  Will be added in a different patchset
   in drivers/power
 - removed NEON init sequence.  Will be moved to bootloader
 - cleaned up Kconfigs for ARCH_BCM_CYGNUS by removing unnecessary selects
 - consolidated ARCH_BCM_IPROC with select from ARCH_BCM_CYGNUS and
   ARCH_BCM5301X
 - removed bcm911360_entphn binding
 - added documentation for SoCs currently supported in Cygnus family

Changes from v2:
 - rebased to 3.17 kernel

Changes from v1:
 - Address code review comments as per previous responses.
 - Copyright headers updated to remove Broadcom URL.
 - mach platform code still contains hard coded addresses. These address are
   the same for all Cygnus variants. Could you please provide guidance on where
   they should go if you would still like them changed.  There does not seem to
   be a reason to change them to device tree as they do not change.

Jonathan Richardson (3):
  ARM: cygnus: Initial support for Broadcom Cygnus SoC
  dt-bindings: Document Broadcom Cygnus SoC and clocks
  ARM: cygnus defconfig : Initial defconfig for Broadcom Cygnus SoC

Ray Jui (1):
  ARM: multi_v7_defconfig: Enable Broadcom Cygnus

Scott Branden (4):
  ARM: dts: Enable Broadcom Cygnus SoC
  MAINTAINERS: Entry for Cygnus/iproc arm architecture
  ARM: mach-bcm: Consolidate currently supported IPROC SoCs
  ARM: mach-bcm: ARCH_BCM_MOBILE: remove one level of menu from Kconfig

 .../devicetree/bindings/arm/bcm/cygnus.txt         |   31 +++
 .../devicetree/bindings/clock/bcm-cygnus-clock.txt |   34 +++
 MAINTAINERS                                        |   14 ++
 arch/arm/boot/dts/Makefile                         |    4 +
 arch/arm/boot/dts/bcm-cygnus-clock.dtsi            |   73 ++++++
 arch/arm/boot/dts/bcm-cygnus.dtsi                  |  100 +++++++++
 arch/arm/boot/dts/bcm911360_entphn.dts             |   32 +++
 arch/arm/boot/dts/bcm911360k.dts                   |   32 +++
 arch/arm/boot/dts/bcm958300k.dts                   |   32 +++
 arch/arm/configs/bcm_cygnus_defconfig              |  237 ++++++++++++++++++++
 arch/arm/configs/bcm_defconfig                     |    3 +-
 arch/arm/configs/multi_v7_defconfig                |    4 +-
 arch/arm/mach-bcm/Kconfig                          |   93 +++++---
 arch/arm/mach-bcm/Makefile                         |    3 +
 arch/arm/mach-bcm/bcm_cygnus.c                     |   26 +++
 15 files changed, 680 insertions(+), 38 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/cygnus.txt
 create mode 100644 Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
 create mode 100644 arch/arm/boot/dts/bcm-cygnus-clock.dtsi
 create mode 100644 arch/arm/boot/dts/bcm-cygnus.dtsi
 create mode 100644 arch/arm/boot/dts/bcm911360_entphn.dts
 create mode 100644 arch/arm/boot/dts/bcm911360k.dts
 create mode 100644 arch/arm/boot/dts/bcm958300k.dts
 create mode 100644 arch/arm/configs/bcm_cygnus_defconfig
 create mode 100644 arch/arm/mach-bcm/bcm_cygnus.c

-- 
1.7.9.5

[PATCH v8 1/8] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Scott Branden]

From: Jonathan Richardson <jonathar@broadcom.com>

Adds initial support for the Cygnus SoC based on Broadcom’s iProc series.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Desmond Liu <desmondl@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/mach-bcm/Kconfig      |   32 ++++++++++++++++++++++++++++++++
 arch/arm/mach-bcm/Makefile     |    3 +++
 arch/arm/mach-bcm/bcm_cygnus.c |   26 ++++++++++++++++++++++++++
 3 files changed, 61 insertions(+)
 create mode 100644 arch/arm/mach-bcm/bcm_cygnus.c

diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 2abad74..73d95c2 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -5,6 +5,36 @@ menuconfig ARCH_BCM
 
 if ARCH_BCM
 
+comment "IPROC architected SoCs"
+
+config ARCH_BCM_IPROC
+	bool
+	select ARM_GIC
+	select CACHE_L2X0
+	select HAVE_ARM_SCU if SMP
+	select HAVE_ARM_TWD if SMP
+	select ARM_GLOBAL_TIMER
+
+	select CLKSRC_MMIO
+	select ARCH_REQUIRE_GPIOLIB
+	select ARM_AMBA
+	select PINCTRL
+	help
+	  This enables support for systems based on Broadcom IPROC architected SoCs.
+	  The IPROC complex contains one or more ARM CPUs along with common
+	  core periperals. Application specific SoCs are created by adding a
+	  uArchitecture containing peripherals outside of the IPROC complex.
+	  Currently supported SoCs are Cygnus.
+
+config ARCH_BCM_CYGNUS
+	bool "Broadcom Cygnus Support" if ARCH_MULTI_V7
+	select ARCH_BCM_IPROC
+	help
+	  Enable support for the Cygnus family,
+	  which includes the following variants:
+	  BCM11300, BCM11320, BCM11350, BCM11360,
+	  BCM58300, BCM58302, BCM58303, BCM58305.
+
 config ARCH_BCM_MOBILE
 	bool "Broadcom Mobile SoC Support" if ARCH_MULTI_V7
 	select ARCH_REQUIRE_GPIOLIB
@@ -65,6 +95,8 @@ endmenu
 
 endif
 
+comment "Other Architectures"
+
 config ARCH_BCM2835
 	bool "Broadcom BCM2835 family" if ARCH_MULTI_V6
 	select ARCH_REQUIRE_GPIOLIB
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 300ae4b..34d45ba 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -10,6 +10,9 @@
 # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
 
+# Cygnus
+obj-$(CONFIG_ARCH_BCM_CYGNUS) +=  bcm_cygnus.o
+
 # BCM281XX
 obj-$(CONFIG_ARCH_BCM_281XX)	+= board_bcm281xx.o
 
diff --git a/arch/arm/mach-bcm/bcm_cygnus.c b/arch/arm/mach-bcm/bcm_cygnus.c
new file mode 100644
index 0000000..41b4933
--- /dev/null
+++ b/arch/arm/mach-bcm/bcm_cygnus.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <asm/mach/arch.h>
+
+static const char const *bcm_cygnus_dt_compat[] = {
+	"brcm,cygnus",
+	NULL,
+};
+
+DT_MACHINE_START(BCM_CYGNUS_DT, "Broadcom Cygnus SoC")
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
+	.dt_compat = bcm_cygnus_dt_compat,
+MACHINE_END
-- 
1.7.9.5

[PATCH v8 2/8] dt-bindings: Document Broadcom Cygnus SoC and clocks

[Scott Branden]

From: Jonathan Richardson <jonathar@broadcom.com>

Reviewed-by: Arun Parameswaran <aparames@broadcom.com>
Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 .../devicetree/bindings/arm/bcm/cygnus.txt         |   31 ++++++++++++++++++
 .../devicetree/bindings/clock/bcm-cygnus-clock.txt |   34 ++++++++++++++++++++
 2 files changed, 65 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/cygnus.txt
 create mode 100644 Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt

diff --git a/Documentation/devicetree/bindings/arm/bcm/cygnus.txt b/Documentation/devicetree/bindings/arm/bcm/cygnus.txt
new file mode 100644
index 0000000..4c77169
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/cygnus.txt
@@ -0,0 +1,31 @@
+Broadcom Cygnus device tree bindings
+------------------------------------
+
+
+Boards with Cygnus SoCs shall have the following properties:
+
+Required root node property:
+
+BCM11300
+compatible = "brcm,bcm11300", "brcm,cygnus";
+
+BCM11320
+compatible = "brcm,bcm11320", "brcm,cygnus";
+
+BCM11350
+compatible = "brcm,bcm11350", "brcm,cygnus";
+
+BCM11360
+compatible = "brcm,bcm11360", "brcm,cygnus";
+
+BCM58300
+compatible = "brcm,bcm58300", "brcm,cygnus";
+
+BCM58302
+compatible = "brcm,bcm58302", "brcm,cygnus";
+
+BCM58303
+compatible = "brcm,bcm58303", "brcm,cygnus";
+
+BCM58305
+compatible = "brcm,bcm58305", "brcm,cygnus";
diff --git a/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt b/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
new file mode 100644
index 0000000..00d26ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
@@ -0,0 +1,34 @@
+Broadcom Cygnus Clocks
+
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Currently various "fixed" clocks are declared for peripheral drivers that use
+the common clock framework to reference their core clocks. Proper support of
+these clocks will be added later
+
+Device tree example:
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		osc: oscillator {
+			compatible = "fixed-clock";
+			#clock-cells = <1>;
+			clock-frequency = <25000000>;
+		};
+
+		apb_clk: apb_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <1000000000>;
+		};
+
+		periph_clk: periph_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <500000000>;
+		};
+	};
-- 
1.7.9.5

[PATCH v8 3/8] ARM: cygnus defconfig : Initial defconfig for Broadcom Cygnus SoC

[Scott Branden]

From: Jonathan Richardson <jonathar@broadcom.com>

This defconfig is utilized so a customer or developer can understand
what kernel drivers are utilized by the Cygnus SoC.  It also enables
debug configs which should be disabled if optimal performance is
desired.

Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/configs/bcm_cygnus_defconfig |  237 +++++++++++++++++++++++++++++++++
 1 file changed, 237 insertions(+)
 create mode 100644 arch/arm/configs/bcm_cygnus_defconfig

diff --git a/arch/arm/configs/bcm_cygnus_defconfig b/arch/arm/configs/bcm_cygnus_defconfig
new file mode 100644
index 0000000..9ad77a8
--- /dev/null
+++ b/arch/arm/configs/bcm_cygnus_defconfig
@@ -0,0 +1,237 @@
+CONFIG_KERNEL_XZ=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_FHANDLE=y
+CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=19
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_BLK_CGROUP=y
+CONFIG_NAMESPACES=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_JUMP_LABEL=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BCM_CYGNUS=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_PCI=y
+CONFIG_PCI_DEBUG=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+# CONFIG_COMPACTION is not set
+# CONFIG_ATAGS is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_TCP_CONG_ADVANCED=y
+# CONFIG_TCP_CONG_BIC is not set
+# CONFIG_TCP_CONG_WESTWOOD is not set
+# CONFIG_TCP_CONG_HTCP is not set
+CONFIG_IPV6=y
+# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET6_XFRM_MODE_BEET is not set
+# CONFIG_IPV6_SIT is not set
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+CONFIG_NETFILTER=y
+# CONFIG_BRIDGE_NETFILTER is not set
+CONFIG_NF_CONNTRACK=y
+# CONFIG_NF_CONNTRACK_PROCFS is not set
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_RAW=y
+CONFIG_NF_CONNTRACK_IPV6=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_MATCH_AH=y
+CONFIG_IP6_NF_MATCH_EUI64=y
+CONFIG_IP6_NF_MATCH_FRAG=y
+CONFIG_IP6_NF_MATCH_OPTS=y
+CONFIG_IP6_NF_MATCH_IPV6HEADER=y
+CONFIG_IP6_NF_MATCH_MH=y
+CONFIG_IP6_NF_MATCH_RT=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_IP6_NF_RAW=y
+CONFIG_BRIDGE=y
+# CONFIG_BRIDGE_IGMP_SNOOPING is not set
+CONFIG_VLAN_8021Q=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_FQ_CODEL=y
+CONFIG_CFG80211=y
+# CONFIG_CFG80211_DEFAULT_PS is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_RFKILL=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_PHYLIB=y
+CONFIG_BROADCOM_PHY=y
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
+CONFIG_I2C_SMBUS=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=y
+# CONFIG_USB_GSPCA is not set
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_DEBUG=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_SOC=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_RTC_CLASS=y
+CONFIG_PWM=y
+CONFIG_EXT4_FS=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_UBIFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_INFO=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_OBJECTS=y
+CONFIG_DEBUG_OBJECTS_RCU_HEAD=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=110
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_SCHEDSTATS=y
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_ATOMIC_SLEEP=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_UART_8250=y
+CONFIG_DEBUG_UART_PHYS=0x18023000
+CONFIG_DEBUG_UART_VIRT=0xf1023000
+CONFIG_EARLY_PRINTK=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
-- 
1.7.9.5

[PATCH v8 4/8] ARM: dts: Enable Broadcom Cygnus SoC

[Scott Branden]

DT files to enable cygnus consisting on reference designs
and cygnus core configuration.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Arun Parameswaran <aparames@broadcom.com>
Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/boot/dts/Makefile              |    4 ++
 arch/arm/boot/dts/bcm-cygnus-clock.dtsi |   73 ++++++++++++++++++++++
 arch/arm/boot/dts/bcm-cygnus.dtsi       |  100 +++++++++++++++++++++++++++++++
 arch/arm/boot/dts/bcm911360_entphn.dts  |   32 ++++++++++
 arch/arm/boot/dts/bcm911360k.dts        |   32 ++++++++++
 arch/arm/boot/dts/bcm958300k.dts        |   32 ++++++++++
 6 files changed, 273 insertions(+)
 create mode 100644 arch/arm/boot/dts/bcm-cygnus-clock.dtsi
 create mode 100644 arch/arm/boot/dts/bcm-cygnus.dtsi
 create mode 100644 arch/arm/boot/dts/bcm911360_entphn.dts
 create mode 100644 arch/arm/boot/dts/bcm911360k.dts
 create mode 100644 arch/arm/boot/dts/bcm958300k.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 38c89ca..4b3a590 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -54,6 +54,10 @@ dtb-$(CONFIG_ARCH_AT91)	+= at91-sama5d4ek.dtb
 dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
 dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
+dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
+	bcm911360_entphn.dtb \
+	bcm911360k.dtb \
+	bcm958300k.dtb
 dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
 dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb
 dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
diff --git a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
new file mode 100644
index 0000000..d06172b
--- /dev/null
+++ b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+clocks {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges;
+
+	osc: oscillator {
+		compatible = "fixed-clock";
+		#clock-cells = <1>;
+		clock-frequency = <25000000>;
+	};
+
+	apb_clk: apb_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1000000000>;
+	};
+
+	periph_clk: periph_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <500000000>;
+	};
+
+	sdio_clk: lcpll_ch2 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <200000000>;
+	};
+
+	axi81_clk: axi81_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	keypad_clk: keypad_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <31806>;
+	};
+
+	adc_clk: adc_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1562500>;
+	};
+
+	pwm_clk: pwm_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1000000>;
+	};
+
+	lcd_clk: mipipll_ch1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+};
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
new file mode 100644
index 0000000..9c650ab
--- /dev/null
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "brcm,cygnus";
+	model = "Broadcom Cygnus SoC";
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <0x0>;
+		};
+	};
+
+	/include/ "bcm-cygnus-clock.dtsi"
+
+	amba {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "arm,amba-bus", "simple-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		wdt@18009000 {
+			 compatible = "arm,sp805" , "arm,primecell";
+			 reg = <0x18009000 0x1000>;
+			 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+			 clocks = <&axi81_clk>;
+			 clock-names = "apb_pclk";
+		};
+	};
+
+	uart3: serial@18023000 {
+		compatible = "snps,dw-apb-uart";
+		reg = <0x18023000 0x100>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <100000000>;
+		clocks = <&axi81_clk>;
+		status = "okay";
+	};
+
+	uart0: serial@18020000 {
+		compatible = "snps,dw-apb-uart";
+		reg = <0x18020000 0x100>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&axi81_clk>;
+		clock-frequency = <100000000>;
+		status = "okay";
+	};
+
+	gic: interrupt-controller@19021000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+		interrupt-controller;
+		reg = <0x19021000 0x1000>,
+		      <0x19020100 0x100>;
+	};
+
+	L2: l2-cache {
+		compatible = "arm,pl310-cache";
+		reg = <0x19022000 0x1000>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	timer@19020200 {
+		compatible = "arm,cortex-a9-global-timer";
+		reg = <0x19020200 0x100>;
+		interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&periph_clk>;
+	};
+
+};
diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts
new file mode 100644
index 0000000..9de5e87
--- /dev/null
+++ b/arch/arm/boot/dts/bcm911360_entphn.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "bcm-cygnus.dtsi"
+
+/ {
+	model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)";
+	compatible = "brcm,bcm11360", "brcm,cygnus";
+
+	aliases {
+		serial0 = &uart3;
+		serial1 = &uart0;
+	};
+
+	chosen {
+		stdout-path = &uart3;
+		bootargs = "console=ttyS0,115200";
+	};
+};
diff --git a/arch/arm/boot/dts/bcm911360k.dts b/arch/arm/boot/dts/bcm911360k.dts
new file mode 100644
index 0000000..dd4f102
--- /dev/null
+++ b/arch/arm/boot/dts/bcm911360k.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "bcm-cygnus.dtsi"
+
+/ {
+	model = "Cygnus SVK (BCM911360K)";
+	compatible = "brcm,bcm11360", "brcm,cygnus";
+
+	aliases {
+		serial0 = &uart3;
+		serial1 = &uart0;
+	};
+
+	chosen {
+		stdout-path = &uart3;
+		bootargs = "console=ttyS0,115200";
+	};
+};
diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts
new file mode 100644
index 0000000..f8b9625
--- /dev/null
+++ b/arch/arm/boot/dts/bcm958300k.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "bcm-cygnus.dtsi"
+
+/ {
+	model = "Cygnus SVK (BCM958300K)";
+	compatible = "brcm,bcm58300", "brcm,cygnus";
+
+	aliases {
+		serial0 = &uart3;
+		serial1 = &uart0;
+	};
+
+	chosen {
+		stdout-path = &uart3;
+		bootargs = "console=ttyS0,115200";
+	};
+};
-- 
1.7.9.5

[PATCH v8 5/8] MAINTAINERS: Entry for Cygnus/iproc arm architecture

[Scott Branden]

Acked-by: Jonathan Richardson <jonathar@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 MAINTAINERS |   14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index dab92a7..15a3d89 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2129,6 +2129,20 @@ L:	linux-scsi@vger.kernel.org
 S:	Supported
 F:	drivers/scsi/bnx2i/
 
+BROADCOM CYGNUS/IPROC ARM ARCHITECTURE
+M:	Ray Jui <rjui@broadcom.com>
+M:	Scott Branden <sbranden@broadcom.com>
+L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L:	bcm-kernel-feedback-list@broadcom.com
+T:	git git://git.github.com/brcm/linux.git
+S:	Maintained
+N:	iproc
+N:	cygnus
+N:	bcm9113*
+N:	bcm9583*
+N:	bcm583*
+N:	bcm113*
+
 BROADCOM KONA GPIO DRIVER
 M:	Ray Jui <rjui@broadcom.com>
 L:	bcm-kernel-feedback-list@broadcom.com
-- 
1.7.9.5

[PATCH v8 6/8] ARM: mach-bcm: Consolidate currently supported IPROC SoCs

[Scott Branden]

Move ARCH_BCM_5301X subarch under ARCH_IPROC architecture.
Additional IPROC chipsets that share a lot of commonality should be
added under ARCH_IPROC as well.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/mach-bcm/Kconfig |   37 ++++++++++++++++---------------------
 1 file changed, 16 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 73d95c2..6e79696 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -35,6 +35,22 @@ config ARCH_BCM_CYGNUS
 	  BCM11300, BCM11320, BCM11350, BCM11360,
 	  BCM58300, BCM58302, BCM58303, BCM58305.
 
+config ARCH_BCM_5301X
+	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
+	select ARCH_BCM_IPROC
+	help
+	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
+
+	  This is a network SoC line mostly used in home routers and
+	  wifi access points, it's internal name is Northstar.
+	  This inclused the following SoC: BCM53010, BCM53011, BCM53012,
+	  BCM53014, BCM53015, BCM53016, BCM53017, BCM53018, BCM4707,
+	  BCM4708 and BCM4709.
+
+	  Do not confuse this with the BCM4760 which is a totally
+	  different SoC or with the older BCM47XX and BCM53XX based
+	  network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
+
 config ARCH_BCM_MOBILE
 	bool "Broadcom Mobile SoC Support" if ARCH_MULTI_V7
 	select ARCH_REQUIRE_GPIOLIB
@@ -110,27 +126,6 @@ config ARCH_BCM2835
 	  This enables support for the Broadcom BCM2835 SoC. This SoC is
 	  used in the Raspberry Pi and Roku 2 devices.
 
-config ARCH_BCM_5301X
-	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
-	select ARM_GIC
-	select CACHE_L2X0
-	select HAVE_ARM_SCU if SMP
-	select HAVE_ARM_TWD if SMP
-	select ARM_GLOBAL_TIMER
-	select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
-	help
-	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
-
-	  This is a network SoC line mostly used in home routers and
-	  wifi access points, it's internal name is Northstar.
-	  This inclused the following SoC: BCM53010, BCM53011, BCM53012,
-	  BCM53014, BCM53015, BCM53016, BCM53017, BCM53018, BCM4707,
-	  BCM4708 and BCM4709.
-
-	  Do not confuse this with the BCM4760 which is a totally
-	  different SoC or with the older BCM47XX and BCM53XX based
-	  network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
-
 config ARCH_BCM_63XX
 	bool "Broadcom BCM63xx DSL SoC" if ARCH_MULTI_V7
 	depends on MMU
-- 
1.7.9.5

[PATCH v8 7/8] ARM: mach-bcm: ARCH_BCM_MOBILE: remove one level of menu from Kconfig

[Scott Branden]

remove menu "Broadcom Mobile SoC Selection"
This requires:
- selecting ARCH_BCM_MOBILE based on SoC selections
- fixup bcm_defconfig and multi_v7_defconfig to work with new menu levels.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/configs/bcm_defconfig      |    3 ++-
 arch/arm/configs/multi_v7_defconfig |    3 ++-
 arch/arm/mach-bcm/Kconfig           |   26 ++++++++++----------------
 3 files changed, 14 insertions(+), 18 deletions(-)

diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
index bc614f4..83a87e4 100644
--- a/arch/arm/configs/bcm_defconfig
+++ b/arch/arm/configs/bcm_defconfig
@@ -25,7 +25,8 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_ARCH_BCM=y
-CONFIG_ARCH_BCM_MOBILE=y
+CONFIG_ARCH_BCM_21664=y
+CONFIG_ARCH_BCM_281XX=y
 CONFIG_ARM_THUMBEE=y
 CONFIG_SMP=y
 CONFIG_PREEMPT=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index f1dc7fc..6e0d7cb 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -17,7 +17,8 @@ CONFIG_MACH_ARMADA_38X=y
 CONFIG_MACH_ARMADA_XP=y
 CONFIG_MACH_DOVE=y
 CONFIG_ARCH_BCM=y
-CONFIG_ARCH_BCM_MOBILE=y
+CONFIG_ARCH_BCM_21664=y
+CONFIG_ARCH_BCM_281XX=y
 CONFIG_ARCH_BCM_5301X=y
 CONFIG_ARCH_BRCMSTB=y
 CONFIG_ARCH_BERLIN=y
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 6e79696..cceb69f 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -51,8 +51,10 @@ config ARCH_BCM_5301X
 	  different SoC or with the older BCM47XX and BCM53XX based
 	  network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
 
+comment "KONA architected SoCs"
+
 config ARCH_BCM_MOBILE
-	bool "Broadcom Mobile SoC Support" if ARCH_MULTI_V7
+	bool
 	select ARCH_REQUIRE_GPIOLIB
 	select ARM_ERRATA_754322
 	select ARM_ERRATA_775420
@@ -61,16 +63,13 @@ config ARCH_BCM_MOBILE
 	select TICK_ONESHOT
 	select HAVE_ARM_ARCH_TIMER
 	select PINCTRL
+	select ARCH_BCM_MOBILE_SMP if SMP
 	help
 	  This enables support for systems based on Broadcom mobile SoCs.
 
-if ARCH_BCM_MOBILE
-
-menu "Broadcom Mobile SoC Selection"
-
 config ARCH_BCM_281XX
 	bool "Broadcom BCM281XX SoC family"
-	default y
+	select ARCH_BCM_MOBILE
 	select HAVE_SMP
 	help
 	  Enable support for the BCM281XX family, which includes
@@ -79,7 +78,7 @@ config ARCH_BCM_281XX
 
 config ARCH_BCM_21664
 	bool "Broadcom BCM21664 SoC family"
-	default y
+	select ARCH_BCM_MOBILE
 	select HAVE_SMP
 	help
 	  Enable support for the BCM21664 family, which includes
@@ -87,19 +86,18 @@ config ARCH_BCM_21664
 
 config ARCH_BCM_MOBILE_L2_CACHE
 	bool "Broadcom mobile SoC level 2 cache support"
-	depends on (ARCH_BCM_281XX || ARCH_BCM_21664)
+	depends on ARCH_BCM_MOBILE
 	default y
 	select CACHE_L2X0
 	select ARCH_BCM_MOBILE_SMC
 
 config ARCH_BCM_MOBILE_SMC
 	bool
-	depends on ARCH_BCM_281XX || ARCH_BCM_21664
+	depends on ARCH_BCM_MOBILE
 
 config ARCH_BCM_MOBILE_SMP
-	bool "Broadcom mobile SoC SMP support"
-	depends on (ARCH_BCM_281XX || ARCH_BCM_21664) && SMP
-	default y
+	bool
+	depends on ARCH_BCM_MOBILE
 	select HAVE_ARM_SCU
 	select ARM_ERRATA_764369
 	help
@@ -107,10 +105,6 @@ config ARCH_BCM_MOBILE_SMP
 	  Provided as an option so SMP support for SoCs of this type
 	  can be disabled for an SMP-enabled kernel.
 
-endmenu
-
-endif
-
 comment "Other Architectures"
 
 config ARCH_BCM2835
-- 
1.7.9.5

[PATCH v8 8/8] ARM: multi_v7_defconfig: Enable Broadcom Cygnus

[Scott Branden]

From: Ray Jui <rjui@broadcom.com>

Enable Broadcom Cygnus platform support in multi_v7_defconfig

Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/configs/multi_v7_defconfig |    1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 6e0d7cb..c223da3 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -17,6 +17,7 @@ CONFIG_MACH_ARMADA_38X=y
 CONFIG_MACH_ARMADA_XP=y
 CONFIG_MACH_DOVE=y
 CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BCM_CYGNUS=y
 CONFIG_ARCH_BCM_21664=y
 CONFIG_ARCH_BCM_281XX=y
 CONFIG_ARCH_BCM_5301X=y
-- 
1.7.9.5

Re: [PATCH v8 8/8] ARM: multi_v7_defconfig: Enable Broadcom Cygnus

[Arnd Bergmann]

On Tuesday 28 October 2014 12:53:12 Scott Branden wrote:
> From: Ray Jui <rjui@broadcom.com>
> 
> Enable Broadcom Cygnus platform support in multi_v7_defconfig
> 
> Signed-off-by: Ray Jui <rjui@broadcom.com>
> Signed-off-by: Scott Branden <sbranden@broadcom.com>
> 

Just to be sure: did you check that multi_v7_defconfig contains
all the drivers you need that you enable in your other defconfig?

	Arnd

Re: [PATCH v8 8/8] ARM: multi_v7_defconfig: Enable Broadcom Cygnus

[Scott Branden]

On 14-10-28 01:01 PM, Arnd Bergmann wrote:
> On Tuesday 28 October 2014 12:53:12 Scott Branden wrote:
>> From: Ray Jui <rjui@broadcom.com>
>>
>> Enable Broadcom Cygnus platform support in multi_v7_defconfig
>>
>> Signed-off-by: Ray Jui <rjui@broadcom.com>
>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>>
>
> Just to be sure: did you check that multi_v7_defconfig contains
> all the drivers you need that you enable in your other defconfig?
No - the other defconfig has more that have not been tested on the 
device.  The defconfig builds, but the other drivers haven't been 
tested.  I guess we can try adding them to the multi_defconfig right now 
as well or wait until we have tested them?  There will need to be 
addition dts changes in the future after we have tested the other drivers.

Can we wait to add them to multi_v7_defconfig or do you want them in 
this patchset?
>
> 	Arnd
>

Re: [PATCH v8 8/8] ARM: multi_v7_defconfig: Enable Broadcom Cygnus

[Arnd Bergmann]

On Tuesday 28 October 2014 13:06:28 Scott Branden wrote:
> On 14-10-28 01:01 PM, Arnd Bergmann wrote:
> > On Tuesday 28 October 2014 12:53:12 Scott Branden wrote:
> >> From: Ray Jui <rjui@broadcom.com>
> >>
> >> Enable Broadcom Cygnus platform support in multi_v7_defconfig
> >>
> >> Signed-off-by: Ray Jui <rjui@broadcom.com>
> >> Signed-off-by: Scott Branden <sbranden@broadcom.com>
> >>
> >
> > Just to be sure: did you check that multi_v7_defconfig contains
> > all the drivers you need that you enable in your other defconfig?
> No - the other defconfig has more that have not been tested on the 
> device.  The defconfig builds, but the other drivers haven't been 
> tested.  I guess we can try adding them to the multi_defconfig right now 
> as well or wait until we have tested them?  There will need to be 
> addition dts changes in the future after we have tested the other drivers.
> 
> Can we wait to add them to multi_v7_defconfig or do you want them in 
> this patchset?

The important part is that you don't break other platforms, and that
is independent of whether the code actually does the right thing.

If you know that you will need certain drivers to make use of
the platform, just enable them now.

	Arnd

[PATCH v9 0/8] Add initial support for Broadcom Cygnus SoC

[Scott Branden]

This patchset contains initial support for Broadcom's Cygnus SoC based on our
iProc architecture. Initial support is minimal and includes just the mach
platform code, clock driver, and a basic device tree configuration. Peripheral
drivers will be submitted soon, as will device tree configurations for other
Cygnus board variants.

Changes from v8:
 - enabled additional drivers in multi_v7_defconfig used by Cygnus

Changes from v7:
 - Fixed dts to move uart code to board specific dts files
 - Add Cygnus to multi_v7_defconfig. It boots.

Changes from v6:
 - Additional patch added for cleanup of other areas of mach-bcm/Kconfig
   discovered during Cygnus submission review to:
   - removed one level of menu for ARCH_BCM_MOBILE in mach-bcm-Kconfig based
     on feedback from Arnd
   - added comment sections to Kconfig to identify SoC architecture groupings

Changes from v5:
 - removed one level of menu used in mach-bcm/Kconfig
 - changed MAINTAINERS to use N: to support all files associated with iproc
   and cygnus going forward
 - updated bcm_cygnus_defconfig to remove some DEBUG options that greatly
   hamper performance

Changes from v4:
 - simple clock tree used. reworked clock driver will be submitted later
 - fixed MAINTAINERS patchset error
 - removed DEBUG_UART_8250 Kconfig.debug legacy support
 - made ARCH_BCM_IPROC a silent Kconfig option
 - removed multi_v7_defconfig as it is not needed at this time, can
   support in future patchset but does not seem optimal configs for our
   current usage.
 
Changes from v3:
 - restart functionality removed.  Will be added in a different patchset
   in drivers/power
 - removed NEON init sequence.  Will be moved to bootloader
 - cleaned up Kconfigs for ARCH_BCM_CYGNUS by removing unnecessary selects
 - consolidated ARCH_BCM_IPROC with select from ARCH_BCM_CYGNUS and
   ARCH_BCM5301X
 - removed bcm911360_entphn binding
 - added documentation for SoCs currently supported in Cygnus family

Changes from v2:
 - rebased to 3.17 kernel

Changes from v1:
 - Address code review comments as per previous responses.
 - Copyright headers updated to remove Broadcom URL.
 - mach platform code still contains hard coded addresses. These address are
   the same for all Cygnus variants. Could you please provide guidance on where
   they should go if you would still like them changed.  There does not seem to
   be a reason to change them to device tree as they do not change.

Jonathan Richardson (3):
  ARM: cygnus: Initial support for Broadcom Cygnus SoC
  dt-bindings: Document Broadcom Cygnus SoC and clocks
  ARM: cygnus defconfig : Initial defconfig for Broadcom Cygnus SoC

Ray Jui (1):
  ARM: multi_v7_defconfig: Enable Broadcom Cygnus

Scott Branden (4):
  ARM: dts: Enable Broadcom Cygnus SoC
  MAINTAINERS: Entry for Cygnus/iproc arm architecture
  ARM: mach-bcm: Consolidate currently supported IPROC SoCs
  ARM: mach-bcm: ARCH_BCM_MOBILE: remove one level of menu from Kconfig

 .../devicetree/bindings/arm/bcm/cygnus.txt         |   31 +++
 .../devicetree/bindings/clock/bcm-cygnus-clock.txt |   34 +++
 MAINTAINERS                                        |   14 ++
 arch/arm/boot/dts/Makefile                         |    4 +
 arch/arm/boot/dts/bcm-cygnus-clock.dtsi            |   73 ++++++
 arch/arm/boot/dts/bcm-cygnus.dtsi                  |  100 +++++++++
 arch/arm/boot/dts/bcm911360_entphn.dts             |   32 +++
 arch/arm/boot/dts/bcm911360k.dts                   |   32 +++
 arch/arm/boot/dts/bcm958300k.dts                   |   32 +++
 arch/arm/configs/bcm_cygnus_defconfig              |  237 ++++++++++++++++++++
 arch/arm/configs/bcm_defconfig                     |    3 +-
 arch/arm/configs/multi_v7_defconfig                |   21 +-
 arch/arm/mach-bcm/Kconfig                          |   93 +++++---
 arch/arm/mach-bcm/Makefile                         |    3 +
 arch/arm/mach-bcm/bcm_cygnus.c                     |   26 +++
 15 files changed, 697 insertions(+), 38 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/cygnus.txt
 create mode 100644 Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
 create mode 100644 arch/arm/boot/dts/bcm-cygnus-clock.dtsi
 create mode 100644 arch/arm/boot/dts/bcm-cygnus.dtsi
 create mode 100644 arch/arm/boot/dts/bcm911360_entphn.dts
 create mode 100644 arch/arm/boot/dts/bcm911360k.dts
 create mode 100644 arch/arm/boot/dts/bcm958300k.dts
 create mode 100644 arch/arm/configs/bcm_cygnus_defconfig
 create mode 100644 arch/arm/mach-bcm/bcm_cygnus.c

-- 
1.7.9.5

[PATCH v9 1/8] ARM: cygnus: Initial support for Broadcom Cygnus SoC

[Scott Branden]

From: Jonathan Richardson <jonathar@broadcom.com>

Adds initial support for the Cygnus SoC based on Broadcom’s iProc series.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Desmond Liu <desmondl@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/mach-bcm/Kconfig      |   32 ++++++++++++++++++++++++++++++++
 arch/arm/mach-bcm/Makefile     |    3 +++
 arch/arm/mach-bcm/bcm_cygnus.c |   26 ++++++++++++++++++++++++++
 3 files changed, 61 insertions(+)
 create mode 100644 arch/arm/mach-bcm/bcm_cygnus.c

diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 2abad74..73d95c2 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -5,6 +5,36 @@ menuconfig ARCH_BCM
 
 if ARCH_BCM
 
+comment "IPROC architected SoCs"
+
+config ARCH_BCM_IPROC
+	bool
+	select ARM_GIC
+	select CACHE_L2X0
+	select HAVE_ARM_SCU if SMP
+	select HAVE_ARM_TWD if SMP
+	select ARM_GLOBAL_TIMER
+
+	select CLKSRC_MMIO
+	select ARCH_REQUIRE_GPIOLIB
+	select ARM_AMBA
+	select PINCTRL
+	help
+	  This enables support for systems based on Broadcom IPROC architected SoCs.
+	  The IPROC complex contains one or more ARM CPUs along with common
+	  core periperals. Application specific SoCs are created by adding a
+	  uArchitecture containing peripherals outside of the IPROC complex.
+	  Currently supported SoCs are Cygnus.
+
+config ARCH_BCM_CYGNUS
+	bool "Broadcom Cygnus Support" if ARCH_MULTI_V7
+	select ARCH_BCM_IPROC
+	help
+	  Enable support for the Cygnus family,
+	  which includes the following variants:
+	  BCM11300, BCM11320, BCM11350, BCM11360,
+	  BCM58300, BCM58302, BCM58303, BCM58305.
+
 config ARCH_BCM_MOBILE
 	bool "Broadcom Mobile SoC Support" if ARCH_MULTI_V7
 	select ARCH_REQUIRE_GPIOLIB
@@ -65,6 +95,8 @@ endmenu
 
 endif
 
+comment "Other Architectures"
+
 config ARCH_BCM2835
 	bool "Broadcom BCM2835 family" if ARCH_MULTI_V6
 	select ARCH_REQUIRE_GPIOLIB
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 300ae4b..34d45ba 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -10,6 +10,9 @@
 # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
 
+# Cygnus
+obj-$(CONFIG_ARCH_BCM_CYGNUS) +=  bcm_cygnus.o
+
 # BCM281XX
 obj-$(CONFIG_ARCH_BCM_281XX)	+= board_bcm281xx.o
 
diff --git a/arch/arm/mach-bcm/bcm_cygnus.c b/arch/arm/mach-bcm/bcm_cygnus.c
new file mode 100644
index 0000000..41b4933
--- /dev/null
+++ b/arch/arm/mach-bcm/bcm_cygnus.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <asm/mach/arch.h>
+
+static const char const *bcm_cygnus_dt_compat[] = {
+	"brcm,cygnus",
+	NULL,
+};
+
+DT_MACHINE_START(BCM_CYGNUS_DT, "Broadcom Cygnus SoC")
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
+	.dt_compat = bcm_cygnus_dt_compat,
+MACHINE_END
-- 
1.7.9.5

[PATCH v9 2/8] dt-bindings: Document Broadcom Cygnus SoC and clocks

[Scott Branden]

From: Jonathan Richardson <jonathar@broadcom.com>

Reviewed-by: Arun Parameswaran <aparames@broadcom.com>
Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 .../devicetree/bindings/arm/bcm/cygnus.txt         |   31 ++++++++++++++++++
 .../devicetree/bindings/clock/bcm-cygnus-clock.txt |   34 ++++++++++++++++++++
 2 files changed, 65 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/bcm/cygnus.txt
 create mode 100644 Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt

diff --git a/Documentation/devicetree/bindings/arm/bcm/cygnus.txt b/Documentation/devicetree/bindings/arm/bcm/cygnus.txt
new file mode 100644
index 0000000..4c77169
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/cygnus.txt
@@ -0,0 +1,31 @@
+Broadcom Cygnus device tree bindings
+------------------------------------
+
+
+Boards with Cygnus SoCs shall have the following properties:
+
+Required root node property:
+
+BCM11300
+compatible = "brcm,bcm11300", "brcm,cygnus";
+
+BCM11320
+compatible = "brcm,bcm11320", "brcm,cygnus";
+
+BCM11350
+compatible = "brcm,bcm11350", "brcm,cygnus";
+
+BCM11360
+compatible = "brcm,bcm11360", "brcm,cygnus";
+
+BCM58300
+compatible = "brcm,bcm58300", "brcm,cygnus";
+
+BCM58302
+compatible = "brcm,bcm58302", "brcm,cygnus";
+
+BCM58303
+compatible = "brcm,bcm58303", "brcm,cygnus";
+
+BCM58305
+compatible = "brcm,bcm58305", "brcm,cygnus";
diff --git a/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt b/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
new file mode 100644
index 0000000..00d26ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
@@ -0,0 +1,34 @@
+Broadcom Cygnus Clocks
+
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Currently various "fixed" clocks are declared for peripheral drivers that use
+the common clock framework to reference their core clocks. Proper support of
+these clocks will be added later
+
+Device tree example:
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		osc: oscillator {
+			compatible = "fixed-clock";
+			#clock-cells = <1>;
+			clock-frequency = <25000000>;
+		};
+
+		apb_clk: apb_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <1000000000>;
+		};
+
+		periph_clk: periph_clk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <500000000>;
+		};
+	};
-- 
1.7.9.5

[PATCH v9 3/8] ARM: cygnus defconfig : Initial defconfig for Broadcom Cygnus SoC

[Scott Branden]

From: Jonathan Richardson <jonathar@broadcom.com>

This defconfig is utilized so a customer or developer can understand
what kernel drivers are utilized by the Cygnus SoC.  It also enables
debug configs which should be disabled if optimal performance is
desired.

Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/configs/bcm_cygnus_defconfig |  237 +++++++++++++++++++++++++++++++++
 1 file changed, 237 insertions(+)
 create mode 100644 arch/arm/configs/bcm_cygnus_defconfig

diff --git a/arch/arm/configs/bcm_cygnus_defconfig b/arch/arm/configs/bcm_cygnus_defconfig
new file mode 100644
index 0000000..9ad77a8
--- /dev/null
+++ b/arch/arm/configs/bcm_cygnus_defconfig
@@ -0,0 +1,237 @@
+CONFIG_KERNEL_XZ=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_FHANDLE=y
+CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=19
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_BLK_CGROUP=y
+CONFIG_NAMESPACES=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_JUMP_LABEL=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BCM_CYGNUS=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_PCI=y
+CONFIG_PCI_DEBUG=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+# CONFIG_COMPACTION is not set
+# CONFIG_ATAGS is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_TCP_CONG_ADVANCED=y
+# CONFIG_TCP_CONG_BIC is not set
+# CONFIG_TCP_CONG_WESTWOOD is not set
+# CONFIG_TCP_CONG_HTCP is not set
+CONFIG_IPV6=y
+# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET6_XFRM_MODE_BEET is not set
+# CONFIG_IPV6_SIT is not set
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+CONFIG_NETFILTER=y
+# CONFIG_BRIDGE_NETFILTER is not set
+CONFIG_NF_CONNTRACK=y
+# CONFIG_NF_CONNTRACK_PROCFS is not set
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_RAW=y
+CONFIG_NF_CONNTRACK_IPV6=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_MATCH_AH=y
+CONFIG_IP6_NF_MATCH_EUI64=y
+CONFIG_IP6_NF_MATCH_FRAG=y
+CONFIG_IP6_NF_MATCH_OPTS=y
+CONFIG_IP6_NF_MATCH_IPV6HEADER=y
+CONFIG_IP6_NF_MATCH_MH=y
+CONFIG_IP6_NF_MATCH_RT=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_IP6_NF_RAW=y
+CONFIG_BRIDGE=y
+# CONFIG_BRIDGE_IGMP_SNOOPING is not set
+CONFIG_VLAN_8021Q=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_FQ_CODEL=y
+CONFIG_CFG80211=y
+# CONFIG_CFG80211_DEFAULT_PS is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_RFKILL=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_PHYLIB=y
+CONFIG_BROADCOM_PHY=y
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
+CONFIG_I2C_SMBUS=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=y
+# CONFIG_USB_GSPCA is not set
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_DEBUG=y
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_SOC=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_RTC_CLASS=y
+CONFIG_PWM=y
+CONFIG_EXT4_FS=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_UBIFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_INFO=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_OBJECTS=y
+CONFIG_DEBUG_OBJECTS_RCU_HEAD=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=110
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_SCHEDSTATS=y
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_ATOMIC_SLEEP=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_UART_8250=y
+CONFIG_DEBUG_UART_PHYS=0x18023000
+CONFIG_DEBUG_UART_VIRT=0xf1023000
+CONFIG_EARLY_PRINTK=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
-- 
1.7.9.5

[PATCH v9 4/8] ARM: dts: Enable Broadcom Cygnus SoC

[Scott Branden]

DT files to enable cygnus consisting on reference designs
and cygnus core configuration.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Arun Parameswaran <aparames@broadcom.com>
Tested-by: Jonathan Richardson <jonathar@broadcom.com>
Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/boot/dts/Makefile              |    4 ++
 arch/arm/boot/dts/bcm-cygnus-clock.dtsi |   73 ++++++++++++++++++++++
 arch/arm/boot/dts/bcm-cygnus.dtsi       |  100 +++++++++++++++++++++++++++++++
 arch/arm/boot/dts/bcm911360_entphn.dts  |   32 ++++++++++
 arch/arm/boot/dts/bcm911360k.dts        |   32 ++++++++++
 arch/arm/boot/dts/bcm958300k.dts        |   32 ++++++++++
 6 files changed, 273 insertions(+)
 create mode 100644 arch/arm/boot/dts/bcm-cygnus-clock.dtsi
 create mode 100644 arch/arm/boot/dts/bcm-cygnus.dtsi
 create mode 100644 arch/arm/boot/dts/bcm911360_entphn.dts
 create mode 100644 arch/arm/boot/dts/bcm911360k.dts
 create mode 100644 arch/arm/boot/dts/bcm958300k.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 38c89ca..4b3a590 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -54,6 +54,10 @@ dtb-$(CONFIG_ARCH_AT91)	+= at91-sama5d4ek.dtb
 dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
 dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
+dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
+	bcm911360_entphn.dtb \
+	bcm911360k.dtb \
+	bcm958300k.dtb
 dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
 dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb
 dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
diff --git a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
new file mode 100644
index 0000000..d06172b
--- /dev/null
+++ b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+clocks {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges;
+
+	osc: oscillator {
+		compatible = "fixed-clock";
+		#clock-cells = <1>;
+		clock-frequency = <25000000>;
+	};
+
+	apb_clk: apb_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1000000000>;
+	};
+
+	periph_clk: periph_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <500000000>;
+	};
+
+	sdio_clk: lcpll_ch2 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <200000000>;
+	};
+
+	axi81_clk: axi81_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	keypad_clk: keypad_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <31806>;
+	};
+
+	adc_clk: adc_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1562500>;
+	};
+
+	pwm_clk: pwm_clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1000000>;
+	};
+
+	lcd_clk: mipipll_ch1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+};
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
new file mode 100644
index 0000000..9c650ab
--- /dev/null
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "brcm,cygnus";
+	model = "Broadcom Cygnus SoC";
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			next-level-cache = <&L2>;
+			reg = <0x0>;
+		};
+	};
+
+	/include/ "bcm-cygnus-clock.dtsi"
+
+	amba {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "arm,amba-bus", "simple-bus";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		wdt@18009000 {
+			 compatible = "arm,sp805" , "arm,primecell";
+			 reg = <0x18009000 0x1000>;
+			 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+			 clocks = <&axi81_clk>;
+			 clock-names = "apb_pclk";
+		};
+	};
+
+	uart3: serial@18023000 {
+		compatible = "snps,dw-apb-uart";
+		reg = <0x18023000 0x100>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <100000000>;
+		clocks = <&axi81_clk>;
+		status = "okay";
+	};
+
+	uart0: serial@18020000 {
+		compatible = "snps,dw-apb-uart";
+		reg = <0x18020000 0x100>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&axi81_clk>;
+		clock-frequency = <100000000>;
+		status = "okay";
+	};
+
+	gic: interrupt-controller@19021000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+		interrupt-controller;
+		reg = <0x19021000 0x1000>,
+		      <0x19020100 0x100>;
+	};
+
+	L2: l2-cache {
+		compatible = "arm,pl310-cache";
+		reg = <0x19022000 0x1000>;
+		cache-unified;
+		cache-level = <2>;
+	};
+
+	timer@19020200 {
+		compatible = "arm,cortex-a9-global-timer";
+		reg = <0x19020200 0x100>;
+		interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&periph_clk>;
+	};
+
+};
diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts
new file mode 100644
index 0000000..9de5e87
--- /dev/null
+++ b/arch/arm/boot/dts/bcm911360_entphn.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "bcm-cygnus.dtsi"
+
+/ {
+	model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)";
+	compatible = "brcm,bcm11360", "brcm,cygnus";
+
+	aliases {
+		serial0 = &uart3;
+		serial1 = &uart0;
+	};
+
+	chosen {
+		stdout-path = &uart3;
+		bootargs = "console=ttyS0,115200";
+	};
+};
diff --git a/arch/arm/boot/dts/bcm911360k.dts b/arch/arm/boot/dts/bcm911360k.dts
new file mode 100644
index 0000000..dd4f102
--- /dev/null
+++ b/arch/arm/boot/dts/bcm911360k.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "bcm-cygnus.dtsi"
+
+/ {
+	model = "Cygnus SVK (BCM911360K)";
+	compatible = "brcm,bcm11360", "brcm,cygnus";
+
+	aliases {
+		serial0 = &uart3;
+		serial1 = &uart0;
+	};
+
+	chosen {
+		stdout-path = &uart3;
+		bootargs = "console=ttyS0,115200";
+	};
+};
diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts
new file mode 100644
index 0000000..f8b9625
--- /dev/null
+++ b/arch/arm/boot/dts/bcm958300k.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2014 Broadcom Corporation.  All rights reserved.
+ *
+ * Unless you and Broadcom execute a separate written software license
+ * agreement governing use of this software, this software is licensed to you
+ * under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "bcm-cygnus.dtsi"
+
+/ {
+	model = "Cygnus SVK (BCM958300K)";
+	compatible = "brcm,bcm58300", "brcm,cygnus";
+
+	aliases {
+		serial0 = &uart3;
+		serial1 = &uart0;
+	};
+
+	chosen {
+		stdout-path = &uart3;
+		bootargs = "console=ttyS0,115200";
+	};
+};
-- 
1.7.9.5

[PATCH v9 5/8] MAINTAINERS: Entry for Cygnus/iproc arm architecture

[Scott Branden]

Acked-by: Jonathan Richardson <jonathar@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 MAINTAINERS |   14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index dab92a7..15a3d89 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2129,6 +2129,20 @@ L:	linux-scsi@vger.kernel.org
 S:	Supported
 F:	drivers/scsi/bnx2i/
 
+BROADCOM CYGNUS/IPROC ARM ARCHITECTURE
+M:	Ray Jui <rjui@broadcom.com>
+M:	Scott Branden <sbranden@broadcom.com>
+L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L:	bcm-kernel-feedback-list@broadcom.com
+T:	git git://git.github.com/brcm/linux.git
+S:	Maintained
+N:	iproc
+N:	cygnus
+N:	bcm9113*
+N:	bcm9583*
+N:	bcm583*
+N:	bcm113*
+
 BROADCOM KONA GPIO DRIVER
 M:	Ray Jui <rjui@broadcom.com>
 L:	bcm-kernel-feedback-list@broadcom.com
-- 
1.7.9.5

[PATCH v9 6/8] ARM: mach-bcm: Consolidate currently supported IPROC SoCs

[Scott Branden]

Move ARCH_BCM_5301X subarch under ARCH_IPROC architecture.
Additional IPROC chipsets that share a lot of commonality should be
added under ARCH_IPROC as well.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/mach-bcm/Kconfig |   37 ++++++++++++++++---------------------
 1 file changed, 16 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 73d95c2..6e79696 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -35,6 +35,22 @@ config ARCH_BCM_CYGNUS
 	  BCM11300, BCM11320, BCM11350, BCM11360,
 	  BCM58300, BCM58302, BCM58303, BCM58305.
 
+config ARCH_BCM_5301X
+	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
+	select ARCH_BCM_IPROC
+	help
+	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
+
+	  This is a network SoC line mostly used in home routers and
+	  wifi access points, it's internal name is Northstar.
+	  This inclused the following SoC: BCM53010, BCM53011, BCM53012,
+	  BCM53014, BCM53015, BCM53016, BCM53017, BCM53018, BCM4707,
+	  BCM4708 and BCM4709.
+
+	  Do not confuse this with the BCM4760 which is a totally
+	  different SoC or with the older BCM47XX and BCM53XX based
+	  network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
+
 config ARCH_BCM_MOBILE
 	bool "Broadcom Mobile SoC Support" if ARCH_MULTI_V7
 	select ARCH_REQUIRE_GPIOLIB
@@ -110,27 +126,6 @@ config ARCH_BCM2835
 	  This enables support for the Broadcom BCM2835 SoC. This SoC is
 	  used in the Raspberry Pi and Roku 2 devices.
 
-config ARCH_BCM_5301X
-	bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
-	select ARM_GIC
-	select CACHE_L2X0
-	select HAVE_ARM_SCU if SMP
-	select HAVE_ARM_TWD if SMP
-	select ARM_GLOBAL_TIMER
-	select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
-	help
-	  Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
-
-	  This is a network SoC line mostly used in home routers and
-	  wifi access points, it's internal name is Northstar.
-	  This inclused the following SoC: BCM53010, BCM53011, BCM53012,
-	  BCM53014, BCM53015, BCM53016, BCM53017, BCM53018, BCM4707,
-	  BCM4708 and BCM4709.
-
-	  Do not confuse this with the BCM4760 which is a totally
-	  different SoC or with the older BCM47XX and BCM53XX based
-	  network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
-
 config ARCH_BCM_63XX
 	bool "Broadcom BCM63xx DSL SoC" if ARCH_MULTI_V7
 	depends on MMU
-- 
1.7.9.5

[PATCH v9 7/8] ARM: mach-bcm: ARCH_BCM_MOBILE: remove one level of menu from Kconfig

[Scott Branden]

remove menu "Broadcom Mobile SoC Selection"
This requires:
- selecting ARCH_BCM_MOBILE based on SoC selections
- fixup bcm_defconfig and multi_v7_defconfig to work with new menu levels.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/configs/bcm_defconfig      |    3 ++-
 arch/arm/configs/multi_v7_defconfig |    3 ++-
 arch/arm/mach-bcm/Kconfig           |   26 ++++++++++----------------
 3 files changed, 14 insertions(+), 18 deletions(-)

diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
index bc614f4..83a87e4 100644
--- a/arch/arm/configs/bcm_defconfig
+++ b/arch/arm/configs/bcm_defconfig
@@ -25,7 +25,8 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_ARCH_BCM=y
-CONFIG_ARCH_BCM_MOBILE=y
+CONFIG_ARCH_BCM_21664=y
+CONFIG_ARCH_BCM_281XX=y
 CONFIG_ARM_THUMBEE=y
 CONFIG_SMP=y
 CONFIG_PREEMPT=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index f1dc7fc..6e0d7cb 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -17,7 +17,8 @@ CONFIG_MACH_ARMADA_38X=y
 CONFIG_MACH_ARMADA_XP=y
 CONFIG_MACH_DOVE=y
 CONFIG_ARCH_BCM=y
-CONFIG_ARCH_BCM_MOBILE=y
+CONFIG_ARCH_BCM_21664=y
+CONFIG_ARCH_BCM_281XX=y
 CONFIG_ARCH_BCM_5301X=y
 CONFIG_ARCH_BRCMSTB=y
 CONFIG_ARCH_BERLIN=y
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 6e79696..cceb69f 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -51,8 +51,10 @@ config ARCH_BCM_5301X
 	  different SoC or with the older BCM47XX and BCM53XX based
 	  network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
 
+comment "KONA architected SoCs"
+
 config ARCH_BCM_MOBILE
-	bool "Broadcom Mobile SoC Support" if ARCH_MULTI_V7
+	bool
 	select ARCH_REQUIRE_GPIOLIB
 	select ARM_ERRATA_754322
 	select ARM_ERRATA_775420
@@ -61,16 +63,13 @@ config ARCH_BCM_MOBILE
 	select TICK_ONESHOT
 	select HAVE_ARM_ARCH_TIMER
 	select PINCTRL
+	select ARCH_BCM_MOBILE_SMP if SMP
 	help
 	  This enables support for systems based on Broadcom mobile SoCs.
 
-if ARCH_BCM_MOBILE
-
-menu "Broadcom Mobile SoC Selection"
-
 config ARCH_BCM_281XX
 	bool "Broadcom BCM281XX SoC family"
-	default y
+	select ARCH_BCM_MOBILE
 	select HAVE_SMP
 	help
 	  Enable support for the BCM281XX family, which includes
@@ -79,7 +78,7 @@ config ARCH_BCM_281XX
 
 config ARCH_BCM_21664
 	bool "Broadcom BCM21664 SoC family"
-	default y
+	select ARCH_BCM_MOBILE
 	select HAVE_SMP
 	help
 	  Enable support for the BCM21664 family, which includes
@@ -87,19 +86,18 @@ config ARCH_BCM_21664
 
 config ARCH_BCM_MOBILE_L2_CACHE
 	bool "Broadcom mobile SoC level 2 cache support"
-	depends on (ARCH_BCM_281XX || ARCH_BCM_21664)
+	depends on ARCH_BCM_MOBILE
 	default y
 	select CACHE_L2X0
 	select ARCH_BCM_MOBILE_SMC
 
 config ARCH_BCM_MOBILE_SMC
 	bool
-	depends on ARCH_BCM_281XX || ARCH_BCM_21664
+	depends on ARCH_BCM_MOBILE
 
 config ARCH_BCM_MOBILE_SMP
-	bool "Broadcom mobile SoC SMP support"
-	depends on (ARCH_BCM_281XX || ARCH_BCM_21664) && SMP
-	default y
+	bool
+	depends on ARCH_BCM_MOBILE
 	select HAVE_ARM_SCU
 	select ARM_ERRATA_764369
 	help
@@ -107,10 +105,6 @@ config ARCH_BCM_MOBILE_SMP
 	  Provided as an option so SMP support for SoCs of this type
 	  can be disabled for an SMP-enabled kernel.
 
-endmenu
-
-endif
-
 comment "Other Architectures"
 
 config ARCH_BCM2835
-- 
1.7.9.5

[PATCH v9 8/8] ARM: multi_v7_defconfig: Enable Broadcom Cygnus

[Scott Branden]

From: Ray Jui <rjui@broadcom.com>

Enable Broadcom Cygnus platform support in multi_v7_defconfig

Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/configs/multi_v7_defconfig |   18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 6e0d7cb..c72afb1 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -17,6 +17,7 @@ CONFIG_MACH_ARMADA_38X=y
 CONFIG_MACH_ARMADA_XP=y
 CONFIG_MACH_DOVE=y
 CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BCM_CYGNUS=y
 CONFIG_ARCH_BCM_21664=y
 CONFIG_ARCH_BCM_281XX=y
 CONFIG_ARCH_BCM_5301X=y
@@ -125,8 +126,12 @@ CONFIG_DMA_CMA=y
 CONFIG_CMA_SIZE_MBYTES=64
 CONFIG_OMAP_OCP2SCP=y
 CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
 CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
 CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_UBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_AD525X_DPOT=y
 CONFIG_AD525X_DPOT_I2C=y
@@ -161,6 +166,7 @@ CONFIG_TI_CPSW=y
 CONFIG_XILINX_EMACLITE=y
 CONFIG_AT803X_PHY=y
 CONFIG_MARVELL_PHY=y
+CONFIG_BROADCOM_PHY=y
 CONFIG_ICPLUS_PHY=y
 CONFIG_USB_PEGASUS=y
 CONFIG_USB_USBNET=y
@@ -234,6 +240,7 @@ CONFIG_SPI_TEGRA114=y
 CONFIG_SPI_TEGRA20_SFLASH=y
 CONFIG_SPI_TEGRA20_SLINK=y
 CONFIG_SPI_XILINX=y
+CONFIG_SPI_SPIDEV=y
 CONFIG_PINCTRL_AS3722=y
 CONFIG_PINCTRL_PALMAS=y
 CONFIG_GPIO_SYSFS=y
@@ -260,6 +267,7 @@ CONFIG_ST_THERMAL_SYSCFG=y
 CONFIG_ST_THERMAL_MEMMAP=y
 CONFIG_WATCHDOG=y
 CONFIG_XILINX_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
 CONFIG_ORION_WATCHDOG=y
 CONFIG_SUNXI_WATCHDOG=y
 CONFIG_MESON_WATCHDOG=y
@@ -307,6 +315,8 @@ CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
 CONFIG_SOUND=y
 CONFIG_SND=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_USB_AUDIO=y
 CONFIG_SND_SOC=y
 CONFIG_SND_SOC_TEGRA=y
 CONFIG_SND_SOC_TEGRA_RT5640=y
@@ -429,7 +439,12 @@ CONFIG_TI_PIPE3=y
 CONFIG_PHY_MIPHY365X=y
 CONFIG_PHY_SUN4I_USB=y
 CONFIG_EXT4_FS=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_UBIFS_FS=y
 CONFIG_TMPFS=y
 CONFIG_SQUASHFS=y
 CONFIG_SQUASHFS_LZO=y
@@ -438,6 +453,9 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3_ACL=y
 CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
 CONFIG_PRINTK_TIME=y
 CONFIG_DEBUG_FS=y
 CONFIG_MAGIC_SYSRQ=y
-- 
1.7.9.5

[PATCHv2 0/5] sdhci-bcm2835: added quirk and removed udelay in write ops

[Scott Branden]

This patch contains driver cleanup of sdhci-bcm2835.
Please note that this has not actually been tested on bcm2835 yet.
Testing comes from other devices with the same sdhci controller.

This patch is being put out for testing and acceptance on the 2835.
Please test and comment.

Scott Branden (5):
  mmc: sdhci-bcm2835: group read and write functions to improve
    readability
  mmc: sdhci-bcm2835: make shift calculations consistent
  mmc: shdci-bcm2835: add efficient back-to-back write workaround
  mmc: shdci-bcm2835: add verify for 32-bit back-to-back workaround
  mmc: sdhci-bcm2835: add sdhci quirk
    SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12

 drivers/mmc/host/Kconfig         |    9 ++
 drivers/mmc/host/sdhci-bcm2835.c |  172 +++++++++++++++++++++-----------------
 2 files changed, 105 insertions(+), 76 deletions(-)

-- 
1.7.9.5

[PATCHv2 1/5] mmc: sdhci-bcm2835: group read and write functions to improve readability

[Scott Branden]

Group the read and write functions to improve readability.  Now all
similar functions are grouped together to evaluate behaviours.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/mmc/host/sdhci-bcm2835.c |   61 +++++++++++++++++++-------------------
 1 file changed, 31 insertions(+), 30 deletions(-)

diff --git a/drivers/mmc/host/sdhci-bcm2835.c b/drivers/mmc/host/sdhci-bcm2835.c
index 439d259..c8ee02c 100644
--- a/drivers/mmc/host/sdhci-bcm2835.c
+++ b/drivers/mmc/host/sdhci-bcm2835.c
@@ -54,13 +54,6 @@ struct bcm2835_sdhci {
 	u32 shadow;
 };
 
-static void bcm2835_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
-{
-	writel(val, host->ioaddr + reg);
-
-	udelay(BCM2835_SDHCI_WRITE_DELAY);
-}
-
 static inline u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg)
 {
 	u32 val = readl(host->ioaddr + reg);
@@ -71,6 +64,34 @@ static inline u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg)
 	return val;
 }
 
+static u16 bcm2835_sdhci_readw(struct sdhci_host *host, int reg)
+{
+	u32 val = bcm2835_sdhci_readl(host, (reg & ~3));
+	u32 word_num = (reg >> 1) & 1;
+	u32 word_shift = word_num * 16;
+	u32 word = (val >> word_shift) & 0xffff;
+
+	return word;
+}
+
+static u8 bcm2835_sdhci_readb(struct sdhci_host *host, int reg)
+{
+	u32 val = bcm2835_sdhci_readl(host, (reg & ~3));
+	u32 byte_num = reg & 3;
+	u32 byte_shift = byte_num * 8;
+	u32 byte = (val >> byte_shift) & 0xff;
+
+	return byte;
+}
+
+static void bcm2835_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
+{
+	writel(val, host->ioaddr + reg);
+
+	udelay(BCM2835_SDHCI_WRITE_DELAY);
+}
+
+
 static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 {
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -88,16 +109,6 @@ static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 		bcm2835_sdhci_writel(host, newval, reg & ~3);
 }
 
-static u16 bcm2835_sdhci_readw(struct sdhci_host *host, int reg)
-{
-	u32 val = bcm2835_sdhci_readl(host, (reg & ~3));
-	u32 word_num = (reg >> 1) & 1;
-	u32 word_shift = word_num * 16;
-	u32 word = (val >> word_shift) & 0xffff;
-
-	return word;
-}
-
 static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 {
 	u32 oldval = bcm2835_sdhci_readl(host, reg & ~3);
@@ -109,28 +120,18 @@ static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 	bcm2835_sdhci_writel(host, newval, reg & ~3);
 }
 
-static u8 bcm2835_sdhci_readb(struct sdhci_host *host, int reg)
-{
-	u32 val = bcm2835_sdhci_readl(host, (reg & ~3));
-	u32 byte_num = reg & 3;
-	u32 byte_shift = byte_num * 8;
-	u32 byte = (val >> byte_shift) & 0xff;
-
-	return byte;
-}
-
 static unsigned int bcm2835_sdhci_get_min_clock(struct sdhci_host *host)
 {
 	return MIN_FREQ;
 }
 
 static const struct sdhci_ops bcm2835_sdhci_ops = {
-	.write_l = bcm2835_sdhci_writel,
-	.write_w = bcm2835_sdhci_writew,
-	.write_b = bcm2835_sdhci_writeb,
 	.read_l = bcm2835_sdhci_readl,
 	.read_w = bcm2835_sdhci_readw,
 	.read_b = bcm2835_sdhci_readb,
+	.write_l = bcm2835_sdhci_writel,
+	.write_w = bcm2835_sdhci_writew,
+	.write_b = bcm2835_sdhci_writeb,
 	.set_clock = sdhci_set_clock,
 	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
 	.get_min_clock = bcm2835_sdhci_get_min_clock,
-- 
1.7.9.5

[PATCHv2 2/5] mmc: sdhci-bcm2835: make shift calculations consistent

[Scott Branden]

Make the shift calculations consistent rather than having different
implementations to calculate the same thing.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/mmc/host/sdhci-bcm2835.c |   18 ++++++------------
 1 file changed, 6 insertions(+), 12 deletions(-)

diff --git a/drivers/mmc/host/sdhci-bcm2835.c b/drivers/mmc/host/sdhci-bcm2835.c
index c8ee02c..b6cb365 100644
--- a/drivers/mmc/host/sdhci-bcm2835.c
+++ b/drivers/mmc/host/sdhci-bcm2835.c
@@ -54,6 +54,8 @@ struct bcm2835_sdhci {
 	u32 shadow;
 };
 
+#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
+
 static inline u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg)
 {
 	u32 val = readl(host->ioaddr + reg);
@@ -67,20 +69,14 @@ static inline u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg)
 static u16 bcm2835_sdhci_readw(struct sdhci_host *host, int reg)
 {
 	u32 val = bcm2835_sdhci_readl(host, (reg & ~3));
-	u32 word_num = (reg >> 1) & 1;
-	u32 word_shift = word_num * 16;
-	u32 word = (val >> word_shift) & 0xffff;
-
+	u16 word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
 	return word;
 }
 
 static u8 bcm2835_sdhci_readb(struct sdhci_host *host, int reg)
 {
 	u32 val = bcm2835_sdhci_readl(host, (reg & ~3));
-	u32 byte_num = reg & 3;
-	u32 byte_shift = byte_num * 8;
-	u32 byte = (val >> byte_shift) & 0xff;
-
+	u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
 	return byte;
 }
 
@@ -98,8 +94,7 @@ static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 	struct bcm2835_sdhci *bcm2835_host = pltfm_host->priv;
 	u32 oldval = (reg == SDHCI_COMMAND) ? bcm2835_host->shadow :
 		bcm2835_sdhci_readl(host, reg & ~3);
-	u32 word_num = (reg >> 1) & 1;
-	u32 word_shift = word_num * 16;
+	u32 word_shift = REG_OFFSET_IN_BITS(reg);
 	u32 mask = 0xffff << word_shift;
 	u32 newval = (oldval & ~mask) | (val << word_shift);
 
@@ -112,8 +107,7 @@ static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 {
 	u32 oldval = bcm2835_sdhci_readl(host, reg & ~3);
-	u32 byte_num = reg & 3;
-	u32 byte_shift = byte_num * 8;
+	u32 byte_shift = REG_OFFSET_IN_BITS(reg);
 	u32 mask = 0xff << byte_shift;
 	u32 newval = (oldval & ~mask) | (val << byte_shift);
 
-- 
1.7.9.5

[PATCHv2 3/5] mmc: shdci-bcm2835: add efficient back-to-back write workaround

[Scott Branden]

The bcm2835 has clock domain issues when back to back writes to certain
registers are written.  The existing driver works around this issue with
udelay.  A more efficient method is to store the 8 and 16 bit writes
to the registers affected and then write them as 32 bits at the appropriate
time.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/mmc/host/sdhci-bcm2835.c |  103 ++++++++++++++++++++------------------
 1 file changed, 55 insertions(+), 48 deletions(-)

diff --git a/drivers/mmc/host/sdhci-bcm2835.c b/drivers/mmc/host/sdhci-bcm2835.c
index b6cb365..f8c450a 100644
--- a/drivers/mmc/host/sdhci-bcm2835.c
+++ b/drivers/mmc/host/sdhci-bcm2835.c
@@ -24,34 +24,9 @@
 #include <linux/mmc/host.h>
 #include "sdhci-pltfm.h"
 
-/*
- * 400KHz is max freq for card ID etc. Use that as min card clock. We need to
- * know the min to enable static calculation of max BCM2835_SDHCI_WRITE_DELAY.
- */
-#define MIN_FREQ 400000
-
-/*
- * The Arasan has a bugette whereby it may lose the content of successive
- * writes to registers that are within two SD-card clock cycles of each other
- * (a clock domain crossing problem). It seems, however, that the data
- * register does not have this problem, which is just as well - otherwise we'd
- * have to nobble the DMA engine too.
- *
- * This should probably be dynamically calculated based on the actual card
- * frequency. However, this is the longest we'll have to wait, and doesn't
- * seem to slow access down too much, so the added complexity doesn't seem
- * worth it for now.
- *
- * 1/MIN_FREQ is (max) time per tick of eMMC clock.
- * 2/MIN_FREQ is time for two ticks.
- * Multiply by 1000000 to get uS per two ticks.
- * *1000000 for uSecs.
- * +1 for hack rounding.
- */
-#define BCM2835_SDHCI_WRITE_DELAY	(((2 * 1000000) / MIN_FREQ) + 1)
-
-struct bcm2835_sdhci {
-	u32 shadow;
+struct bcm2835_sdhci_host {
+	u32 shadow_cmd;
+	u32 shadow_blk;
 };
 
 #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
@@ -80,33 +55,71 @@ static u8 bcm2835_sdhci_readb(struct sdhci_host *host, int reg)
 	return byte;
 }
 
-static void bcm2835_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
+static inline void bcm2835_sdhci_writel(struct sdhci_host *host,
+						u32 val, int reg)
 {
 	writel(val, host->ioaddr + reg);
-
-	udelay(BCM2835_SDHCI_WRITE_DELAY);
 }
 
-
+/*
+ * The Arasan has a bugette whereby it may lose the content of successive
+ * writes to the same register that are within two SD-card clock cycles of
+ * each other (a clock domain crossing problem). The data
+ * register does not have this problem, which is just as well - otherwise we'd
+ * have to nobble the DMA engine too.
+ *
+ * This wouldn't be a problem with the code except that we can only write the
+ * controller with 32-bit writes.  So two different 16-bit registers are
+ * written back to back creates the problem.
+ *
+ * In reality, this only happens when SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT
+ * are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND.
+ * The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so
+ * the work around can be further optimized. We can keep shadow values of
+ * BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued.
+ * Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed
+ * by the TRANSFER+COMMAND in another 32-bit write.
+ */
 static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 {
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
-	struct bcm2835_sdhci *bcm2835_host = pltfm_host->priv;
-	u32 oldval = (reg == SDHCI_COMMAND) ? bcm2835_host->shadow :
-		bcm2835_sdhci_readl(host, reg & ~3);
+	struct bcm2835_sdhci_host *bcm2835_host = pltfm_host->priv;
 	u32 word_shift = REG_OFFSET_IN_BITS(reg);
 	u32 mask = 0xffff << word_shift;
-	u32 newval = (oldval & ~mask) | (val << word_shift);
-
-	if (reg == SDHCI_TRANSFER_MODE)
-		bcm2835_host->shadow = newval;
-	else
+	u32 oldval, newval;
+
+	if (reg == SDHCI_COMMAND) {
+		/* Write the block now as we are issuing a command */
+		if (bcm2835_host->shadow_blk != 0) {
+			bcm2835_sdhci_writel(host, bcm2835_host->shadow_blk,
+				SDHCI_BLOCK_SIZE);
+			bcm2835_host->shadow_blk = 0;
+		}
+		oldval = bcm2835_host->shadow_cmd;
+	} else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
+		/* Block size and count are stored in shadow reg */
+		oldval = bcm2835_host->shadow_blk;
+	} else {
+		/* Read reg, all other registers are not shadowed */
+		oldval = readl(host->ioaddr + (reg & ~3));
+	}
+	newval = (oldval & ~mask) | (val << word_shift);
+
+	if (reg == SDHCI_TRANSFER_MODE) {
+		/* Save the transfer mode until the command is issued */
+		bcm2835_host->shadow_cmd = newval;
+	} else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
+		/* Save the block info until the command is issued */
+		bcm2835_host->shadow_blk = newval;
+	} else {
+		/* Command or other regular 32-bit write */
 		bcm2835_sdhci_writel(host, newval, reg & ~3);
+	}
 }
 
 static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 {
-	u32 oldval = bcm2835_sdhci_readl(host, reg & ~3);
+	u32 oldval = readl(host->ioaddr + (reg & ~3));
 	u32 byte_shift = REG_OFFSET_IN_BITS(reg);
 	u32 mask = 0xff << byte_shift;
 	u32 newval = (oldval & ~mask) | (val << byte_shift);
@@ -114,11 +127,6 @@ static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 	bcm2835_sdhci_writel(host, newval, reg & ~3);
 }
 
-static unsigned int bcm2835_sdhci_get_min_clock(struct sdhci_host *host)
-{
-	return MIN_FREQ;
-}
-
 static const struct sdhci_ops bcm2835_sdhci_ops = {
 	.read_l = bcm2835_sdhci_readl,
 	.read_w = bcm2835_sdhci_readw,
@@ -128,7 +136,6 @@ static const struct sdhci_ops bcm2835_sdhci_ops = {
 	.write_b = bcm2835_sdhci_writeb,
 	.set_clock = sdhci_set_clock,
 	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
-	.get_min_clock = bcm2835_sdhci_get_min_clock,
 	.set_bus_width = sdhci_set_bus_width,
 	.reset = sdhci_reset,
 	.set_uhs_signaling = sdhci_set_uhs_signaling,
@@ -143,7 +150,7 @@ static const struct sdhci_pltfm_data bcm2835_sdhci_pdata = {
 static int bcm2835_sdhci_probe(struct platform_device *pdev)
 {
 	struct sdhci_host *host;
-	struct bcm2835_sdhci *bcm2835_host;
+	struct bcm2835_sdhci_host *bcm2835_host;
 	struct sdhci_pltfm_host *pltfm_host;
 	int ret;
 
-- 
1.7.9.5

[PATCHv2 4/5] mmc: shdci-bcm2835: add verify for 32-bit back-to-back workaround

[Scott Branden]

Add a verify option to driver to print out an error message if a
potential back to back write could cause a clock domain issue.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/mmc/host/Kconfig         |    9 +++++++++
 drivers/mmc/host/sdhci-bcm2835.c |   17 +++++++++++++++++
 2 files changed, 26 insertions(+)

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 1386065..020de98 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -292,6 +292,15 @@ config MMC_SDHCI_BCM2835
 
 	  If unsure, say N.
 
+config MMC_SDHCI_BCM2835_VERIFY_WORKAROUND
+	bool "Verify BCM2835 workaround does not do back to back writes"
+	depends on MMC_SDHCI_BCM2835
+	default y
+	help
+	  This enables code that verifies the bcm2835 workaround.
+	  The verification code checks that back to back writes to the same
+	  register do not occur.
+
 config MMC_MOXART
 	tristate "MOXART SD/MMC Host Controller support"
 	depends on ARCH_MOXART && MMC
diff --git a/drivers/mmc/host/sdhci-bcm2835.c b/drivers/mmc/host/sdhci-bcm2835.c
index f8c450a..11af27f 100644
--- a/drivers/mmc/host/sdhci-bcm2835.c
+++ b/drivers/mmc/host/sdhci-bcm2835.c
@@ -27,6 +27,9 @@
 struct bcm2835_sdhci_host {
 	u32 shadow_cmd;
 	u32 shadow_blk;
+#ifdef CONFIG_MMC_SDHCI_BCM2835_VERIFY_WORKAROUND
+	int previous_reg;
+#endif
 };
 
 #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
@@ -58,6 +61,20 @@ static u8 bcm2835_sdhci_readb(struct sdhci_host *host, int reg)
 static inline void bcm2835_sdhci_writel(struct sdhci_host *host,
 						u32 val, int reg)
 {
+#ifdef CONFIG_MMC_SDHCI_BCM2835_VERIFY_WORKAROUND
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct bcm2835_sdhci_host *bcm2835_host = pltfm_host->priv;
+
+	if (bcm2835_host->previous_reg == reg) {
+		if ((reg != SDHCI_HOST_CONTROL)
+			&& (reg != SDHCI_CLOCK_CONTROL)) {
+			dev_err(mmc_dev(host->mmc),
+			"back-to-back write to 0x%x\n", reg);
+		}
+	}
+	bcm2835_host->previous_reg = reg;
+#endif
+
 	writel(val, host->ioaddr + reg);
 }
 
-- 
1.7.9.5

[PATCHv2 5/5] mmc: sdhci-bcm2835: add sdhci quirk SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12

[Scott Branden]

SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 is missing and needed for this controller.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/mmc/host/sdhci-bcm2835.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci-bcm2835.c b/drivers/mmc/host/sdhci-bcm2835.c
index 11af27f..2a4c10b 100644
--- a/drivers/mmc/host/sdhci-bcm2835.c
+++ b/drivers/mmc/host/sdhci-bcm2835.c
@@ -159,7 +159,8 @@ static const struct sdhci_ops bcm2835_sdhci_ops = {
 };
 
 static const struct sdhci_pltfm_data bcm2835_sdhci_pdata = {
-	.quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
+	.quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 |
+		  SDHCI_QUIRK_BROKEN_CARD_DETECTION |
 		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
 	.ops = &bcm2835_sdhci_ops,
 };
-- 
1.7.9.5

Re: [PATCHv2 4/5] mmc: shdci-bcm2835: add verify for 32-bit back-to-back workaround

[Stephen Warren]

On 10/30/2014 12:36 AM, Scott Branden wrote:
> Add a verify option to driver to print out an error message if a
> potential back to back write could cause a clock domain issue.

> diff --git a/drivers/mmc/host/sdhci-bcm2835.c b/drivers/mmc/host/sdhci-bcm2835.c

>  static inline void bcm2835_sdhci_writel(struct sdhci_host *host,
>  						u32 val, int reg)
>  {
> +#ifdef CONFIG_MMC_SDHCI_BCM2835_VERIFY_WORKAROUND
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct bcm2835_sdhci_host *bcm2835_host = pltfm_host->priv;
> +
> +	if (bcm2835_host->previous_reg == reg) {
> +		if ((reg != SDHCI_HOST_CONTROL)
> +			&& (reg != SDHCI_CLOCK_CONTROL)) {
> +			dev_err(mmc_dev(host->mmc),
> +			"back-to-back write to 0x%x\n", reg);

This fires a *ton* on reg 0x20 and 0x30 on my rev 2 model B with the
patches applied on top of next-20141031. Without the patches applied,
everything works fine. As far as I can tell, SD card accesses no longer
work (or perhaps there's just so much log spew over serial that it takes
more than 1.5 minutes to get to the login prompt).

Re: [PATCHv2 2/5] mmc: sdhci-bcm2835: make shift calculations consistent

[Stephen Warren]

On 10/30/2014 12:36 AM, Scott Branden wrote:
> Make the shift calculations consistent rather than having different
> implementations to calculate the same thing.

> diff --git a/drivers/mmc/host/sdhci-bcm2835.c b/drivers/mmc/host/sdhci-bcm2835.c

> +#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)

This should really be the following so people don't have to memorize
operator precedence:

#define REG_OFFSET_IN_BITS(reg) (((reg) << 3) & 0x18)

(I've been bit by people mis-remembering precedence in very similar code...)

Re: [PATCHv2 3/5] mmc: shdci-bcm2835: add efficient back-to-back write workaround

[Stephen Warren]

On 10/30/2014 12:36 AM, Scott Branden wrote:
> The bcm2835 has clock domain issues when back to back writes to certain
> registers are written.  The existing driver works around this issue with
> udelay.  A more efficient method is to store the 8 and 16 bit writes
> to the registers affected and then write them as 32 bits at the appropriate
> time.

> diff --git a/drivers/mmc/host/sdhci-bcm2835.c b/drivers/mmc/host/sdhci-bcm2835.c

>  static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
>  {
>  	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> -	struct bcm2835_sdhci *bcm2835_host = pltfm_host->priv;
> -	u32 oldval = (reg == SDHCI_COMMAND) ? bcm2835_host->shadow :
> -		bcm2835_sdhci_readl(host, reg & ~3);
> +	struct bcm2835_sdhci_host *bcm2835_host = pltfm_host->priv;

Is that type change for bcm2835_host really correct?

> +	} else {
> +		/* Read reg, all other registers are not shadowed */
> +		oldval = readl(host->ioaddr + (reg & ~3));

Is there any reason to use readl() directly here rather than calling
bcm2835_readl()? ...

>  static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
>  {
> -	u32 oldval = bcm2835_sdhci_readl(host, reg & ~3);
> +	u32 oldval = readl(host->ioaddr + (reg & ~3));

... and here in particular, since this seems like an unrelated change?

>  static int bcm2835_sdhci_probe(struct platform_device *pdev)
>  {
>  	struct sdhci_host *host;
> -	struct bcm2835_sdhci *bcm2835_host;
> +	struct bcm2835_sdhci_host *bcm2835_host;

Is that type change for bcm2835_host really correct?

Re: [PATCHv2 4/5] mmc: shdci-bcm2835: add verify for 32-bit back-to-back workaround

[Stephen Warren]

On 10/30/2014 12:36 AM, Scott Branden wrote:
> Add a verify option to driver to print out an error message if a
> potential back to back write could cause a clock domain issue.

> index f8c450a..11af27f 100644

> +#ifdef CONFIG_MMC_SDHCI_BCM2835_VERIFY_WORKAROUND
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct bcm2835_sdhci_host *bcm2835_host = pltfm_host->priv;
> +
> +	if (bcm2835_host->previous_reg == reg) {
> +		if ((reg != SDHCI_HOST_CONTROL)
> +			&& (reg != SDHCI_CLOCK_CONTROL)) {

The comment in patch 3 says the problem doesn't apply to the data
register. Why does this check for these two registers rather than data?

> +			dev_err(mmc_dev(host->mmc),
> +			"back-to-back write to 0x%x\n", reg);

The continuation line should be indented at least one more level here.

Re: [PATCHv2 5/5] mmc: sdhci-bcm2835: add sdhci quirk SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12

[Stephen Warren]

On 10/30/2014 12:36 AM, Scott Branden wrote:
> SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 is missing and needed for this controller.

This seems fine, although any explanation of why this quirk is needed
would be useful.

Re: [PATCHv2 2/5] mmc: sdhci-bcm2835: make shift calculations consistent

[Scott Branden]

On 14-11-04 08:48 PM, Stephen Warren wrote:
> On 10/30/2014 12:36 AM, Scott Branden wrote:
>> Make the shift calculations consistent rather than having different
>> implementations to calculate the same thing.
>
>> diff --git a/drivers/mmc/host/sdhci-bcm2835.c b/drivers/mmc/host/sdhci-bcm2835.c
>
>> +#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
>
> This should really be the following so people don't have to memorize
> operator precedence:
>
> #define REG_OFFSET_IN_BITS(reg) (((reg) << 3) & 0x18)
>
> (I've been bit by people mis-remembering precedence in very similar code...)
>
Good idea.

Re: [PATCHv2 4/5] mmc: shdci-bcm2835: add verify for 32-bit back-to-back workaround

[Scott Branden]

On 14-11-04 08:44 PM, Stephen Warren wrote:
> On 10/30/2014 12:36 AM, Scott Branden wrote:
>> Add a verify option to driver to print out an error message if a
>> potential back to back write could cause a clock domain issue.
>
>> diff --git a/drivers/mmc/host/sdhci-bcm2835.c b/drivers/mmc/host/sdhci-bcm2835.c
>
>>   static inline void bcm2835_sdhci_writel(struct sdhci_host *host,
>>   						u32 val, int reg)
>>   {
>> +#ifdef CONFIG_MMC_SDHCI_BCM2835_VERIFY_WORKAROUND
>> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>> +	struct bcm2835_sdhci_host *bcm2835_host = pltfm_host->priv;
>> +
>> +	if (bcm2835_host->previous_reg == reg) {
>> +		if ((reg != SDHCI_HOST_CONTROL)
>> +			&& (reg != SDHCI_CLOCK_CONTROL)) {
>> +			dev_err(mmc_dev(host->mmc),
>> +			"back-to-back write to 0x%x\n", reg);
>
> This fires a *ton* on reg 0x20 and 0x30 on my rev 2 model B with the
> patches applied on top of next-20141031. Without the patches applied,
> everything works fine. As far as I can tell, SD card accesses no longer
> work (or perhaps there's just so much log spew over serial that it takes
> more than 1.5 minutes to get to the login prompt).
>
Thanks for testing.  Like I said in the cover message - I've never run 
this on a PI actually.  I've run it on other hardware with the same core 
arasan block having the same clock domain issue.  The registers printed 
out do not have the clock domain issue - I'm still getting more details 
from the silicon designers on this.

Without the verify patch the performance is actually quite good.  See 
tests result from Piotr:

On Fri, Oct 31, 2014 at 05:02:59PM +0000, Scott Branden wrote:
 > Please let me know how this works for you.
 >
Scott,
please ignore my previous mail I made mistake when applying patches.

Results of testing your code on top of 3.18-rc2 with Kingston SDC10/8GB:

* when compiling with CONFIG_MMC_SDHCI_BCM2835_VERIFY_WORKAROUND=y there 
is a
lot of:

sdhci-bcm2835 20300000.sdhci: back-to-back write to 0x30
and
sdhci-bcm2835 20300000.sdhci: back-to-back write to 0x20

* performance w/o patches:
yncraspberrypi:~$ sync; time dd if=/dev/zero of=~/test.tmp bs=500K 
count=1024; sy
1024+0 records in
1024+0 records out
524288000 bytes (524 MB) copied, 787.384 s, 666 kB/s

real    13m7.404s
user    0m0.080s
sys     0m56.300s
pi@raspberrypi:~$ time dd if=~/test.tmp of=/dev/null bs=500K count=1024
1024+0 records in
1024+0 records out
524288000 bytes (524 MB) copied, 34.2115 s, 15.3 MB/s

real    0m34.232s
user    0m0.020s
sys     0m31.190s


* performance w/ patches is great IMHO:
yncraspberrypi:~$ sync; time dd if=/dev/zero of=~/test.tmp bs=500K 
count=1024; sy
1024+0 records in
1024+0 records out
524288000 bytes (524 MB) copied, 45.4886 s, 11.5 MB/s

real    0m45.515s
user    0m0.060s
sys     0m30.050s time dd if=~/test.tmp of=/dev/null bs=500K count=1024
1024+0 records in
1024+0 records out
524288000 bytes (524 MB) copied, 33.6292 s, 15.6 MB/s

real    0m33.649s
user    0m0.020s
sys     0m30.730s

Great work!

Have you got plans to enable DMA for this controller ? sys CPU load is quite
big for above code, my tests with bcm2835-mmc and slave_sg from RaspberryPi
Foundation gives about 15s instead of 31s. It would be great to relive CPU a
little bit.

Best Regards,
Piotr Król

Re: [PATCHv2 3/5] mmc: shdci-bcm2835: add efficient back-to-back write workaround

[Scott Branden]

On 14-11-04 08:57 PM, Stephen Warren wrote:
> On 10/30/2014 12:36 AM, Scott Branden wrote:
>> The bcm2835 has clock domain issues when back to back writes to certain
>> registers are written.  The existing driver works around this issue with
>> udelay.  A more efficient method is to store the 8 and 16 bit writes
>> to the registers affected and then write them as 32 bits at the appropriate
>> time.
>
>> diff --git a/drivers/mmc/host/sdhci-bcm2835.c b/drivers/mmc/host/sdhci-bcm2835.c
>
>>   static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
>>   {
>>   	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>> -	struct bcm2835_sdhci *bcm2835_host = pltfm_host->priv;
>> -	u32 oldval = (reg == SDHCI_COMMAND) ? bcm2835_host->shadow :
>> -		bcm2835_sdhci_readl(host, reg & ~3);
>> +	struct bcm2835_sdhci_host *bcm2835_host = pltfm_host->priv;
>
> Is that type change for bcm2835_host really correct?
Yes - at the top of the patch the structure has been expanded and named 
appropriately.

-struct bcm2835_sdhci {
-	u32 shadow;
+struct bcm2835_sdhci_host {
+	u32 shadow_cmd;
+	u32 shadow_blk;
  };
>
>> +	} else {
>> +		/* Read reg, all other registers are not shadowed */
>> +		oldval = readl(host->ioaddr + (reg & ~3));
>
> Is there any reason to use readl() directly here rather than calling
> bcm2835_readl()? ...
Yes, bcm2835_readl does not need to be called in read-modify-write and 
shadow register situations and just adds overhead.  All that needs to be 
called is readl.  bcm2835_readl has some existing ugly code in it to 
modify the capabilities register on a read function.  This info never 
needs to be for write as you can't overwrite the capabilities register. 
  I hope to get rid of the capabilities hack in a future patch as this 
should never have been acceptable in upstreamed code to begin with.  The 
capabilities override should have been passed in through a device tree 
entry.
>
>>   static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
>>   {
>> -	u32 oldval = bcm2835_sdhci_readl(host, reg & ~3);
>> +	u32 oldval = readl(host->ioaddr + (reg & ~3));
>
> ... and here in particular, since this seems like an unrelated change?
Same situation with bcm2835_readl above.  No need to call in 
read-modify-write situations.
>
>>   static int bcm2835_sdhci_probe(struct platform_device *pdev)
>>   {
>>   	struct sdhci_host *host;
>> -	struct bcm2835_sdhci *bcm2835_host;
>> +	struct bcm2835_sdhci_host *bcm2835_host;
>
> Is that type change for bcm2835_host really correct?
>
yes - structure renamed above

Re: [PATCHv2 4/5] mmc: shdci-bcm2835: add verify for 32-bit back-to-back workaround

[Scott Branden]

On 14-11-04 08:59 PM, Stephen Warren wrote:
> On 10/30/2014 12:36 AM, Scott Branden wrote:
>> Add a verify option to driver to print out an error message if a
>> potential back to back write could cause a clock domain issue.
>
>> index f8c450a..11af27f 100644
>
>> +#ifdef CONFIG_MMC_SDHCI_BCM2835_VERIFY_WORKAROUND
>> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>> +	struct bcm2835_sdhci_host *bcm2835_host = pltfm_host->priv;
>> +
>> +	if (bcm2835_host->previous_reg == reg) {
>> +		if ((reg != SDHCI_HOST_CONTROL)
>> +			&& (reg != SDHCI_CLOCK_CONTROL)) {
>
> The comment in patch 3 says the problem doesn't apply to the data
> register. Why does this check for these two registers rather than data?
This Verify workaround patch still a work in progress.  I'm still 
getting more info from the silicon designers on the back-to-back 
register writes that are affect.  The spew of 0x20 or 0x28 or 0x2c 
register writes are all ok locations that don't need to be worked 
around.  This patch needs to be corrected with the proper register rules 
still.
>
>> +			dev_err(mmc_dev(host->mmc),
>> +			"back-to-back write to 0x%x\n", reg);
>
> The continuation line should be indented at least one more level here.
>

Re: [PATCHv2 5/5] mmc: sdhci-bcm2835: add sdhci quirk SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12

[Scott Branden]

On 14-11-04 09:00 PM, Stephen Warren wrote:
> On 10/30/2014 12:36 AM, Scott Branden wrote:
>> SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 is missing and needed for this controller.
>
> This seems fine, although any explanation of why this quirk is needed
> would be useful.
>
I don't know who to talk to at Arasan about this.  Will try hunting 
around a little for more info as to why this is needed to have eMMC and 
SD work properly through our internal testing on other non-2835 chipset 
that shares the same SDHCI controller as 2835.

Re: [PATCHv2 3/5] mmc: shdci-bcm2835: add efficient back-to-back write workaround

[Stephen Warren]

On 11/04/2014 11:55 PM, Scott Branden wrote:
> On 14-11-04 08:57 PM, Stephen Warren wrote:
>> On 10/30/2014 12:36 AM, Scott Branden wrote:
>>> The bcm2835 has clock domain issues when back to back writes to certain
>>> registers are written.  The existing driver works around this issue with
>>> udelay.  A more efficient method is to store the 8 and 16 bit writes
>>> to the registers affected and then write them as 32 bits at the
>>> appropriate
>>> time.
>>
>>> diff --git a/drivers/mmc/host/sdhci-bcm2835.c
>>> b/drivers/mmc/host/sdhci-bcm2835.c
>>
>>>   static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val,
>>> int reg)
>>>   {
>>>       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>>> -    struct bcm2835_sdhci *bcm2835_host = pltfm_host->priv;
>>> -    u32 oldval = (reg == SDHCI_COMMAND) ? bcm2835_host->shadow :
>>> -        bcm2835_sdhci_readl(host, reg & ~3);
>>> +    struct bcm2835_sdhci_host *bcm2835_host = pltfm_host->priv;
>>
>> Is that type change for bcm2835_host really correct?
>
> Yes - at the top of the patch the structure has been expanded and named
> appropriately.
> 
> -struct bcm2835_sdhci {
> -    u32 shadow;
> +struct bcm2835_sdhci_host {
> +    u32 shadow_cmd;
> +    u32 shadow_blk;
>  };

Ah yes, sorry for missing that.

>>> +    } else {
>>> +        /* Read reg, all other registers are not shadowed */
>>> +        oldval = readl(host->ioaddr + (reg & ~3));
>>
>> Is there any reason to use readl() directly here rather than calling
>> bcm2835_readl()? ...
>
> Yes, bcm2835_readl does not need to be called in read-modify-write and
> shadow register situations and just adds overhead.  All that needs to be
> called is readl.  bcm2835_readl has some existing ugly code in it to
> modify the capabilities register on a read function.  This info never
> needs to be for write as you can't overwrite the capabilities register.

To be honest, it seems better to do all the read/write through
consistent functions. One advantage of bcm2835_readl() is that it
consistently adds on the base address internally so you don't have to
write it out every time manually. Still, the code ought to work fine
after this change, so I guess it's OK.

> I hope to get rid of the capabilities hack in a future patch as this
> should never have been acceptable in upstreamed code to begin with.  The
> capabilities override should have been passed in through a device tree
> entry.

It's a pretty common technique with precedent. I certainly don't agree
that it should be configured by DT. Arguably, DT makes sense to describe
board-to-board variations, but there's almost zero point putting data
into DT that is SoC description rather than board description; just put
it into the driver to avoid continually parsing the same data over and
over from DT just to get back to the same data that could have been
encoded into the driver. If the data varies between similar controllers,
an of_match table can easily be used to parameterize it based on
compatible value.

Re: [PATCHv2 5/5] mmc: sdhci-bcm2835: add sdhci quirk SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12

[Stephen Warren]

On 11/05/2014 12:02 AM, Scott Branden wrote:
> On 14-11-04 09:00 PM, Stephen Warren wrote:
>> On 10/30/2014 12:36 AM, Scott Branden wrote:
>>> SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 is missing and needed for this
>>> controller.
>>
>> This seems fine, although any explanation of why this quirk is needed
>> would be useful.
>>
> I don't know who to talk to at Arasan about this.  Will try hunting
> around a little for more info as to why this is needed to have eMMC and
> SD work properly through our internal testing on other non-2835 chipset
> that shares the same SDHCI controller as 2835.

I thought I heard that this wasn't a bug in the controller itself, but
rather an integration issue between the IP core and the register bus
it's attached to. Consequently, it may be SoC-specific or at least have
SoC-specific variations?

Re: [PATCHv2 4/5] mmc: shdci-bcm2835: add verify for 32-bit back-to-back workaround

[Stephen Warren]

On 11/05/2014 12:00 AM, Scott Branden wrote:
> On 14-11-04 08:59 PM, Stephen Warren wrote:
>> On 10/30/2014 12:36 AM, Scott Branden wrote:
>>> Add a verify option to driver to print out an error message if a
>>> potential back to back write could cause a clock domain issue.
>>
>>> index f8c450a..11af27f 100644
>>
>>> +#ifdef CONFIG_MMC_SDHCI_BCM2835_VERIFY_WORKAROUND
>>> +    struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>>> +    struct bcm2835_sdhci_host *bcm2835_host = pltfm_host->priv;
>>> +
>>> +    if (bcm2835_host->previous_reg == reg) {
>>> +        if ((reg != SDHCI_HOST_CONTROL)
>>> +            && (reg != SDHCI_CLOCK_CONTROL)) {
>>
>> The comment in patch 3 says the problem doesn't apply to the data
>> register. Why does this check for these two registers rather than data?
> This Verify workaround patch still a work in progress.  I'm still
> getting more info from the silicon designers on the back-to-back
> register writes that are affect.  The spew of 0x20 or 0x28 or 0x2c
> register writes are all ok locations that don't need to be worked
> around.  This patch needs to be corrected with the proper register rules
> still.

FYI, I applied the series except for this patch, and everything
/appeared/ to work OK for a brief test (boot, log in, reboot). Still,
I'll hold off my Tested-by/acked-by until the comment in patch 3 and the
register list above match, and there's no log spew with everything applied.

Re: [PATCHv2 3/5] mmc: shdci-bcm2835: add efficient back-to-back write workaround

[Scott Branden]

On 14-11-05 08:48 PM, Stephen Warren wrote:
> On 11/04/2014 11:55 PM, Scott Branden wrote:
>> On 14-11-04 08:57 PM, Stephen Warren wrote:
>>> On 10/30/2014 12:36 AM, Scott Branden wrote:
>>>> The bcm2835 has clock domain issues when back to back writes to certain
>>>> registers are written.  The existing driver works around this issue with
>>>> udelay.  A more efficient method is to store the 8 and 16 bit writes
>>>> to the registers affected and then write them as 32 bits at the
>>>> appropriate
>>>> time.
>>>
>>>> diff --git a/drivers/mmc/host/sdhci-bcm2835.c
>>>> b/drivers/mmc/host/sdhci-bcm2835.c
>>>
>>>>    static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val,
>>>> int reg)
>>>>    {
>>>>        struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>>>> -    struct bcm2835_sdhci *bcm2835_host = pltfm_host->priv;
>>>> -    u32 oldval = (reg == SDHCI_COMMAND) ? bcm2835_host->shadow :
>>>> -        bcm2835_sdhci_readl(host, reg & ~3);
>>>> +    struct bcm2835_sdhci_host *bcm2835_host = pltfm_host->priv;
>>>
>>> Is that type change for bcm2835_host really correct?
>>
>> Yes - at the top of the patch the structure has been expanded and named
>> appropriately.
>>
>> -struct bcm2835_sdhci {
>> -    u32 shadow;
>> +struct bcm2835_sdhci_host {
>> +    u32 shadow_cmd;
>> +    u32 shadow_blk;
>>   };
>
> Ah yes, sorry for missing that.
>
>>>> +    } else {
>>>> +        /* Read reg, all other registers are not shadowed */
>>>> +        oldval = readl(host->ioaddr + (reg & ~3));
>>>
>>> Is there any reason to use readl() directly here rather than calling
>>> bcm2835_readl()? ...
>>
>> Yes, bcm2835_readl does not need to be called in read-modify-write and
>> shadow register situations and just adds overhead.  All that needs to be
>> called is readl.  bcm2835_readl has some existing ugly code in it to
>> modify the capabilities register on a read function.  This info never
>> needs to be for write as you can't overwrite the capabilities register.
>
> To be honest, it seems better to do all the read/write through
> consistent functions. One advantage of bcm2835_readl() is that it
> consistently adds on the base address internally so you don't have to
> write it out every time manually. Still, the code ought to work fine
> after this change, so I guess it's OK.
>
>> I hope to get rid of the capabilities hack in a future patch as this
>> should never have been acceptable in upstreamed code to begin with.  The
>> capabilities override should have been passed in through a device tree
>> entry.
>
> It's a pretty common technique with precedent. I certainly don't agree
> that it should be configured by DT. Arguably, DT makes sense to describe
> board-to-board variations, but there's almost zero point putting data
> into DT that is SoC description rather than board description; just put
> it into the driver to avoid continually parsing the same data over and
> over from DT just to get back to the same data that could have been
> encoded into the driver. If the data varies between similar controllers,
> an of_match table can easily be used to parameterize it based on
> compatible value.
There is work to be done here or I will be unable to use this driver in 
our chipsets.  Perhaps it will be easier having another driver 
actually... as the DMA seems quite different on RPI.
>

Re: [PATCHv2 5/5] mmc: sdhci-bcm2835: add sdhci quirk SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12

[Scott Branden]

On 14-11-05 08:50 PM, Stephen Warren wrote:
> On 11/05/2014 12:02 AM, Scott Branden wrote:
>> On 14-11-04 09:00 PM, Stephen Warren wrote:
>>> On 10/30/2014 12:36 AM, Scott Branden wrote:
>>>> SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 is missing and needed for this
>>>> controller.
>>>
>>> This seems fine, although any explanation of why this quirk is needed
>>> would be useful.
>>>
>> I don't know who to talk to at Arasan about this.  Will try hunting
>> around a little for more info as to why this is needed to have eMMC and
>> SD work properly through our internal testing on other non-2835 chipset
>> that shares the same SDHCI controller as 2835.
>
> I thought I heard that this wasn't a bug in the controller itself, but
> rather an integration issue between the IP core and the register bus
> it's attached to. Consequently, it may be SoC-specific or at least have
> SoC-specific variations?
Yes, this patch is to fix a different bug (in the IP) rather than the 
clock domain integration issue.
>

Re: [PATCHv2 4/5] mmc: shdci-bcm2835: add verify for 32-bit back-to-back workaround

[Scott Branden]

On 14-11-05 09:01 PM, Stephen Warren wrote:
> On 11/05/2014 12:00 AM, Scott Branden wrote:
>> On 14-11-04 08:59 PM, Stephen Warren wrote:
>>> On 10/30/2014 12:36 AM, Scott Branden wrote:
>>>> Add a verify option to driver to print out an error message if a
>>>> potential back to back write could cause a clock domain issue.
>>>
>>>> index f8c450a..11af27f 100644
>>>
>>>> +#ifdef CONFIG_MMC_SDHCI_BCM2835_VERIFY_WORKAROUND
>>>> +    struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>>>> +    struct bcm2835_sdhci_host *bcm2835_host = pltfm_host->priv;
>>>> +
>>>> +    if (bcm2835_host->previous_reg == reg) {
>>>> +        if ((reg != SDHCI_HOST_CONTROL)
>>>> +            && (reg != SDHCI_CLOCK_CONTROL)) {
>>>
>>> The comment in patch 3 says the problem doesn't apply to the data
>>> register. Why does this check for these two registers rather than data?
>> This Verify workaround patch still a work in progress.  I'm still
>> getting more info from the silicon designers on the back-to-back
>> register writes that are affect.  The spew of 0x20 or 0x28 or 0x2c
>> register writes are all ok locations that don't need to be worked
>> around.  This patch needs to be corrected with the proper register rules
>> still.
Thanks for testing.  Yes, I have work to do on the verify patch above still.
>
> FYI, I applied the series except for this patch, and everything
> /appeared/ to work OK for a brief test (boot, log in, reboot). Still,
> I'll hold off my Tested-by/acked-by until the comment in patch 3 and the
> register list above match, and there's no log spew with everything applied.
>

Re: [PATCH v8 4/8] ARM: dts: Enable Broadcom Cygnus SoC

[Olof Johansson]

Hi,

A bunch of small comments below, should be quick to fix.

On Tue, Oct 28, 2014 at 12:53 PM, Scott Branden <sbranden@broadcom.com> wrote:
> DT files to enable cygnus consisting on reference designs
> and cygnus core configuration.
>
> Reviewed-by: Ray Jui <rjui@broadcom.com>
> Reviewed-by: Arun Parameswaran <aparames@broadcom.com>
> Tested-by: Jonathan Richardson <jonathar@broadcom.com>
> Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
> Signed-off-by: Scott Branden <sbranden@broadcom.com>
> ---
>  arch/arm/boot/dts/Makefile              |    4 ++
>  arch/arm/boot/dts/bcm-cygnus-clock.dtsi |   73 ++++++++++++++++++++++
>  arch/arm/boot/dts/bcm-cygnus.dtsi       |  100 +++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/bcm911360_entphn.dts  |   32 ++++++++++
>  arch/arm/boot/dts/bcm911360k.dts        |   32 ++++++++++
>  arch/arm/boot/dts/bcm958300k.dts        |   32 ++++++++++
>  6 files changed, 273 insertions(+)
>  create mode 100644 arch/arm/boot/dts/bcm-cygnus-clock.dtsi
>  create mode 100644 arch/arm/boot/dts/bcm-cygnus.dtsi
>  create mode 100644 arch/arm/boot/dts/bcm911360_entphn.dts
>  create mode 100644 arch/arm/boot/dts/bcm911360k.dts
>  create mode 100644 arch/arm/boot/dts/bcm958300k.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 38c89ca..4b3a590 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -54,6 +54,10 @@ dtb-$(CONFIG_ARCH_AT91)      += at91-sama5d4ek.dtb
>  dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
>  dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
>  dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
> +dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
> +       bcm911360_entphn.dtb \
> +       bcm911360k.dtb \
> +       bcm958300k.dtb
>  dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
>  dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb
>  dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \

Please add new entries in alphabetical/alphanumerical order. Also,
first entry is commonly added on the first line


> diff --git a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
> new file mode 100644
> index 0000000..d06172b
> --- /dev/null
> +++ b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
> @@ -0,0 +1,73 @@
> +/*
> + * Copyright 2014 Broadcom Corporation.  All rights reserved.
> + *
> + * Unless you and Broadcom execute a separate written software license
> + * agreement governing use of this software, this software is licensed to you
> + * under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.

We ask for new DT contents to be added with dual BSD/GPL license, to
allow for reuse of the DT data structures in other projects as well.
There's currently a lot of activity going on relicensing the current
files so I recommend sorting it out before they are added if you can.

> + */
> +
> +clocks {
> +       #address-cells = <1>;
> +       #size-cells = <1>;
> +       ranges;
> +
> +       osc: oscillator {
> +               compatible = "fixed-clock";
> +               #clock-cells = <1>;
> +               clock-frequency = <25000000>;
> +       };
> +
> +       apb_clk: apb_clk {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <1000000000>;
> +       };
> +
> +       periph_clk: periph_clk {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <500000000>;
> +       };
> +
> +       sdio_clk: lcpll_ch2 {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <200000000>;
> +       };
> +
> +       axi81_clk: axi81_clk {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <100000000>;
> +       };
> +
> +       keypad_clk: keypad_clk {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <31806>;
> +       };
> +
> +       adc_clk: adc_clk {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <1562500>;
> +       };
> +
> +       pwm_clk: pwm_clk {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <1000000>;
> +       };
> +
> +       lcd_clk: mipipll_ch1 {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <100000000>;
> +       };
> +};
> diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
> new file mode 100644
> index 0000000..9c650ab
> --- /dev/null
> +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
> @@ -0,0 +1,100 @@
> +/*
> + * Copyright 2014 Broadcom Corporation.  All rights reserved.
> + *
> + * Unless you and Broadcom execute a separate written software license
> + * agreement governing use of this software, this software is licensed to you
> + * under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +#include "skeleton.dtsi"
> +
> +/ {
> +       compatible = "brcm,cygnus";
> +       model = "Broadcom Cygnus SoC";
> +       interrupt-parent = <&gic>;
> +
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               cpu@0 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a9";
> +                       next-level-cache = <&L2>;
> +                       reg = <0x0>;
> +               };
> +       };
> +
> +       /include/ "bcm-cygnus-clock.dtsi"
> +
> +       amba {
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               compatible = "arm,amba-bus", "simple-bus";
> +               interrupt-parent = <&gic>;
> +               ranges;
> +
> +               wdt@18009000 {
> +                        compatible = "arm,sp805" , "arm,primecell";
> +                        reg = <0x18009000 0x1000>;
> +                        interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
> +                        clocks = <&axi81_clk>;
> +                        clock-names = "apb_pclk";
> +               };
> +       };
> +
> +       uart3: serial@18023000 {
> +               compatible = "snps,dw-apb-uart";
> +               reg = <0x18023000 0x100>;
> +               reg-shift = <2>;
> +               reg-io-width = <4>;
> +               interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
> +               clock-frequency = <100000000>;
> +               clocks = <&axi81_clk>;
> +               status = "okay";

It is common to leave these disabled in the SoC/common dtsi, and
enable them in the per-board dts files, since different boards might
not use all peripherals, etc.

It seems like all your boards currently use both uarts, but if it
changes in the future please consider switching over. It might be
worth doing so now to avoid churn later on. That also allows you to
define all the uards (I'm going to guess that there's a total of at
least 4 on this system :).

> +       };
> +
> +       uart0: serial@18020000 {

These are also out of order, uart3 is before uart0 (and the registers
are in reverse order).

We normally recommend that you add entries sorted by reg/unit address
-- that way there's less risk of conflict due to add/add compared to
if people just append new entries at the end of the file.

> +               compatible = "snps,dw-apb-uart";
> +               reg = <0x18020000 0x100>;
> +               reg-shift = <2>;
> +               reg-io-width = <4>;
> +               interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> +               clocks = <&axi81_clk>;
> +               clock-frequency = <100000000>;
> +               status = "okay";
> +       };
> +
> +       gic: interrupt-controller@19021000 {
> +               compatible = "arm,cortex-a9-gic";
> +               #interrupt-cells = <3>;
> +               #address-cells = <0>;
> +               interrupt-controller;
> +               reg = <0x19021000 0x1000>,
> +                     <0x19020100 0x100>;
> +       };
> +
> +       L2: l2-cache {

l2-cache@19022000

> +               compatible = "arm,pl310-cache";
> +               reg = <0x19022000 0x1000>;
> +               cache-unified;
> +               cache-level = <2>;
> +       };
> +
> +       timer@19020200 {
> +               compatible = "arm,cortex-a9-global-timer";
> +               reg = <0x19020200 0x100>;
> +               interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
> +               clocks = <&periph_clk>;
> +       };
> +
> +};
> diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts
> new file mode 100644
> index 0000000..9de5e87
> --- /dev/null
> +++ b/arch/arm/boot/dts/bcm911360_entphn.dts
> @@ -0,0 +1,32 @@
> +/*
> + * Copyright 2014 Broadcom Corporation.  All rights reserved.
> + *
> + * Unless you and Broadcom execute a separate written software license
> + * agreement governing use of this software, this software is licensed to you
> + * under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +/dts-v1/;
> +
> +#include "bcm-cygnus.dtsi"
> +
> +/ {
> +       model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)";
> +       compatible = "brcm,bcm11360", "brcm,cygnus";
> +
> +       aliases {
> +               serial0 = &uart3;
> +               serial1 = &uart0;
> +       };
> +
> +       chosen {
> +               stdout-path = &uart3;
> +               bootargs = "console=ttyS0,115200";
> +       };
> +};
> diff --git a/arch/arm/boot/dts/bcm911360k.dts b/arch/arm/boot/dts/bcm911360k.dts
> new file mode 100644
> index 0000000..dd4f102
> --- /dev/null
> +++ b/arch/arm/boot/dts/bcm911360k.dts
> @@ -0,0 +1,32 @@
> +/*
> + * Copyright 2014 Broadcom Corporation.  All rights reserved.
> + *
> + * Unless you and Broadcom execute a separate written software license
> + * agreement governing use of this software, this software is licensed to you
> + * under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +/dts-v1/;
> +
> +#include "bcm-cygnus.dtsi"
> +
> +/ {
> +       model = "Cygnus SVK (BCM911360K)";
> +       compatible = "brcm,bcm11360", "brcm,cygnus";
> +
> +       aliases {
> +               serial0 = &uart3;
> +               serial1 = &uart0;
> +       };
> +
> +       chosen {
> +               stdout-path = &uart3;
> +               bootargs = "console=ttyS0,115200";
> +       };
> +};
> diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts
> new file mode 100644
> index 0000000..f8b9625
> --- /dev/null
> +++ b/arch/arm/boot/dts/bcm958300k.dts
> @@ -0,0 +1,32 @@
> +/*
> + * Copyright 2014 Broadcom Corporation.  All rights reserved.
> + *
> + * Unless you and Broadcom execute a separate written software license
> + * agreement governing use of this software, this software is licensed to you
> + * under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +/dts-v1/;
> +
> +#include "bcm-cygnus.dtsi"
> +
> +/ {
> +       model = "Cygnus SVK (BCM958300K)";
> +       compatible = "brcm,bcm58300", "brcm,cygnus";
> +
> +       aliases {
> +               serial0 = &uart3;
> +               serial1 = &uart0;
> +       };
> +
> +       chosen {
> +               stdout-path = &uart3;
> +               bootargs = "console=ttyS0,115200";
> +       };
> +};
> --
> 1.7.9.5
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v8 4/8] ARM: dts: Enable Broadcom Cygnus SoC

[Scott Branden]

On 14-11-08 04:22 PM, Olof Johansson wrote:
> Hi,
>
> A bunch of small comments below, should be quick to fix.
>
> On Tue, Oct 28, 2014 at 12:53 PM, Scott Branden <sbranden@broadcom.com> wrote:
>> DT files to enable cygnus consisting on reference designs
>> and cygnus core configuration.
>>
>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>> Reviewed-by: Arun Parameswaran <aparames@broadcom.com>
>> Tested-by: Jonathan Richardson <jonathar@broadcom.com>
>> Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>> ---
>>   arch/arm/boot/dts/Makefile              |    4 ++
>>   arch/arm/boot/dts/bcm-cygnus-clock.dtsi |   73 ++++++++++++++++++++++
>>   arch/arm/boot/dts/bcm-cygnus.dtsi       |  100 +++++++++++++++++++++++++++++++
>>   arch/arm/boot/dts/bcm911360_entphn.dts  |   32 ++++++++++
>>   arch/arm/boot/dts/bcm911360k.dts        |   32 ++++++++++
>>   arch/arm/boot/dts/bcm958300k.dts        |   32 ++++++++++
>>   6 files changed, 273 insertions(+)
>>   create mode 100644 arch/arm/boot/dts/bcm-cygnus-clock.dtsi
>>   create mode 100644 arch/arm/boot/dts/bcm-cygnus.dtsi
>>   create mode 100644 arch/arm/boot/dts/bcm911360_entphn.dts
>>   create mode 100644 arch/arm/boot/dts/bcm911360k.dts
>>   create mode 100644 arch/arm/boot/dts/bcm958300k.dts
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index 38c89ca..4b3a590 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -54,6 +54,10 @@ dtb-$(CONFIG_ARCH_AT91)      += at91-sama5d4ek.dtb
>>   dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
>>   dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
>>   dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
>> +dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
>> +       bcm911360_entphn.dtb \
>> +       bcm911360k.dtb \
>> +       bcm958300k.dtb
>>   dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
>>   dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb
>>   dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
>
> Please add new entries in alphabetical/alphanumerical order. Also,
> first entry is commonly added on the first line
>
>
>> diff --git a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
>> new file mode 100644
>> index 0000000..d06172b
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
>> @@ -0,0 +1,73 @@
>> +/*
>> + * Copyright 2014 Broadcom Corporation.  All rights reserved.
>> + *
>> + * Unless you and Broadcom execute a separate written software license
>> + * agreement governing use of this software, this software is licensed to you
>> + * under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation version 2.
>> + *
>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> + * kind, whether express or implied; without even the implied warranty
>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>
> We ask for new DT contents to be added with dual BSD/GPL license, to
> allow for reuse of the DT data structures in other projects as well.
> There's currently a lot of activity going on relicensing the current
> files so I recommend sorting it out before they are added if you can.

This may take more time than you think.  I am going to have to go 
through legal to get such a license created.  Also, why would you need 
dual license?  If it is BSD that should serve both purposes?
>
>> + */
>> +
>> +clocks {
>> +       #address-cells = <1>;
>> +       #size-cells = <1>;
>> +       ranges;
>> +
>> +       osc: oscillator {
>> +               compatible = "fixed-clock";
>> +               #clock-cells = <1>;
>> +               clock-frequency = <25000000>;
>> +       };
>> +
>> +       apb_clk: apb_clk {
>> +               compatible = "fixed-clock";
>> +               #clock-cells = <0>;
>> +               clock-frequency = <1000000000>;
>> +       };
>> +
>> +       periph_clk: periph_clk {
>> +               compatible = "fixed-clock";
>> +               #clock-cells = <0>;
>> +               clock-frequency = <500000000>;
>> +       };
>> +
>> +       sdio_clk: lcpll_ch2 {
>> +               compatible = "fixed-clock";
>> +               #clock-cells = <0>;
>> +               clock-frequency = <200000000>;
>> +       };
>> +
>> +       axi81_clk: axi81_clk {
>> +               compatible = "fixed-clock";
>> +               #clock-cells = <0>;
>> +               clock-frequency = <100000000>;
>> +       };
>> +
>> +       keypad_clk: keypad_clk {
>> +               compatible = "fixed-clock";
>> +               #clock-cells = <0>;
>> +               clock-frequency = <31806>;
>> +       };
>> +
>> +       adc_clk: adc_clk {
>> +               compatible = "fixed-clock";
>> +               #clock-cells = <0>;
>> +               clock-frequency = <1562500>;
>> +       };
>> +
>> +       pwm_clk: pwm_clk {
>> +               compatible = "fixed-clock";
>> +               #clock-cells = <0>;
>> +               clock-frequency = <1000000>;
>> +       };
>> +
>> +       lcd_clk: mipipll_ch1 {
>> +               compatible = "fixed-clock";
>> +               #clock-cells = <0>;
>> +               clock-frequency = <100000000>;
>> +       };
>> +};
>> diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
>> new file mode 100644
>> index 0000000..9c650ab
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
>> @@ -0,0 +1,100 @@
>> +/*
>> + * Copyright 2014 Broadcom Corporation.  All rights reserved.
>> + *
>> + * Unless you and Broadcom execute a separate written software license
>> + * agreement governing use of this software, this software is licensed to you
>> + * under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation version 2.
>> + *
>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> + * kind, whether express or implied; without even the implied warranty
>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +
>> +#include "skeleton.dtsi"
>> +
>> +/ {
>> +       compatible = "brcm,cygnus";
>> +       model = "Broadcom Cygnus SoC";
>> +       interrupt-parent = <&gic>;
>> +
>> +       cpus {
>> +               #address-cells = <1>;
>> +               #size-cells = <0>;
>> +
>> +               cpu@0 {
>> +                       device_type = "cpu";
>> +                       compatible = "arm,cortex-a9";
>> +                       next-level-cache = <&L2>;
>> +                       reg = <0x0>;
>> +               };
>> +       };
>> +
>> +       /include/ "bcm-cygnus-clock.dtsi"
>> +
>> +       amba {
>> +               #address-cells = <1>;
>> +               #size-cells = <1>;
>> +               compatible = "arm,amba-bus", "simple-bus";
>> +               interrupt-parent = <&gic>;
>> +               ranges;
>> +
>> +               wdt@18009000 {
>> +                        compatible = "arm,sp805" , "arm,primecell";
>> +                        reg = <0x18009000 0x1000>;
>> +                        interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
>> +                        clocks = <&axi81_clk>;
>> +                        clock-names = "apb_pclk";
>> +               };
>> +       };
>> +
>> +       uart3: serial@18023000 {
>> +               compatible = "snps,dw-apb-uart";
>> +               reg = <0x18023000 0x100>;
>> +               reg-shift = <2>;
>> +               reg-io-width = <4>;
>> +               interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
>> +               clock-frequency = <100000000>;
>> +               clocks = <&axi81_clk>;
>> +               status = "okay";
>
> It is common to leave these disabled in the SoC/common dtsi, and
> enable them in the per-board dts files, since different boards might
> not use all peripherals, etc.
>
> It seems like all your boards currently use both uarts, but if it
> changes in the future please consider switching over. It might be
> worth doing so now to avoid churn later on. That also allows you to
> define all the uards (I'm going to guess that there's a total of at
> least 4 on this system :).
>
>> +       };
>> +
>> +       uart0: serial@18020000 {
>
> These are also out of order, uart3 is before uart0 (and the registers
> are in reverse order).
>
> We normally recommend that you add entries sorted by reg/unit address
> -- that way there's less risk of conflict due to add/add compared to
> if people just append new entries at the end of the file.
>
>> +               compatible = "snps,dw-apb-uart";
>> +               reg = <0x18020000 0x100>;
>> +               reg-shift = <2>;
>> +               reg-io-width = <4>;
>> +               interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
>> +               clocks = <&axi81_clk>;
>> +               clock-frequency = <100000000>;
>> +               status = "okay";
>> +       };
>> +
>> +       gic: interrupt-controller@19021000 {
>> +               compatible = "arm,cortex-a9-gic";
>> +               #interrupt-cells = <3>;
>> +               #address-cells = <0>;
>> +               interrupt-controller;
>> +               reg = <0x19021000 0x1000>,
>> +                     <0x19020100 0x100>;
>> +       };
>> +
>> +       L2: l2-cache {
>
> l2-cache@19022000
>
>> +               compatible = "arm,pl310-cache";
>> +               reg = <0x19022000 0x1000>;
>> +               cache-unified;
>> +               cache-level = <2>;
>> +       };
>> +
>> +       timer@19020200 {
>> +               compatible = "arm,cortex-a9-global-timer";
>> +               reg = <0x19020200 0x100>;
>> +               interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
>> +               clocks = <&periph_clk>;
>> +       };
>> +
>> +};
>> diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts
>> new file mode 100644
>> index 0000000..9de5e87
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/bcm911360_entphn.dts
>> @@ -0,0 +1,32 @@
>> +/*
>> + * Copyright 2014 Broadcom Corporation.  All rights reserved.
>> + *
>> + * Unless you and Broadcom execute a separate written software license
>> + * agreement governing use of this software, this software is licensed to you
>> + * under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation version 2.
>> + *
>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> + * kind, whether express or implied; without even the implied warranty
>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "bcm-cygnus.dtsi"
>> +
>> +/ {
>> +       model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)";
>> +       compatible = "brcm,bcm11360", "brcm,cygnus";
>> +
>> +       aliases {
>> +               serial0 = &uart3;
>> +               serial1 = &uart0;
>> +       };
>> +
>> +       chosen {
>> +               stdout-path = &uart3;
>> +               bootargs = "console=ttyS0,115200";
>> +       };
>> +};
>> diff --git a/arch/arm/boot/dts/bcm911360k.dts b/arch/arm/boot/dts/bcm911360k.dts
>> new file mode 100644
>> index 0000000..dd4f102
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/bcm911360k.dts
>> @@ -0,0 +1,32 @@
>> +/*
>> + * Copyright 2014 Broadcom Corporation.  All rights reserved.
>> + *
>> + * Unless you and Broadcom execute a separate written software license
>> + * agreement governing use of this software, this software is licensed to you
>> + * under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation version 2.
>> + *
>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> + * kind, whether express or implied; without even the implied warranty
>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "bcm-cygnus.dtsi"
>> +
>> +/ {
>> +       model = "Cygnus SVK (BCM911360K)";
>> +       compatible = "brcm,bcm11360", "brcm,cygnus";
>> +
>> +       aliases {
>> +               serial0 = &uart3;
>> +               serial1 = &uart0;
>> +       };
>> +
>> +       chosen {
>> +               stdout-path = &uart3;
>> +               bootargs = "console=ttyS0,115200";
>> +       };
>> +};
>> diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts
>> new file mode 100644
>> index 0000000..f8b9625
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/bcm958300k.dts
>> @@ -0,0 +1,32 @@
>> +/*
>> + * Copyright 2014 Broadcom Corporation.  All rights reserved.
>> + *
>> + * Unless you and Broadcom execute a separate written software license
>> + * agreement governing use of this software, this software is licensed to you
>> + * under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation version 2.
>> + *
>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> + * kind, whether express or implied; without even the implied warranty
>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "bcm-cygnus.dtsi"
>> +
>> +/ {
>> +       model = "Cygnus SVK (BCM958300K)";
>> +       compatible = "brcm,bcm58300", "brcm,cygnus";
>> +
>> +       aliases {
>> +               serial0 = &uart3;
>> +               serial1 = &uart0;
>> +       };
>> +
>> +       chosen {
>> +               stdout-path = &uart3;
>> +               bootargs = "console=ttyS0,115200";
>> +       };
>> +};
>> --
>> 1.7.9.5
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v8 4/8] ARM: dts: Enable Broadcom Cygnus SoC

[Olof Johansson]

On Sat, Nov 8, 2014 at 10:13 PM, Scott Branden <sbranden@broadcom.com> wrote:
> On 14-11-08 04:22 PM, Olof Johansson wrote:
>>
>> Hi,
>>
>> A bunch of small comments below, should be quick to fix.
>>
>> On Tue, Oct 28, 2014 at 12:53 PM, Scott Branden <sbranden@broadcom.com>
>> wrote:
>>>
>>> DT files to enable cygnus consisting on reference designs
>>> and cygnus core configuration.
>>>
>>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>>> Reviewed-by: Arun Parameswaran <aparames@broadcom.com>
>>> Tested-by: Jonathan Richardson <jonathar@broadcom.com>
>>> Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
>>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>>> ---
>>>   arch/arm/boot/dts/Makefile              |    4 ++
>>>   arch/arm/boot/dts/bcm-cygnus-clock.dtsi |   73 ++++++++++++++++++++++
>>>   arch/arm/boot/dts/bcm-cygnus.dtsi       |  100
>>> +++++++++++++++++++++++++++++++
>>>   arch/arm/boot/dts/bcm911360_entphn.dts  |   32 ++++++++++
>>>   arch/arm/boot/dts/bcm911360k.dts        |   32 ++++++++++
>>>   arch/arm/boot/dts/bcm958300k.dts        |   32 ++++++++++
>>>   6 files changed, 273 insertions(+)
>>>   create mode 100644 arch/arm/boot/dts/bcm-cygnus-clock.dtsi
>>>   create mode 100644 arch/arm/boot/dts/bcm-cygnus.dtsi
>>>   create mode 100644 arch/arm/boot/dts/bcm911360_entphn.dts
>>>   create mode 100644 arch/arm/boot/dts/bcm911360k.dts
>>>   create mode 100644 arch/arm/boot/dts/bcm958300k.dts
>>>
>>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>>> index 38c89ca..4b3a590 100644
>>> --- a/arch/arm/boot/dts/Makefile
>>> +++ b/arch/arm/boot/dts/Makefile
>>> @@ -54,6 +54,10 @@ dtb-$(CONFIG_ARCH_AT91)      += at91-sama5d4ek.dtb
>>>   dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
>>>   dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
>>>   dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
>>> +dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
>>> +       bcm911360_entphn.dtb \
>>> +       bcm911360k.dtb \
>>> +       bcm958300k.dtb
>>>   dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
>>>   dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb
>>>   dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
>>
>>
>> Please add new entries in alphabetical/alphanumerical order. Also,
>> first entry is commonly added on the first line
>>
>>
>>> diff --git a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
>>> b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
>>> new file mode 100644
>>> index 0000000..d06172b
>>> --- /dev/null
>>> +++ b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi
>>> @@ -0,0 +1,73 @@
>>> +/*
>>> + * Copyright 2014 Broadcom Corporation.  All rights reserved.
>>> + *
>>> + * Unless you and Broadcom execute a separate written software license
>>> + * agreement governing use of this software, this software is licensed
>>> to you
>>> + * under the terms of the GNU General Public License as
>>> + * published by the Free Software Foundation version 2.
>>> + *
>>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>>> + * kind, whether express or implied; without even the implied warranty
>>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>> + * GNU General Public License for more details.
>>
>>
>> We ask for new DT contents to be added with dual BSD/GPL license, to
>> allow for reuse of the DT data structures in other projects as well.
>> There's currently a lot of activity going on relicensing the current
>> files so I recommend sorting it out before they are added if you can.
>
>
> This may take more time than you think.  I am going to have to go through
> legal to get such a license created. Also, why would you need dual license?
> If it is BSD that should serve both purposes?

I haven't followed the discussion close enough to know if there's been
discussion about single-license BSD vs dual BSD/GPL.

At the very least, please start the process of getting it changed.

Also, I see now that this isn't even a clean GPL v2, given "Unless you
and Broadcom..." language. I see the bnx2x driver had that in the
past, but none of the Kona contributions did. I strongly suggest
sticking to the normal copyrights here and not making things more
complicated than they have to.


-Olof

Re: [PATCH v8 4/8] ARM: dts: Enable Broadcom Cygnus SoC

[Greg Kroah-Hartman]

On Sat, Nov 08, 2014 at 10:49:09PM -0800, Olof Johansson wrote:
> >>> +/*
> >>> + * Copyright 2014 Broadcom Corporation.  All rights reserved.
> >>> + *
> >>> + * Unless you and Broadcom execute a separate written software license
> >>> + * agreement governing use of this software, this software is licensed
> >>> to you
> >>> + * under the terms of the GNU General Public License as
> >>> + * published by the Free Software Foundation version 2.
> >>> + *
> >>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> >>> + * kind, whether express or implied; without even the implied warranty
> >>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> >>> + * GNU General Public License for more details.
> >>
> >>
> >> We ask for new DT contents to be added with dual BSD/GPL license, to
> >> allow for reuse of the DT data structures in other projects as well.
> >> There's currently a lot of activity going on relicensing the current
> >> files so I recommend sorting it out before they are added if you can.
> >
> >
> > This may take more time than you think.  I am going to have to go through
> > legal to get such a license created. Also, why would you need dual license?
> > If it is BSD that should serve both purposes?
> 
> I haven't followed the discussion close enough to know if there's been
> discussion about single-license BSD vs dual BSD/GPL.
> 
> At the very least, please start the process of getting it changed.
> 
> Also, I see now that this isn't even a clean GPL v2, given "Unless you
> and Broadcom..." language. I see the bnx2x driver had that in the
> past, but none of the Kona contributions did. I strongly suggest
> sticking to the normal copyrights here and not making things more
> complicated than they have to.

I'm thinking that the "unless you and Broadcom..." language really
doesn't mean much other than what all other files in the kernel mean
from what I can tell.  This should just default to GPLv2 and everyone
should be ok.

But note, I'm not a lawyer, it would be good to get a confirmation from
Broadcom that this is the exact wording they want in this file, and that
they are happy with it being "just" GPLv2 for all intensive purposes, as
it does "differ" from the wording we are "accustomed" to seeing in
kernel files.

thanks,

greg k-h

Re: [PATCH v8 4/8] ARM: dts: Enable Broadcom Cygnus SoC

[Arnd Bergmann]

On Sunday 09 November 2014 09:23:11 Greg Kroah-Hartman wrote:
> On Sat, Nov 08, 2014 at 10:49:09PM -0800, Olof Johansson wrote:
> > >>> +/*
> > >>> + * Copyright 2014 Broadcom Corporation.  All rights reserved.
> > >>> + *
> > >>> + * Unless you and Broadcom execute a separate written software license
> > >>> + * agreement governing use of this software, this software is licensed
> > >>> to you
> > >>> + * under the terms of the GNU General Public License as
> > >>> + * published by the Free Software Foundation version 2.
> > >>> + *
> > >>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> > >>> + * kind, whether express or implied; without even the implied warranty
> > >>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > >>> + * GNU General Public License for more details.
> > >>
> > >>
> > >> We ask for new DT contents to be added with dual BSD/GPL license, to
> > >> allow for reuse of the DT data structures in other projects as well.
> > >> There's currently a lot of activity going on relicensing the current
> > >> files so I recommend sorting it out before they are added if you can.
> > >
> > >
> > > This may take more time than you think.  I am going to have to go through
> > > legal to get such a license created. Also, why would you need dual license?
> > > If it is BSD that should serve both purposes?
> >
> > I haven't followed the discussion close enough to know if there's been
> > discussion about single-license BSD vs dual BSD/GPL.

I think for all practical purposes, BSD and dual BSD/GPL is the same and
listing it as dual was meant as a clarification to make it easier to see
that all files in the kernel are GPLv2 compatible.
 
> > At the very least, please start the process of getting it changed.
> > 
> > Also, I see now that this isn't even a clean GPL v2, given "Unless you
> > and Broadcom..." language. I see the bnx2x driver had that in the
> > past, but none of the Kona contributions did. I strongly suggest
> > sticking to the normal copyrights here and not making things more
> > complicated than they have to.
> 
> I'm thinking that the "unless you and Broadcom..." language really
> doesn't mean much other than what all other files in the kernel mean
> from what I can tell.  This should just default to GPLv2 and everyone
> should be ok.

I would hope so at least. It's certainly not obvious whether that means
Broadcom can give additional rights to someone over what someone else
contributed upstream, or worse if this becomes GPL-incompatible and
makes the kernel undistributable for anybody who has an additional
license agreement that doesn't give them all the rights that they already
had under the GPL.

	Arnd

Re: [PATCH v8 4/8] ARM: dts: Enable Broadcom Cygnus SoC

[Scott Branden]

On 14-11-09 12:38 PM, Arnd Bergmann wrote:
> On Sunday 09 November 2014 09:23:11 Greg Kroah-Hartman wrote:
>> On Sat, Nov 08, 2014 at 10:49:09PM -0800, Olof Johansson wrote:
>>>>>> +/*
>>>>>> + * Copyright 2014 Broadcom Corporation.  All rights reserved.
>>>>>> + *
>>>>>> + * Unless you and Broadcom execute a separate written software license
>>>>>> + * agreement governing use of this software, this software is licensed
>>>>>> to you
>>>>>> + * under the terms of the GNU General Public License as
>>>>>> + * published by the Free Software Foundation version 2.
>>>>>> + *
>>>>>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>>>>>> + * kind, whether express or implied; without even the implied warranty
>>>>>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>>>>> + * GNU General Public License for more details.
>>>>>
>>>>>
>>>>> We ask for new DT contents to be added with dual BSD/GPL license, to
>>>>> allow for reuse of the DT data structures in other projects as well.
>>>>> There's currently a lot of activity going on relicensing the current
>>>>> files so I recommend sorting it out before they are added if you can.
>>>>
>>>>
>>>> This may take more time than you think.  I am going to have to go through
>>>> legal to get such a license created. Also, why would you need dual license?
>>>> If it is BSD that should serve both purposes?
>>>
>>> I haven't followed the discussion close enough to know if there's been
>>> discussion about single-license BSD vs dual BSD/GPL.
>
> I think for all practical purposes, BSD and dual BSD/GPL is the same and
> listing it as dual was meant as a clarification to make it easier to see
> that all files in the kernel are GPLv2 compatible.
A dual BSD/GPL may involve having me get a lawyer to create such a 
header.  I would prefer to leave it as GPL for now until some concrete 
decision has finally been made on this by the rest of the community? 
Or, I can put it as BSD right now if that helps?
>
>>> At the very least, please start the process of getting it changed.
>>>
>>> Also, I see now that this isn't even a clean GPL v2, given "Unless you
>>> and Broadcom..." language. I see the bnx2x driver had that in the
>>> past, but none of the Kona contributions did. I strongly suggest
>>> sticking to the normal copyrights here and not making things more
>>> complicated than they have to.
>>
>> I'm thinking that the "unless you and Broadcom..." language really
>> doesn't mean much other than what all other files in the kernel mean
>> from what I can tell.  This should just default to GPLv2 and everyone
>> should be ok.
>
> I would hope so at least. It's certainly not obvious whether that means
> Broadcom can give additional rights to someone over what someone else
> contributed upstream, or worse if this becomes GPL-incompatible and
> makes the kernel undistributable for anybody who has an additional
> license agreement that doesn't give them all the rights that they already
> had under the GPL.
I'll change the header on these files so there are no disagreements.
>
> 	Arnd
>

[PATCH 1/2] ARM: multi_v7_defconfig: remove one level of menu from Kconfig

[Scott Branden]

remove menu "Broadcom Mobile SoC Selection"
This requires:
- selecting ARCH_BCM_MOBILE based on SoC selections
- fixup multi_v7_defconfig to work with new menu levels of mach-bcm.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/configs/multi_v7_defconfig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 491b7d5..e8f79fd 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -17,7 +17,8 @@ CONFIG_MACH_ARMADA_38X=y
 CONFIG_MACH_ARMADA_XP=y
 CONFIG_MACH_DOVE=y
 CONFIG_ARCH_BCM=y
-CONFIG_ARCH_BCM_MOBILE=y
+CONFIG_ARCH_BCM_21664=y
+CONFIG_ARCH_BCM_281XX=y
 CONFIG_ARCH_BCM_5301X=y
 CONFIG_ARCH_BRCMSTB=y
 CONFIG_ARCH_BERLIN=y
-- 
2.1.3

[PATCH 2/2] ARM: multi_v7_defconfig: Enable Broadcom Cygnus

[Scott Branden]

From: Ray Jui <rjui@broadcom.com>

Enable Broadcom Cygnus platform support in multi_v7_defconfig

Signed-off-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 arch/arm/configs/multi_v7_defconfig | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index e8f79fd..f3ef3f5 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -17,6 +17,7 @@ CONFIG_MACH_ARMADA_38X=y
 CONFIG_MACH_ARMADA_XP=y
 CONFIG_MACH_DOVE=y
 CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BCM_CYGNUS=y
 CONFIG_ARCH_BCM_21664=y
 CONFIG_ARCH_BCM_281XX=y
 CONFIG_ARCH_BCM_5301X=y
@@ -125,8 +126,12 @@ CONFIG_DMA_CMA=y
 CONFIG_CMA_SIZE_MBYTES=64
 CONFIG_OMAP_OCP2SCP=y
 CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
 CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
 CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_UBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_AD525X_DPOT=y
 CONFIG_AD525X_DPOT_I2C=y
@@ -161,6 +166,7 @@ CONFIG_TI_CPSW=y
 CONFIG_XILINX_EMACLITE=y
 CONFIG_AT803X_PHY=y
 CONFIG_MARVELL_PHY=y
+CONFIG_BROADCOM_PHY=y
 CONFIG_ICPLUS_PHY=y
 CONFIG_USB_PEGASUS=y
 CONFIG_USB_USBNET=y
@@ -234,6 +240,7 @@ CONFIG_SPI_TEGRA114=y
 CONFIG_SPI_TEGRA20_SFLASH=y
 CONFIG_SPI_TEGRA20_SLINK=y
 CONFIG_SPI_XILINX=y
+CONFIG_SPI_SPIDEV=y
 CONFIG_PINCTRL_AS3722=y
 CONFIG_PINCTRL_PALMAS=y
 CONFIG_GPIO_SYSFS=y
@@ -260,6 +267,7 @@ CONFIG_ST_THERMAL_SYSCFG=y
 CONFIG_ST_THERMAL_MEMMAP=y
 CONFIG_WATCHDOG=y
 CONFIG_XILINX_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
 CONFIG_ORION_WATCHDOG=y
 CONFIG_SUNXI_WATCHDOG=y
 CONFIG_MFD_AS3722=y
@@ -306,6 +314,8 @@ CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
 CONFIG_SOUND=y
 CONFIG_SND=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_USB_AUDIO=y
 CONFIG_SND_SOC=y
 CONFIG_SND_SOC_TEGRA=y
 CONFIG_SND_SOC_TEGRA_RT5640=y
@@ -427,7 +437,12 @@ CONFIG_TI_PIPE3=y
 CONFIG_PHY_MIPHY365X=y
 CONFIG_PHY_SUN4I_USB=y
 CONFIG_EXT4_FS=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_UBIFS_FS=y
 CONFIG_TMPFS=y
 CONFIG_SQUASHFS=y
 CONFIG_SQUASHFS_LZO=y
@@ -436,6 +451,9 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3_ACL=y
 CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
 CONFIG_PRINTK_TIME=y
 CONFIG_DEBUG_FS=y
 CONFIG_MAGIC_SYSRQ=y
-- 
2.1.3

Re: [PATCH v8 4/8] ARM: dts: Enable Broadcom Cygnus SoC

[Arnd Bergmann]

On Sunday 09 November 2014 21:17:37 Scott Branden wrote:
> On 14-11-09 12:38 PM, Arnd Bergmann wrote:
> > On Sunday 09 November 2014 09:23:11 Greg Kroah-Hartman wrote:
> >> On Sat, Nov 08, 2014 at 10:49:09PM -0800, Olof Johansson wrote:
> >>>>>> +/*
> >>>>>> + * Copyright 2014 Broadcom Corporation.  All rights reserved.
> >>>>>> + *
> >>>>>> + * Unless you and Broadcom execute a separate written software license
> >>>>>> + * agreement governing use of this software, this software is licensed
> >>>>>> to you
> >>>>>> + * under the terms of the GNU General Public License as
> >>>>>> + * published by the Free Software Foundation version 2.
> >>>>>> + *
> >>>>>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> >>>>>> + * kind, whether express or implied; without even the implied warranty
> >>>>>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> >>>>>> + * GNU General Public License for more details.
> >>>>>
> >>>>>
> >>>>> We ask for new DT contents to be added with dual BSD/GPL license, to
> >>>>> allow for reuse of the DT data structures in other projects as well.
> >>>>> There's currently a lot of activity going on relicensing the current
> >>>>> files so I recommend sorting it out before they are added if you can.
> >>>>
> >>>>
> >>>> This may take more time than you think.  I am going to have to go through
> >>>> legal to get such a license created. Also, why would you need dual license?
> >>>> If it is BSD that should serve both purposes?
> >>>
> >>> I haven't followed the discussion close enough to know if there's been
> >>> discussion about single-license BSD vs dual BSD/GPL.
> >
> > I think for all practical purposes, BSD and dual BSD/GPL is the same and
> > listing it as dual was meant as a clarification to make it easier to see
> > that all files in the kernel are GPLv2 compatible.
> A dual BSD/GPL may involve having me get a lawyer to create such a 
> header.  I would prefer to leave it as GPL for now until some concrete 
> decision has finally been made on this by the rest of the community? 
> Or, I can put it as BSD right now if that helps?

I would prefer a pure BSD header for the moment over a pure GPL header.
The last thing we want is to force other operating systems to create
another set of dts files for the same hardware.

	Arnd

Re: [PATCH v9 4/8] ARM: dts: Enable Broadcom Cygnus SoC

[Paul Bolle]

On Tue, 2014-10-28 at 16:15 -0700, Scott Branden wrote:
> DT files to enable cygnus consisting on reference designs
> and cygnus core configuration.
> 
> Reviewed-by: Ray Jui <rjui@broadcom.com>
> Reviewed-by: Arun Parameswaran <aparames@broadcom.com>
> Tested-by: Jonathan Richardson <jonathar@broadcom.com>
> Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
> Signed-off-by: Scott Branden <sbranden@broadcom.com>

This landed in today's linux-next (ie, next-21041110) as commit
8872fc22c267 ("ARM: dts: Enable Broadcom Cygnus SoC").

>  arch/arm/boot/dts/Makefile              |    4 ++
>  arch/arm/boot/dts/bcm-cygnus-clock.dtsi |   73 ++++++++++++++++++++++
>  arch/arm/boot/dts/bcm-cygnus.dtsi       |  100 +++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/bcm911360_entphn.dts  |   32 ++++++++++
>  arch/arm/boot/dts/bcm911360k.dts        |   32 ++++++++++
>  arch/arm/boot/dts/bcm958300k.dts        |   32 ++++++++++
>  6 files changed, 273 insertions(+)
>  create mode 100644 arch/arm/boot/dts/bcm-cygnus-clock.dtsi
>  create mode 100644 arch/arm/boot/dts/bcm-cygnus.dtsi
>  create mode 100644 arch/arm/boot/dts/bcm911360_entphn.dts
>  create mode 100644 arch/arm/boot/dts/bcm911360k.dts
>  create mode 100644 arch/arm/boot/dts/bcm958300k.dts
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 38c89ca..4b3a590 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -54,6 +54,10 @@ dtb-$(CONFIG_ARCH_AT91)	+= at91-sama5d4ek.dtb
>  dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
>  dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
>  dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
> +dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
> +	bcm911360_entphn.dtb \
> +	bcm911360k.dtb \
> +	bcm958300k.dtb
>  dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
>  dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb
>  dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \

Without patch 1/8 ("ARM: cygnus: Initial support for Broadcom Cygnus
SoC") CONFIG_ARCH_BCM_CYGNUS will not be set. I guess patch 1/8 will be
added to linux-next one of these days. Is that correct?


Paul Bolle

Re: [PATCH v8 4/8] ARM: dts: Enable Broadcom Cygnus SoC

[Scott Branden]

On 14-11-10 12:11 AM, Arnd Bergmann wrote:
> On Sunday 09 November 2014 21:17:37 Scott Branden wrote:
>> On 14-11-09 12:38 PM, Arnd Bergmann wrote:
>>> On Sunday 09 November 2014 09:23:11 Greg Kroah-Hartman wrote:
>>>> On Sat, Nov 08, 2014 at 10:49:09PM -0800, Olof Johansson wrote:
>>>>>>>> +/*
>>>>>>>> + * Copyright 2014 Broadcom Corporation.  All rights reserved.
>>>>>>>> + *
>>>>>>>> + * Unless you and Broadcom execute a separate written software license
>>>>>>>> + * agreement governing use of this software, this software is licensed
>>>>>>>> to you
>>>>>>>> + * under the terms of the GNU General Public License as
>>>>>>>> + * published by the Free Software Foundation version 2.
>>>>>>>> + *
>>>>>>>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>>>>>>>> + * kind, whether express or implied; without even the implied warranty
>>>>>>>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>>>>>>> + * GNU General Public License for more details.
>>>>>>>
>>>>>>>
>>>>>>> We ask for new DT contents to be added with dual BSD/GPL license, to
>>>>>>> allow for reuse of the DT data structures in other projects as well.
>>>>>>> There's currently a lot of activity going on relicensing the current
>>>>>>> files so I recommend sorting it out before they are added if you can.
>>>>>>
>>>>>>
>>>>>> This may take more time than you think.  I am going to have to go through
>>>>>> legal to get such a license created. Also, why would you need dual license?
>>>>>> If it is BSD that should serve both purposes?
>>>>>
>>>>> I haven't followed the discussion close enough to know if there's been
>>>>> discussion about single-license BSD vs dual BSD/GPL.
>>>
>>> I think for all practical purposes, BSD and dual BSD/GPL is the same and
>>> listing it as dual was meant as a clarification to make it easier to see
>>> that all files in the kernel are GPLv2 compatible.
>> A dual BSD/GPL may involve having me get a lawyer to create such a
>> header.  I would prefer to leave it as GPL for now until some concrete
>> decision has finally been made on this by the rest of the community?
>> Or, I can put it as BSD right now if that helps?
>
> I would prefer a pure BSD header for the moment over a pure GPL header.
> The last thing we want is to force other operating systems to create
> another set of dts files for the same hardware.
I have changed the headers to pure BSD.  I hope this is acceptable.
>
> 	Arnd
>

Re: [PATCH v9 4/8] ARM: dts: Enable Broadcom Cygnus SoC

[Olof Johansson]

On Mon, Nov 10, 2014 at 2:50 AM, Paul Bolle <pebolle@tiscali.nl> wrote:
> On Tue, 2014-10-28 at 16:15 -0700, Scott Branden wrote:
>> DT files to enable cygnus consisting on reference designs
>> and cygnus core configuration.
>>
>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>> Reviewed-by: Arun Parameswaran <aparames@broadcom.com>
>> Tested-by: Jonathan Richardson <jonathar@broadcom.com>
>> Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>
> This landed in today's linux-next (ie, next-21041110) as commit
> 8872fc22c267 ("ARM: dts: Enable Broadcom Cygnus SoC").
>
>>  arch/arm/boot/dts/Makefile              |    4 ++
>>  arch/arm/boot/dts/bcm-cygnus-clock.dtsi |   73 ++++++++++++++++++++++
>>  arch/arm/boot/dts/bcm-cygnus.dtsi       |  100 +++++++++++++++++++++++++++++++
>>  arch/arm/boot/dts/bcm911360_entphn.dts  |   32 ++++++++++
>>  arch/arm/boot/dts/bcm911360k.dts        |   32 ++++++++++
>>  arch/arm/boot/dts/bcm958300k.dts        |   32 ++++++++++
>>  6 files changed, 273 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/bcm-cygnus-clock.dtsi
>>  create mode 100644 arch/arm/boot/dts/bcm-cygnus.dtsi
>>  create mode 100644 arch/arm/boot/dts/bcm911360_entphn.dts
>>  create mode 100644 arch/arm/boot/dts/bcm911360k.dts
>>  create mode 100644 arch/arm/boot/dts/bcm958300k.dts
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index 38c89ca..4b3a590 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -54,6 +54,10 @@ dtb-$(CONFIG_ARCH_AT91)    += at91-sama5d4ek.dtb
>>  dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
>>  dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
>>  dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
>> +dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
>> +     bcm911360_entphn.dtb \
>> +     bcm911360k.dtb \
>> +     bcm958300k.dtb
>>  dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
>>  dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb
>>  dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
>
> Without patch 1/8 ("ARM: cygnus: Initial support for Broadcom Cygnus
> SoC") CONFIG_ARCH_BCM_CYGNUS will not be set. I guess patch 1/8 will be
> added to linux-next one of these days. Is that correct?

Yes.


-Olof

Re: [PATCH v9 4/8] ARM: dts: Enable Broadcom Cygnus SoC

[Paul Bolle]

On Mon, 2014-11-10 at 10:35 -0800, Olof Johansson wrote:
> On Mon, Nov 10, 2014 at 2:50 AM, Paul Bolle <pebolle@tiscali.nl> wrote:
> > I guess patch 1/8 will be added to linux-next one of these days. Is
> > that correct?
> 
> Yes.

Thanks.


Paul Bolle

[PATCH 0/4] pwm: kona: Drivers fixes

[Scott Branden]

This patchset contains fixes for Broadcom's Kona PWM driver.

These changes fix glitch issues when changing settings on different channels.
Kconfig change made to allow the driver to work on any Broadcom SoC rather
than just mobile devices.

Arun Ramamurthy (4):
  pwm: kona: Remove setting default smooth type and polarity for all
    channels
  pwm: kona: Fix incorrect enable after channel polarity change
  pwm: kona: Fix enable, disable and config procedures
  pwm: kona: Update dependency to ARCH_BCM

 drivers/pwm/Kconfig        |   2 +-
 drivers/pwm/pwm-bcm-kona.c | 112 ++++++++++++++++++++++++++++++++-------------
 2 files changed, 81 insertions(+), 33 deletions(-)

-- 
2.1.3

[PATCH 1/4] pwm: kona: Remove setting default smooth type and polarity for all channels

[Scott Branden]

From: Arun Ramamurthy <arunrama@broadcom.com>

The probe routine unnecessarily sets the smooth type and polarity for
all channels. This causes the channel for the speaker to click at the same
time the backlight turns on. The smooth type and polarity should be set individually
for each channel as required and no defaults need to be set.

Signed-off-by: Arun Ramamurthy <arunrama@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/pwm/pwm-bcm-kona.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
index 02bc048..29eef9e 100644
--- a/drivers/pwm/pwm-bcm-kona.c
+++ b/drivers/pwm/pwm-bcm-kona.c
@@ -266,12 +266,9 @@ static int kona_pwmc_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	/* Set smooth mode, push/pull, and normal polarity for all channels */
-	for (chan = 0; chan < kp->chip.npwm; chan++) {
-		value |= (1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
+	/* Set push/pull for all channels */
+	for (chan = 0; chan < kp->chip.npwm; chan++)
 		value |= (1 << PWM_CONTROL_TYPE_SHIFT(chan));
-		value |= (1 << PWM_CONTROL_POLARITY_SHIFT(chan));
-	}
 
 	writel(value, kp->base + PWM_CONTROL_OFFSET);
 
-- 
2.1.3

[PATCH 2/4] pwm: kona: Fix incorrect enable after channel polarity change

[Scott Branden]

From: Arun Ramamurthy <arunrama@broadcom.com>

The pwm core code requires a separate call for enabling the channel
and hence the driver does not need to set pwm_trigger after a
polarity change

Signed-off-by: Arun Ramamurthy <arunrama@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/pwm/pwm-bcm-kona.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
index 29eef9e..fa0b5bf 100644
--- a/drivers/pwm/pwm-bcm-kona.c
+++ b/drivers/pwm/pwm-bcm-kona.c
@@ -173,11 +173,6 @@ static int kona_pwmc_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
 
 	writel(value, kp->base + PWM_CONTROL_OFFSET);
 
-	kona_pwmc_apply_settings(kp, chan);
-
-	/* Wait for waveform to settle before gating off the clock */
-	ndelay(400);
-
 	clk_disable_unprepare(kp->clk);
 
 	return 0;
-- 
2.1.3

[PATCH 3/4] pwm: kona: Fix enable, disable and config procedures

[Scott Branden]

From: Arun Ramamurthy <arunrama@broadcom.com>

- Added helper functions to set and clear smooth and trigger bits
- Added 400ns delays when clearing and setting trigger bit as requied
  by spec
- Added helper function to write prescale and other settings
- Updated config procedure to match spec
- Added code to handle pwn config when channel is disabled
- Updated disable procedure to match spec

Signed-off-by: Arun Ramamurthy <arunrama@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/pwm/pwm-bcm-kona.c | 100 +++++++++++++++++++++++++++++++++++----------
 1 file changed, 78 insertions(+), 22 deletions(-)

diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
index fa0b5bf..06fa983 100644
--- a/drivers/pwm/pwm-bcm-kona.c
+++ b/drivers/pwm/pwm-bcm-kona.c
@@ -65,6 +65,10 @@
 #define DUTY_CYCLE_HIGH_MIN			(0x00000000)
 #define DUTY_CYCLE_HIGH_MAX			(0x00ffffff)
 
+/* The delay required after clearing or setting
+   PWMOUT_ENABLE*/
+#define PWMOUT_ENABLE_HOLD_DELAY 400
+
 struct kona_pwmc {
 	struct pwm_chip chip;
 	void __iomem *base;
@@ -76,28 +80,70 @@ static inline struct kona_pwmc *to_kona_pwmc(struct pwm_chip *_chip)
 	return container_of(_chip, struct kona_pwmc, chip);
 }
 
-static void kona_pwmc_apply_settings(struct kona_pwmc *kp, unsigned int chan)
+static inline void kona_pwmc_set_trigger(struct kona_pwmc *kp,
+					 unsigned int chan)
 {
 	unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
 
-	/* Clear trigger bit but set smooth bit to maintain old output */
-	value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);
+	/* set trigger bit to enable channel */
+	value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
+	writel(value, kp->base + PWM_CONTROL_OFFSET);
+	ndelay(PWMOUT_ENABLE_HOLD_DELAY);
+}
+static inline void kona_pwmc_clear_trigger(struct kona_pwmc *kp,
+					   unsigned int chan)
+{
+	unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
+
+	/* Clear trigger bit */
 	value &= ~(1 << PWM_CONTROL_TRIGGER_SHIFT(chan));
 	writel(value, kp->base + PWM_CONTROL_OFFSET);
+	ndelay(PWMOUT_ENABLE_HOLD_DELAY);
+}
 
-	/* Set trigger bit and clear smooth bit to apply new settings */
+static inline void kona_pwmc_clear_smooth(struct kona_pwmc *kp,
+					  unsigned int chan)
+{
+	unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
+
+	/* Clear smooth bit */
 	value &= ~(1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
-	value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
 	writel(value, kp->base + PWM_CONTROL_OFFSET);
 }
 
+static inline void kona_pwmc_set_smooth(struct kona_pwmc *kp, unsigned int chan)
+{
+	unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
+
+	/*  set smooth bit to maintain old output */
+	value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);
+	writel(value, kp->base + PWM_CONTROL_OFFSET);
+}
+
+static void kona_pwmc_write_settings(struct kona_pwmc *kp, unsigned int chan,
+				     unsigned long prescale, unsigned long pc,
+				     unsigned long dc)
+{
+	unsigned int value;
+
+	value = readl(kp->base + PRESCALE_OFFSET);
+	value &= ~PRESCALE_MASK(chan);
+	value |= prescale << PRESCALE_SHIFT(chan);
+	writel(value, kp->base + PRESCALE_OFFSET);
+
+	writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
+
+	writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
+
+}
+
 static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm,
 			    int duty_ns, int period_ns)
 {
 	struct kona_pwmc *kp = to_kona_pwmc(chip);
 	u64 val, div, rate;
 	unsigned long prescale = PRESCALE_MIN, pc, dc;
-	unsigned int value, chan = pwm->hwpwm;
+	unsigned int ret, chan = pwm->hwpwm;
 
 	/*
 	 * Find period count, duty count and prescale to suit duty_ns and
@@ -133,19 +179,30 @@ static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm,
 			return -EINVAL;
 	}
 
-	/* If the PWM channel is enabled, write the settings to the HW */
-	if (test_bit(PWMF_ENABLED, &pwm->flags)) {
-		value = readl(kp->base + PRESCALE_OFFSET);
-		value &= ~PRESCALE_MASK(chan);
-		value |= prescale << PRESCALE_SHIFT(chan);
-		writel(value, kp->base + PRESCALE_OFFSET);
 
-		writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
+	/* If the PWM channel is not enabled, enable the clock */
+	if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
+		ret = clk_prepare_enable(kp->clk);
+		if (ret < 0) {
+			dev_err(chip->dev, "failed to enable clock: %d\n", ret);
+			return ret;
+		}
+	}
 
-		writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
+	/* Set smooth bit to maintain old output */
+	kona_pwmc_set_smooth(kp, chan);
+	kona_pwmc_clear_trigger(kp, chan);
+
+	/* apply new settings */
+	kona_pwmc_write_settings(kp, chan, prescale, pc, dc);
+
+	/*If the PWM is enabled, enable the channel with the new settings
+	 and if not  disable the clock*/
+	if (test_bit(PWMF_ENABLED, &pwm->flags))
+		kona_pwmc_set_trigger(kp, chan);
+	else
+		clk_disable_unprepare(kp->clk);
 
-		kona_pwmc_apply_settings(kp, chan);
-	}
 
 	return 0;
 }
@@ -188,7 +245,6 @@ static int kona_pwmc_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 		dev_err(chip->dev, "failed to enable clock: %d\n", ret);
 		return ret;
 	}
-
 	ret = kona_pwmc_config(chip, pwm, pwm->duty_cycle, pwm->period);
 	if (ret < 0) {
 		clk_disable_unprepare(kp->clk);
@@ -203,12 +259,12 @@ static void kona_pwmc_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 	struct kona_pwmc *kp = to_kona_pwmc(chip);
 	unsigned int chan = pwm->hwpwm;
 
+	kona_pwmc_clear_smooth(kp, chan);
+	kona_pwmc_clear_trigger(kp, chan);
 	/* Simulate a disable by configuring for zero duty */
-	writel(0, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
-	kona_pwmc_apply_settings(kp, chan);
-
-	/* Wait for waveform to settle before gating off the clock */
-	ndelay(400);
+	kona_pwmc_write_settings(kp, chan, 0, 0, 0);
+	kona_pwmc_set_polarity(chip, pwm, PWM_POLARITY_NORMAL);
+	kona_pwmc_set_trigger(kp, chan);
 
 	clk_disable_unprepare(kp->clk);
 }
-- 
2.1.3

[PATCH 4/4] pwm: kona: Update dependency to ARCH_BCM

[Scott Branden]

From: Arun Ramamurthy <arunrama@broadcom.com>

Signed-off-by: Arun Ramamurthy <arunrama@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/pwm/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index ef2dd2e..186080e 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -64,7 +64,7 @@ config PWM_ATMEL_TCB
 
 config PWM_BCM_KONA
 	tristate "Kona PWM support"
-	depends on ARCH_BCM_MOBILE
+	depends on ARCH_BCM
 	help
 	  Generic PWM framework driver for Broadcom Kona PWM block.
 
-- 
2.1.3

Re: [PATCH 0/4] pwm: kona: Drivers fixes

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 985 bytes --]

On Fri, Nov 14, 2014 at 10:29:56AM -0800, Scott Branden wrote:
> This patchset contains fixes for Broadcom's Kona PWM driver.
> 
> These changes fix glitch issues when changing settings on different channels.
> Kconfig change made to allow the driver to work on any Broadcom SoC rather
> than just mobile devices.
> 
> Arun Ramamurthy (4):
>   pwm: kona: Remove setting default smooth type and polarity for all
>     channels
>   pwm: kona: Fix incorrect enable after channel polarity change
>   pwm: kona: Fix enable, disable and config procedures
>   pwm: kona: Update dependency to ARCH_BCM
> 
>  drivers/pwm/Kconfig        |   2 +-
>  drivers/pwm/pwm-bcm-kona.c | 112 ++++++++++++++++++++++++++++++++-------------
>  2 files changed, 81 insertions(+), 33 deletions(-)

Can you please resend with Tim Kryger <tim.kryger@gmail.com> in Cc. He
originally submitted the driver and I'd like him to at least have the
opportunity of looking at the patches.

Thierry

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Re: [PATCH 4/4] pwm: kona: Update dependency to ARCH_BCM

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 213 bytes --]

On Fri, Nov 14, 2014 at 10:30:00AM -0800, Scott Branden wrote:
> From: Arun Ramamurthy <arunrama@broadcom.com>
> 

There's no patch description here. You should describe why you make this
change.

Thierry

[-- Attachment #2: Type: application/pgp-signature, Size: 819 bytes --]

Re: [PATCH 4/4] pwm: kona: Update dependency to ARCH_BCM

[Scott Branden]

On 14-11-17 04:52 AM, Thierry Reding wrote:
> On Fri, Nov 14, 2014 at 10:30:00AM -0800, Scott Branden wrote:
>> From: Arun Ramamurthy <arunrama@broadcom.com>
>>
>
> There's no patch description here. You should describe why you make this
> change.
Updated - sent v2 of patchset with Tim Kryger on cc list.
>
> Thierry
>

Re: [PATCH v9 2/8] dt-bindings: Document Broadcom Cygnus SoC and clocks

[Mike Turquette]

Quoting Scott Branden (2014-10-28 16:15:05)
> From: Jonathan Richardson <jonathar@broadcom.com>
> 
> Reviewed-by: Arun Parameswaran <aparames@broadcom.com>
> Tested-by: Jonathan Richardson <jonathar@broadcom.com>
> Reviewed-by: JD (Jiandong) Zheng <jdzheng@broadcom.com>
> Reviewed-by: Ray Jui <rjui@broadcom.com>
> Signed-off-by: Scott Branden <sbranden@broadcom.com>

Acked-by: Michael Turquette <mturquette@linaro.org>

> ---
>  .../devicetree/bindings/arm/bcm/cygnus.txt         |   31 ++++++++++++++++++
>  .../devicetree/bindings/clock/bcm-cygnus-clock.txt |   34 ++++++++++++++++++++
>  2 files changed, 65 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/bcm/cygnus.txt
>  create mode 100644 Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/bcm/cygnus.txt b/Documentation/devicetree/bindings/arm/bcm/cygnus.txt
> new file mode 100644
> index 0000000..4c77169
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/bcm/cygnus.txt
> @@ -0,0 +1,31 @@
> +Broadcom Cygnus device tree bindings
> +------------------------------------
> +
> +
> +Boards with Cygnus SoCs shall have the following properties:
> +
> +Required root node property:
> +
> +BCM11300
> +compatible = "brcm,bcm11300", "brcm,cygnus";
> +
> +BCM11320
> +compatible = "brcm,bcm11320", "brcm,cygnus";
> +
> +BCM11350
> +compatible = "brcm,bcm11350", "brcm,cygnus";
> +
> +BCM11360
> +compatible = "brcm,bcm11360", "brcm,cygnus";
> +
> +BCM58300
> +compatible = "brcm,bcm58300", "brcm,cygnus";
> +
> +BCM58302
> +compatible = "brcm,bcm58302", "brcm,cygnus";
> +
> +BCM58303
> +compatible = "brcm,bcm58303", "brcm,cygnus";
> +
> +BCM58305
> +compatible = "brcm,bcm58305", "brcm,cygnus";
> diff --git a/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt b/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
> new file mode 100644
> index 0000000..00d26ed
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/bcm-cygnus-clock.txt
> @@ -0,0 +1,34 @@
> +Broadcom Cygnus Clocks
> +
> +This binding uses the common clock binding:
> +Documentation/devicetree/bindings/clock/clock-bindings.txt
> +
> +Currently various "fixed" clocks are declared for peripheral drivers that use
> +the common clock framework to reference their core clocks. Proper support of
> +these clocks will be added later
> +
> +Device tree example:
> +
> +       clocks {
> +               #address-cells = <1>;
> +               #size-cells = <1>;
> +               ranges;
> +
> +               osc: oscillator {
> +                       compatible = "fixed-clock";
> +                       #clock-cells = <1>;
> +                       clock-frequency = <25000000>;
> +               };
> +
> +               apb_clk: apb_clk {
> +                       compatible = "fixed-clock";
> +                       #clock-cells = <0>;
> +                       clock-frequency = <1000000000>;
> +               };
> +
> +               periph_clk: periph_clk {
> +                       compatible = "fixed-clock";
> +                       #clock-cells = <0>;
> +                       clock-frequency = <500000000>;
> +               };
> +       };
> -- 
> 1.7.9.5
> 

[PATCH] mtd: nand: added nand_shutdown

[Scott Branden]

Add nand_shutdown to wait for current nand operations to finish and prevent
further operations by changing the nand flash state to FL_SHUTDOWN.

This is addressing a problem observed during reboot tests using UBIFS
root file system: NAND erase operations that are in progress during
system reboot/shutdown are causing partial erased blocks. Although UBI should
be able to detect and recover from this error, this change will avoid
the creation of partial erased blocks on reboot in the middle of a NAND erase
operation.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/mtd/nand/nand_base.c | 11 +++++++++++
 include/linux/mtd/nand.h     |  7 +++++++
 2 files changed, 18 insertions(+)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 5b5c627..100a967 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -4236,6 +4236,17 @@ void nand_release(struct mtd_info *mtd)
 }
 EXPORT_SYMBOL_GPL(nand_release);
 
+/**
+ * nand_shutdown - [NAND Interface] finish the current nand operation and
+ *                 prevent further operations
+ * @mtd: MTD device structure
+ */
+int nand_shutdown(struct mtd_info *mtd)
+{
+	return nand_get_device(mtd, FL_SHUTDOWN);
+}
+EXPORT_SYMBOL_GPL(nand_shutdown);
+
 static int __init nand_base_init(void)
 {
 	led_trigger_register_simple("nand-disk", &nand_led_trigger);
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index e4d451e..80e4367 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -48,6 +48,13 @@ extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
 /* unlocks specified locked blocks */
 extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
 
+/*
+ * Internal helper for board drivers which need to make sure that the current
+ * nand operation is finished and further operations are prevented before
+ * rebooting the system.
+ */
+extern int nand_shutdown(struct mtd_info *mtd);
+
 /* The maximum number of NAND chips in an array */
 #define NAND_MAX_CHIPS		8
 
-- 
2.1.3

[PATCH v2 0/4] pwm: kona: Drivers fixes

[Scott Branden]

This patchset contains fixes for Broadcom's Kona PWM driver.

These changes fix glitch issues when changing settings on different channels.
Kconfig change made to allow the driver to work on any Broadcom SoC rather
than just mobile devices.

Arun Ramamurthy (4):
  pwm: kona: Remove setting default smooth type and polarity for all
    channels
  pwm: kona: Fix incorrect enable after channel polarity change
  pwm: kona: Fix enable, disable and config procedures
  pwm: kona: Update dependency to ARCH_BCM

 drivers/pwm/Kconfig        |   2 +-
 drivers/pwm/pwm-bcm-kona.c | 112 ++++++++++++++++++++++++++++++++-------------
 2 files changed, 81 insertions(+), 33 deletions(-)

-- 
2.1.3

[PATCH v2 1/4] pwm: kona: Remove setting default smooth type and polarity for all channels

[Scott Branden]

From: Arun Ramamurthy <arunrama@broadcom.com>

The probe routine unnecessarily sets the smooth type and polarity for
all channels. This causes the channel for the speaker to click at the same
time the backlight turns on. The smooth type and polarity should be set individually
for each channel as required and no defaults need to be set.

Signed-off-by: Arun Ramamurthy <arunrama@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/pwm/pwm-bcm-kona.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
index 02bc048..29eef9e 100644
--- a/drivers/pwm/pwm-bcm-kona.c
+++ b/drivers/pwm/pwm-bcm-kona.c
@@ -266,12 +266,9 @@ static int kona_pwmc_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	/* Set smooth mode, push/pull, and normal polarity for all channels */
-	for (chan = 0; chan < kp->chip.npwm; chan++) {
-		value |= (1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
+	/* Set push/pull for all channels */
+	for (chan = 0; chan < kp->chip.npwm; chan++)
 		value |= (1 << PWM_CONTROL_TYPE_SHIFT(chan));
-		value |= (1 << PWM_CONTROL_POLARITY_SHIFT(chan));
-	}
 
 	writel(value, kp->base + PWM_CONTROL_OFFSET);
 
-- 
2.1.3

[PATCH v2 2/4] pwm: kona: Fix incorrect enable after channel polarity change

[Scott Branden]

From: Arun Ramamurthy <arunrama@broadcom.com>

The pwm core code requires a separate call for enabling the channel
and hence the driver does not need to set pwm_trigger after a
polarity change

Signed-off-by: Arun Ramamurthy <arunrama@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/pwm/pwm-bcm-kona.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
index 29eef9e..fa0b5bf 100644
--- a/drivers/pwm/pwm-bcm-kona.c
+++ b/drivers/pwm/pwm-bcm-kona.c
@@ -173,11 +173,6 @@ static int kona_pwmc_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
 
 	writel(value, kp->base + PWM_CONTROL_OFFSET);
 
-	kona_pwmc_apply_settings(kp, chan);
-
-	/* Wait for waveform to settle before gating off the clock */
-	ndelay(400);
-
 	clk_disable_unprepare(kp->clk);
 
 	return 0;
-- 
2.1.3

[PATCH v2 3/4] pwm: kona: Fix enable, disable and config procedures

[Scott Branden]

From: Arun Ramamurthy <arunrama@broadcom.com>

- Added helper functions to set and clear smooth and trigger bits
- Added 400ns delays when clearing and setting trigger bit as requied
  by spec
- Added helper function to write prescale and other settings
- Updated config procedure to match spec
- Added code to handle pwn config when channel is disabled
- Updated disable procedure to match spec

Signed-off-by: Arun Ramamurthy <arunrama@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/pwm/pwm-bcm-kona.c | 100 +++++++++++++++++++++++++++++++++++----------
 1 file changed, 78 insertions(+), 22 deletions(-)

diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
index fa0b5bf..06fa983 100644
--- a/drivers/pwm/pwm-bcm-kona.c
+++ b/drivers/pwm/pwm-bcm-kona.c
@@ -65,6 +65,10 @@
 #define DUTY_CYCLE_HIGH_MIN			(0x00000000)
 #define DUTY_CYCLE_HIGH_MAX			(0x00ffffff)
 
+/* The delay required after clearing or setting
+   PWMOUT_ENABLE*/
+#define PWMOUT_ENABLE_HOLD_DELAY 400
+
 struct kona_pwmc {
 	struct pwm_chip chip;
 	void __iomem *base;
@@ -76,28 +80,70 @@ static inline struct kona_pwmc *to_kona_pwmc(struct pwm_chip *_chip)
 	return container_of(_chip, struct kona_pwmc, chip);
 }
 
-static void kona_pwmc_apply_settings(struct kona_pwmc *kp, unsigned int chan)
+static inline void kona_pwmc_set_trigger(struct kona_pwmc *kp,
+					 unsigned int chan)
 {
 	unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
 
-	/* Clear trigger bit but set smooth bit to maintain old output */
-	value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);
+	/* set trigger bit to enable channel */
+	value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
+	writel(value, kp->base + PWM_CONTROL_OFFSET);
+	ndelay(PWMOUT_ENABLE_HOLD_DELAY);
+}
+static inline void kona_pwmc_clear_trigger(struct kona_pwmc *kp,
+					   unsigned int chan)
+{
+	unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
+
+	/* Clear trigger bit */
 	value &= ~(1 << PWM_CONTROL_TRIGGER_SHIFT(chan));
 	writel(value, kp->base + PWM_CONTROL_OFFSET);
+	ndelay(PWMOUT_ENABLE_HOLD_DELAY);
+}
 
-	/* Set trigger bit and clear smooth bit to apply new settings */
+static inline void kona_pwmc_clear_smooth(struct kona_pwmc *kp,
+					  unsigned int chan)
+{
+	unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
+
+	/* Clear smooth bit */
 	value &= ~(1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
-	value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
 	writel(value, kp->base + PWM_CONTROL_OFFSET);
 }
 
+static inline void kona_pwmc_set_smooth(struct kona_pwmc *kp, unsigned int chan)
+{
+	unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
+
+	/*  set smooth bit to maintain old output */
+	value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);
+	writel(value, kp->base + PWM_CONTROL_OFFSET);
+}
+
+static void kona_pwmc_write_settings(struct kona_pwmc *kp, unsigned int chan,
+				     unsigned long prescale, unsigned long pc,
+				     unsigned long dc)
+{
+	unsigned int value;
+
+	value = readl(kp->base + PRESCALE_OFFSET);
+	value &= ~PRESCALE_MASK(chan);
+	value |= prescale << PRESCALE_SHIFT(chan);
+	writel(value, kp->base + PRESCALE_OFFSET);
+
+	writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
+
+	writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
+
+}
+
 static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm,
 			    int duty_ns, int period_ns)
 {
 	struct kona_pwmc *kp = to_kona_pwmc(chip);
 	u64 val, div, rate;
 	unsigned long prescale = PRESCALE_MIN, pc, dc;
-	unsigned int value, chan = pwm->hwpwm;
+	unsigned int ret, chan = pwm->hwpwm;
 
 	/*
 	 * Find period count, duty count and prescale to suit duty_ns and
@@ -133,19 +179,30 @@ static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm,
 			return -EINVAL;
 	}
 
-	/* If the PWM channel is enabled, write the settings to the HW */
-	if (test_bit(PWMF_ENABLED, &pwm->flags)) {
-		value = readl(kp->base + PRESCALE_OFFSET);
-		value &= ~PRESCALE_MASK(chan);
-		value |= prescale << PRESCALE_SHIFT(chan);
-		writel(value, kp->base + PRESCALE_OFFSET);
 
-		writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
+	/* If the PWM channel is not enabled, enable the clock */
+	if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
+		ret = clk_prepare_enable(kp->clk);
+		if (ret < 0) {
+			dev_err(chip->dev, "failed to enable clock: %d\n", ret);
+			return ret;
+		}
+	}
 
-		writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
+	/* Set smooth bit to maintain old output */
+	kona_pwmc_set_smooth(kp, chan);
+	kona_pwmc_clear_trigger(kp, chan);
+
+	/* apply new settings */
+	kona_pwmc_write_settings(kp, chan, prescale, pc, dc);
+
+	/*If the PWM is enabled, enable the channel with the new settings
+	 and if not  disable the clock*/
+	if (test_bit(PWMF_ENABLED, &pwm->flags))
+		kona_pwmc_set_trigger(kp, chan);
+	else
+		clk_disable_unprepare(kp->clk);
 
-		kona_pwmc_apply_settings(kp, chan);
-	}
 
 	return 0;
 }
@@ -188,7 +245,6 @@ static int kona_pwmc_enable(struct pwm_chip *chip, struct pwm_device *pwm)
 		dev_err(chip->dev, "failed to enable clock: %d\n", ret);
 		return ret;
 	}
-
 	ret = kona_pwmc_config(chip, pwm, pwm->duty_cycle, pwm->period);
 	if (ret < 0) {
 		clk_disable_unprepare(kp->clk);
@@ -203,12 +259,12 @@ static void kona_pwmc_disable(struct pwm_chip *chip, struct pwm_device *pwm)
 	struct kona_pwmc *kp = to_kona_pwmc(chip);
 	unsigned int chan = pwm->hwpwm;
 
+	kona_pwmc_clear_smooth(kp, chan);
+	kona_pwmc_clear_trigger(kp, chan);
 	/* Simulate a disable by configuring for zero duty */
-	writel(0, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
-	kona_pwmc_apply_settings(kp, chan);
-
-	/* Wait for waveform to settle before gating off the clock */
-	ndelay(400);
+	kona_pwmc_write_settings(kp, chan, 0, 0, 0);
+	kona_pwmc_set_polarity(chip, pwm, PWM_POLARITY_NORMAL);
+	kona_pwmc_set_trigger(kp, chan);
 
 	clk_disable_unprepare(kp->clk);
 }
-- 
2.1.3

[PATCH v2 4/4] pwm: kona: Update dependency to ARCH_BCM

[Scott Branden]

From: Arun Ramamurthy <arunrama@broadcom.com>

change kona driver depends on so to it is available for any Broadcom SoC
Signed-off-by: Arun Ramamurthy <arunrama@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/pwm/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index ef2dd2e..186080e 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -64,7 +64,7 @@ config PWM_ATMEL_TCB
 
 config PWM_BCM_KONA
 	tristate "Kona PWM support"
-	depends on ARCH_BCM_MOBILE
+	depends on ARCH_BCM
 	help
 	  Generic PWM framework driver for Broadcom Kona PWM block.
 
-- 
2.1.3

Re: [PATCH v2 1/4] pwm: kona: Remove setting default smooth type and polarity for all channels

[Tim Kryger]

On Tue, Nov 25, 2014 at 11:40 AM, Scott Branden <sbranden@broadcom.com> wrote:
> From: Arun Ramamurthy <arunrama@broadcom.com>
>
> The probe routine unnecessarily sets the smooth type and polarity for
> all channels. This causes the channel for the speaker to click at the same
> time the backlight turns on. The smooth type and polarity should be set individually
> for each channel as required and no defaults need to be set.

I am guessing you are talking about a PWM controlled beeper/buzzer.

Can you mention what board you are observing this issue on?

Also please explain why setting these bits result in an audible click.

>
> Signed-off-by: Arun Ramamurthy <arunrama@broadcom.com>
> Reviewed-by: Ray Jui <rjui@broadcom.com>
> Signed-off-by: Scott Branden <sbranden@broadcom.com>
> ---
>  drivers/pwm/pwm-bcm-kona.c | 7 ++-----
>  1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
> index 02bc048..29eef9e 100644
> --- a/drivers/pwm/pwm-bcm-kona.c
> +++ b/drivers/pwm/pwm-bcm-kona.c
> @@ -266,12 +266,9 @@ static int kona_pwmc_probe(struct platform_device *pdev)
>                 return ret;
>         }
>
> -       /* Set smooth mode, push/pull, and normal polarity for all channels */
> -       for (chan = 0; chan < kp->chip.npwm; chan++) {
> -               value |= (1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
> +       /* Set push/pull for all channels */
> +       for (chan = 0; chan < kp->chip.npwm; chan++)
>                 value |= (1 << PWM_CONTROL_TYPE_SHIFT(chan));
> -               value |= (1 << PWM_CONTROL_POLARITY_SHIFT(chan));
> -       }
>
>         writel(value, kp->base + PWM_CONTROL_OFFSET);

While the smooth bit need not be set here, it is important that the
polarity bit be set.

Otherwise software will report the polarity as normal when it it is
actually inversed.

Consider the case where a userspace process is controlling the PWM via sysfs.

Re: [PATCH v2 2/4] pwm: kona: Fix incorrect enable after channel polarity change

[Tim Kryger]

On Tue, Nov 25, 2014 at 11:40 AM, Scott Branden <sbranden@broadcom.com> wrote:
> From: Arun Ramamurthy <arunrama@broadcom.com>
>
> The pwm core code requires a separate call for enabling the channel
> and hence the driver does not need to set pwm_trigger after a
> polarity change

The framework does restrict when polarity changes can occur but it
isn't clear to me that there is any reason to delay applying the
polarity change.  Keep in mind that polarity matters even when a PWM
is disabled.  While disabled, the output should be equivalent to an
enabled configuration with zero duty.  Thus for normal polarity the
output is constant low and for inversed polarity the output is
constant high. I believe there is an expectation that the output is
updated to reflect the requested polarity change prior to returning to
the caller.

>
> Signed-off-by: Arun Ramamurthy <arunrama@broadcom.com>
> Reviewed-by: Ray Jui <rjui@broadcom.com>
> Signed-off-by: Scott Branden <sbranden@broadcom.com>
> ---
>  drivers/pwm/pwm-bcm-kona.c | 5 -----
>  1 file changed, 5 deletions(-)
>
> diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
> index 29eef9e..fa0b5bf 100644
> --- a/drivers/pwm/pwm-bcm-kona.c
> +++ b/drivers/pwm/pwm-bcm-kona.c
> @@ -173,11 +173,6 @@ static int kona_pwmc_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
>
>         writel(value, kp->base + PWM_CONTROL_OFFSET);
>
> -       kona_pwmc_apply_settings(kp, chan);
> -
> -       /* Wait for waveform to settle before gating off the clock */
> -       ndelay(400);
> -
>         clk_disable_unprepare(kp->clk);
>
>         return 0;
> --
> 2.1.3
>

Re: [PATCH v2 3/4] pwm: kona: Fix enable, disable and config procedures

[Tim Kryger]

On Tue, Nov 25, 2014 at 11:40 AM, Scott Branden <sbranden@broadcom.com> wrote:
> From: Arun Ramamurthy <arunrama@broadcom.com>
>
> - Added helper functions to set and clear smooth and trigger bits
> - Added 400ns delays when clearing and setting trigger bit as requied
>   by spec
> - Added helper function to write prescale and other settings
> - Updated config procedure to match spec
> - Added code to handle pwn config when channel is disabled
> - Updated disable procedure to match spec
>
> Signed-off-by: Arun Ramamurthy <arunrama@broadcom.com>
> Reviewed-by: Ray Jui <rjui@broadcom.com>
> Signed-off-by: Scott Branden <sbranden@broadcom.com>
> ---
>  drivers/pwm/pwm-bcm-kona.c | 100 +++++++++++++++++++++++++++++++++++----------
>  1 file changed, 78 insertions(+), 22 deletions(-)

The driver is fairly small and this change rewrites a considerable amount of it.

Is there a actually specific deficiency that this change is intended to address?

I'm not sure all the extra helper functions improve readability.

>
> diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
> index fa0b5bf..06fa983 100644
> --- a/drivers/pwm/pwm-bcm-kona.c
> +++ b/drivers/pwm/pwm-bcm-kona.c
> @@ -65,6 +65,10 @@
>  #define DUTY_CYCLE_HIGH_MIN                    (0x00000000)
>  #define DUTY_CYCLE_HIGH_MAX                    (0x00ffffff)
>
> +/* The delay required after clearing or setting
> +   PWMOUT_ENABLE*/
> +#define PWMOUT_ENABLE_HOLD_DELAY 400
> +
>  struct kona_pwmc {
>         struct pwm_chip chip;
>         void __iomem *base;
> @@ -76,28 +80,70 @@ static inline struct kona_pwmc *to_kona_pwmc(struct pwm_chip *_chip)
>         return container_of(_chip, struct kona_pwmc, chip);
>  }
>
> -static void kona_pwmc_apply_settings(struct kona_pwmc *kp, unsigned int chan)
> +static inline void kona_pwmc_set_trigger(struct kona_pwmc *kp,
> +                                        unsigned int chan)
>  {
>         unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
>
> -       /* Clear trigger bit but set smooth bit to maintain old output */
> -       value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);
> +       /* set trigger bit to enable channel */
> +       value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
> +       writel(value, kp->base + PWM_CONTROL_OFFSET);
> +       ndelay(PWMOUT_ENABLE_HOLD_DELAY);
> +}
> +static inline void kona_pwmc_clear_trigger(struct kona_pwmc *kp,
> +                                          unsigned int chan)
> +{
> +       unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
> +
> +       /* Clear trigger bit */
>         value &= ~(1 << PWM_CONTROL_TRIGGER_SHIFT(chan));
>         writel(value, kp->base + PWM_CONTROL_OFFSET);
> +       ndelay(PWMOUT_ENABLE_HOLD_DELAY);
> +}
>
> -       /* Set trigger bit and clear smooth bit to apply new settings */
> +static inline void kona_pwmc_clear_smooth(struct kona_pwmc *kp,
> +                                         unsigned int chan)
> +{
> +       unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
> +
> +       /* Clear smooth bit */
>         value &= ~(1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
> -       value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
>         writel(value, kp->base + PWM_CONTROL_OFFSET);
>  }
>
> +static inline void kona_pwmc_set_smooth(struct kona_pwmc *kp, unsigned int chan)
> +{
> +       unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
> +
> +       /*  set smooth bit to maintain old output */
> +       value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);
> +       writel(value, kp->base + PWM_CONTROL_OFFSET);
> +}
> +
> +static void kona_pwmc_write_settings(struct kona_pwmc *kp, unsigned int chan,
> +                                    unsigned long prescale, unsigned long pc,
> +                                    unsigned long dc)
> +{
> +       unsigned int value;
> +
> +       value = readl(kp->base + PRESCALE_OFFSET);
> +       value &= ~PRESCALE_MASK(chan);
> +       value |= prescale << PRESCALE_SHIFT(chan);
> +       writel(value, kp->base + PRESCALE_OFFSET);
> +
> +       writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
> +
> +       writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
> +
> +}
> +
>  static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm,
>                             int duty_ns, int period_ns)
>  {
>         struct kona_pwmc *kp = to_kona_pwmc(chip);
>         u64 val, div, rate;
>         unsigned long prescale = PRESCALE_MIN, pc, dc;
> -       unsigned int value, chan = pwm->hwpwm;
> +       unsigned int ret, chan = pwm->hwpwm;
>
>         /*
>          * Find period count, duty count and prescale to suit duty_ns and
> @@ -133,19 +179,30 @@ static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm,
>                         return -EINVAL;
>         }
>
> -       /* If the PWM channel is enabled, write the settings to the HW */
> -       if (test_bit(PWMF_ENABLED, &pwm->flags)) {
> -               value = readl(kp->base + PRESCALE_OFFSET);
> -               value &= ~PRESCALE_MASK(chan);
> -               value |= prescale << PRESCALE_SHIFT(chan);
> -               writel(value, kp->base + PRESCALE_OFFSET);
>
> -               writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
> +       /* If the PWM channel is not enabled, enable the clock */
> +       if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
> +               ret = clk_prepare_enable(kp->clk);
> +               if (ret < 0) {
> +                       dev_err(chip->dev, "failed to enable clock: %d\n", ret);
> +                       return ret;
> +               }
> +       }
>
> -               writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
> +       /* Set smooth bit to maintain old output */
> +       kona_pwmc_set_smooth(kp, chan);
> +       kona_pwmc_clear_trigger(kp, chan);
> +
> +       /* apply new settings */
> +       kona_pwmc_write_settings(kp, chan, prescale, pc, dc);
> +
> +       /*If the PWM is enabled, enable the channel with the new settings
> +        and if not  disable the clock*/
> +       if (test_bit(PWMF_ENABLED, &pwm->flags))
> +               kona_pwmc_set_trigger(kp, chan);
> +       else
> +               clk_disable_unprepare(kp->clk);
>
> -               kona_pwmc_apply_settings(kp, chan);
> -       }
>
>         return 0;
>  }
> @@ -188,7 +245,6 @@ static int kona_pwmc_enable(struct pwm_chip *chip, struct pwm_device *pwm)
>                 dev_err(chip->dev, "failed to enable clock: %d\n", ret);
>                 return ret;
>         }
> -
>         ret = kona_pwmc_config(chip, pwm, pwm->duty_cycle, pwm->period);
>         if (ret < 0) {
>                 clk_disable_unprepare(kp->clk);
> @@ -203,12 +259,12 @@ static void kona_pwmc_disable(struct pwm_chip *chip, struct pwm_device *pwm)
>         struct kona_pwmc *kp = to_kona_pwmc(chip);
>         unsigned int chan = pwm->hwpwm;
>
> +       kona_pwmc_clear_smooth(kp, chan);
> +       kona_pwmc_clear_trigger(kp, chan);

I believe the output will spike high here.  Likely not what you want...

>         /* Simulate a disable by configuring for zero duty */
> -       writel(0, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
> -       kona_pwmc_apply_settings(kp, chan);
> -
> -       /* Wait for waveform to settle before gating off the clock */
> -       ndelay(400);
> +       kona_pwmc_write_settings(kp, chan, 0, 0, 0);
> +       kona_pwmc_set_polarity(chip, pwm, PWM_POLARITY_NORMAL);

This is wrong.  You shouldn't change the polarity when the PWM is disabled.

The original polarity isn't even restored when it is re-enabled...

> +       kona_pwmc_set_trigger(kp, chan);
>
>         clk_disable_unprepare(kp->clk);
>  }
> --
> 2.1.3
>

Re: [PATCH] mtd: nand: added nand_shutdown

[Brian Norris]

On Thu, Nov 20, 2014 at 11:18:05AM -0800, Scott Branden wrote:
> Add nand_shutdown to wait for current nand operations to finish and prevent
> further operations by changing the nand flash state to FL_SHUTDOWN.
> 
> This is addressing a problem observed during reboot tests using UBIFS
> root file system: NAND erase operations that are in progress during
> system reboot/shutdown are causing partial erased blocks. Although UBI should
> be able to detect and recover from this error, this change will avoid
> the creation of partial erased blocks on reboot in the middle of a NAND erase
> operation.
[...]
> diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
> index e4d451e..80e4367 100644
> --- a/include/linux/mtd/nand.h
> +++ b/include/linux/mtd/nand.h
> @@ -48,6 +48,13 @@ extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
>  /* unlocks specified locked blocks */
>  extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
>  
> +/*
> + * Internal helper for board drivers which need to make sure that the current
> + * nand operation is finished and further operations are prevented before
> + * rebooting the system.
> + */
> +extern int nand_shutdown(struct mtd_info *mtd);

I don't think we should push this out to the board drivers. And I
definitely don't want to merge this function without any user. It'd turn
out like our useless nand_lock() and nand_unlock() functions.

> +
>  /* The maximum number of NAND chips in an array */
>  #define NAND_MAX_CHIPS		8
>  

So, to do this right, I think maybe we should add an (optional)
reboot_notifier field to struct mtd_info, and use it to register a
system reboot notifier on behalf of the lower layers. We can do the
registration in mtd_device_parse_register(), I think, and any
unregistration in mtd_device_unregister().

With this approach, we can actually move the cfi_cmdset_000{1,2}.c
reboot notifiers over to the same common code. They just will have to
fill out their mtd->reboot_notifier field.

How about the following two untested patches?

From: Brian Norris <computersforpeace@gmail.com>

cfi_cmdset_000{1,2}.c already implement their own reboot notifiers, and
we're going to add one for NAND. Let's put the boilerplate in one place.

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
---
 drivers/mtd/mtdcore.c   | 20 ++++++++++++++++++++
 include/linux/mtd/mtd.h |  1 +
 2 files changed, 21 insertions(+)

diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c
index 4c611871d7e6..b80d44f9751d 100644
--- a/drivers/mtd/mtdcore.c
+++ b/drivers/mtd/mtdcore.c
@@ -37,6 +37,7 @@
 #include <linux/backing-dev.h>
 #include <linux/gfp.h>
 #include <linux/slab.h>
+#include <linux/reboot.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
@@ -365,6 +366,17 @@ static struct device_type mtd_devtype = {
 	.release	= mtd_release,
 };
 
+static int mtd_reboot_notifier(struct notifier_block *n, unsigned long state,
+			       void *cmd)
+{
+       struct mtd_info *mtd;
+
+       mtd = container_of(n, struct mtd_info, reboot_notifier);
+       mtd->_reboot(mtd);
+
+       return NOTIFY_DONE;
+}
+
 /**
  *	add_mtd_device - register an MTD device
  *	@mtd: pointer to new MTD device info structure
@@ -565,6 +577,11 @@ int mtd_device_parse_register(struct mtd_info *mtd, const char * const *types,
 			err = -ENODEV;
 	}
 
+	if (mtd->_reboot) {
+		mtd->reboot_notifier.notifier_call = mtd_reboot_notifier;
+		register_reboot_notifier(&mtd->reboot_notifier);
+	}
+
 	return err;
 }
 EXPORT_SYMBOL_GPL(mtd_device_parse_register);
@@ -579,6 +596,9 @@ int mtd_device_unregister(struct mtd_info *master)
 {
 	int err;
 
+	if (master->_reboot)
+		unregister_reboot_notifier(&master->reboot_notifier);
+
 	err = del_mtd_partitions(master);
 	if (err)
 		return err;
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 031ff3a9a0bd..c06f5373d870 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -227,6 +227,7 @@ struct mtd_info {
 	int (*_block_markbad) (struct mtd_info *mtd, loff_t ofs);
 	int (*_suspend) (struct mtd_info *mtd);
 	void (*_resume) (struct mtd_info *mtd);
+	void (*_reboot) (struct mtd_info *mtd);
 	/*
 	 * If the driver is something smart, like UBI, it may need to maintain
 	 * its own reference counting. The below functions are only for driver.
-- 


From: Scott Branden <sbranden@broadcom.com>

Add nand_shutdown to wait for current nand operations to finish and prevent
further operations by changing the nand flash state to FL_SHUTDOWN.

This is addressing a problem observed during reboot tests using UBIFS
root file system: NAND erase operations that are in progress during
system reboot/shutdown are causing partial erased blocks. Although UBI should
be able to detect and recover from this error, this change will avoid
the creation of partial erased blocks on reboot in the middle of a NAND erase
operation.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
---
 drivers/mtd/nand/nand_base.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 4cbd14552d48..06ae96834063 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2944,6 +2944,16 @@ static void nand_resume(struct mtd_info *mtd)
 			__func__);
 }
 
+/**
+ * nand_shutdown - [MTD Interface] Finish the current NAND operation and
+ *                 prevent further operations
+ * @mtd: MTD device structure
+ */
+static int nand_shutdown(struct mtd_info *mtd)
+{
+	return nand_get_device(mtd, FL_SHUTDOWN);
+}
+
 /* Set default functions */
 static void nand_set_defaults(struct nand_chip *chip, int busw)
 {
@@ -4146,6 +4156,7 @@ int nand_scan_tail(struct mtd_info *mtd)
 	mtd->_unlock = NULL;
 	mtd->_suspend = nand_suspend;
 	mtd->_resume = nand_resume;
+	mtd->_reboot = nand_shutdown;
 	mtd->_block_isreserved = nand_block_isreserved;
 	mtd->_block_isbad = nand_block_isbad;
 	mtd->_block_markbad = nand_block_markbad;
-- 

Re: [PATCH] mtd: nand: added nand_shutdown

[Scott Branden]

On 14-11-26 01:10 AM, Brian Norris wrote:
> On Thu, Nov 20, 2014 at 11:18:05AM -0800, Scott Branden wrote:
>> Add nand_shutdown to wait for current nand operations to finish and prevent
>> further operations by changing the nand flash state to FL_SHUTDOWN.
>>
>> This is addressing a problem observed during reboot tests using UBIFS
>> root file system: NAND erase operations that are in progress during
>> system reboot/shutdown are causing partial erased blocks. Although UBI should
>> be able to detect and recover from this error, this change will avoid
>> the creation of partial erased blocks on reboot in the middle of a NAND erase
>> operation.
> [...]
>> diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
>> index e4d451e..80e4367 100644
>> --- a/include/linux/mtd/nand.h
>> +++ b/include/linux/mtd/nand.h
>> @@ -48,6 +48,13 @@ extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
>>   /* unlocks specified locked blocks */
>>   extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
>>
>> +/*
>> + * Internal helper for board drivers which need to make sure that the current
>> + * nand operation is finished and further operations are prevented before
>> + * rebooting the system.
>> + */
>> +extern int nand_shutdown(struct mtd_info *mtd);
>
> I don't think we should push this out to the board drivers. And I
> definitely don't want to merge this function without any user. It'd turn
> out like our useless nand_lock() and nand_unlock() functions.
>
>> +
>>   /* The maximum number of NAND chips in an array */
>>   #define NAND_MAX_CHIPS		8
>>
>
> So, to do this right, I think maybe we should add an (optional)
> reboot_notifier field to struct mtd_info, and use it to register a
> system reboot notifier on behalf of the lower layers. We can do the
> registration in mtd_device_parse_register(), I think, and any
> unregistration in mtd_device_unregister().
>
> With this approach, we can actually move the cfi_cmdset_000{1,2}.c
> reboot notifiers over to the same common code. They just will have to
> fill out their mtd->reboot_notifier field.
>
> How about the following two untested patches?

This is great if we can move this to common code as it should be done 
for all NAND (and NOR) devices.  For nand, I suggest we install a 
reboot_notifier in a common location like nand_base rather than each 
driver.  If a particular driver wishes to override this they are free to 
do so in their particular driver?

>
> From: Brian Norris <computersforpeace@gmail.com>
>
> cfi_cmdset_000{1,2}.c already implement their own reboot notifiers, and
> we're going to add one for NAND. Let's put the boilerplate in one place.
>
> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
> ---
>   drivers/mtd/mtdcore.c   | 20 ++++++++++++++++++++
>   include/linux/mtd/mtd.h |  1 +
>   2 files changed, 21 insertions(+)
>
> diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c
> index 4c611871d7e6..b80d44f9751d 100644
> --- a/drivers/mtd/mtdcore.c
> +++ b/drivers/mtd/mtdcore.c
> @@ -37,6 +37,7 @@
>   #include <linux/backing-dev.h>
>   #include <linux/gfp.h>
>   #include <linux/slab.h>
> +#include <linux/reboot.h>
>
>   #include <linux/mtd/mtd.h>
>   #include <linux/mtd/partitions.h>
> @@ -365,6 +366,17 @@ static struct device_type mtd_devtype = {
>   	.release	= mtd_release,
>   };
>
> +static int mtd_reboot_notifier(struct notifier_block *n, unsigned long state,
> +			       void *cmd)
> +{
> +       struct mtd_info *mtd;
> +
> +       mtd = container_of(n, struct mtd_info, reboot_notifier);
> +       mtd->_reboot(mtd);
> +
> +       return NOTIFY_DONE;
> +}
> +
>   /**
>    *	add_mtd_device - register an MTD device
>    *	@mtd: pointer to new MTD device info structure
> @@ -565,6 +577,11 @@ int mtd_device_parse_register(struct mtd_info *mtd, const char * const *types,
>   			err = -ENODEV;
>   	}
>
> +	if (mtd->_reboot) {
> +		mtd->reboot_notifier.notifier_call = mtd_reboot_notifier;
> +		register_reboot_notifier(&mtd->reboot_notifier);
> +	}
> +
>   	return err;
>   }
>   EXPORT_SYMBOL_GPL(mtd_device_parse_register);
> @@ -579,6 +596,9 @@ int mtd_device_unregister(struct mtd_info *master)
>   {
>   	int err;
>
> +	if (master->_reboot)
> +		unregister_reboot_notifier(&master->reboot_notifier);
> +
>   	err = del_mtd_partitions(master);
>   	if (err)
>   		return err;
> diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
> index 031ff3a9a0bd..c06f5373d870 100644
> --- a/include/linux/mtd/mtd.h
> +++ b/include/linux/mtd/mtd.h
> @@ -227,6 +227,7 @@ struct mtd_info {
>   	int (*_block_markbad) (struct mtd_info *mtd, loff_t ofs);
>   	int (*_suspend) (struct mtd_info *mtd);
>   	void (*_resume) (struct mtd_info *mtd);
> +	void (*_reboot) (struct mtd_info *mtd);
>   	/*
>   	 * If the driver is something smart, like UBI, it may need to maintain
>   	 * its own reference counting. The below functions are only for driver.
>

Re: [PATCH v2 3/4] pwm: kona: Fix enable, disable and config procedures

[Scott Branden]

Hi Tim,

Thanks for all your comments on the patchset.  We are in the process of 
reviewing and will provide feedback when that is completed.

Scott

On 14-11-25 11:29 PM, Tim Kryger wrote:
> On Tue, Nov 25, 2014 at 11:40 AM, Scott Branden <sbranden@broadcom.com> wrote:
>> From: Arun Ramamurthy <arunrama@broadcom.com>
>>
>> - Added helper functions to set and clear smooth and trigger bits
>> - Added 400ns delays when clearing and setting trigger bit as requied
>>    by spec
>> - Added helper function to write prescale and other settings
>> - Updated config procedure to match spec
>> - Added code to handle pwn config when channel is disabled
>> - Updated disable procedure to match spec
>>
>> Signed-off-by: Arun Ramamurthy <arunrama@broadcom.com>
>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>> ---
>>   drivers/pwm/pwm-bcm-kona.c | 100 +++++++++++++++++++++++++++++++++++----------
>>   1 file changed, 78 insertions(+), 22 deletions(-)
>
> The driver is fairly small and this change rewrites a considerable amount of it.
>
> Is there a actually specific deficiency that this change is intended to address?
>
> I'm not sure all the extra helper functions improve readability.
>
>>
>> diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
>> index fa0b5bf..06fa983 100644
>> --- a/drivers/pwm/pwm-bcm-kona.c
>> +++ b/drivers/pwm/pwm-bcm-kona.c
>> @@ -65,6 +65,10 @@
>>   #define DUTY_CYCLE_HIGH_MIN                    (0x00000000)
>>   #define DUTY_CYCLE_HIGH_MAX                    (0x00ffffff)
>>
>> +/* The delay required after clearing or setting
>> +   PWMOUT_ENABLE*/
>> +#define PWMOUT_ENABLE_HOLD_DELAY 400
>> +
>>   struct kona_pwmc {
>>          struct pwm_chip chip;
>>          void __iomem *base;
>> @@ -76,28 +80,70 @@ static inline struct kona_pwmc *to_kona_pwmc(struct pwm_chip *_chip)
>>          return container_of(_chip, struct kona_pwmc, chip);
>>   }
>>
>> -static void kona_pwmc_apply_settings(struct kona_pwmc *kp, unsigned int chan)
>> +static inline void kona_pwmc_set_trigger(struct kona_pwmc *kp,
>> +                                        unsigned int chan)
>>   {
>>          unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
>>
>> -       /* Clear trigger bit but set smooth bit to maintain old output */
>> -       value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);
>> +       /* set trigger bit to enable channel */
>> +       value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
>> +       writel(value, kp->base + PWM_CONTROL_OFFSET);
>> +       ndelay(PWMOUT_ENABLE_HOLD_DELAY);
>> +}
>> +static inline void kona_pwmc_clear_trigger(struct kona_pwmc *kp,
>> +                                          unsigned int chan)
>> +{
>> +       unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
>> +
>> +       /* Clear trigger bit */
>>          value &= ~(1 << PWM_CONTROL_TRIGGER_SHIFT(chan));
>>          writel(value, kp->base + PWM_CONTROL_OFFSET);
>> +       ndelay(PWMOUT_ENABLE_HOLD_DELAY);
>> +}
>>
>> -       /* Set trigger bit and clear smooth bit to apply new settings */
>> +static inline void kona_pwmc_clear_smooth(struct kona_pwmc *kp,
>> +                                         unsigned int chan)
>> +{
>> +       unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
>> +
>> +       /* Clear smooth bit */
>>          value &= ~(1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
>> -       value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
>>          writel(value, kp->base + PWM_CONTROL_OFFSET);
>>   }
>>
>> +static inline void kona_pwmc_set_smooth(struct kona_pwmc *kp, unsigned int chan)
>> +{
>> +       unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
>> +
>> +       /*  set smooth bit to maintain old output */
>> +       value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);
>> +       writel(value, kp->base + PWM_CONTROL_OFFSET);
>> +}
>> +
>> +static void kona_pwmc_write_settings(struct kona_pwmc *kp, unsigned int chan,
>> +                                    unsigned long prescale, unsigned long pc,
>> +                                    unsigned long dc)
>> +{
>> +       unsigned int value;
>> +
>> +       value = readl(kp->base + PRESCALE_OFFSET);
>> +       value &= ~PRESCALE_MASK(chan);
>> +       value |= prescale << PRESCALE_SHIFT(chan);
>> +       writel(value, kp->base + PRESCALE_OFFSET);
>> +
>> +       writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
>> +
>> +       writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
>> +
>> +}
>> +
>>   static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm,
>>                              int duty_ns, int period_ns)
>>   {
>>          struct kona_pwmc *kp = to_kona_pwmc(chip);
>>          u64 val, div, rate;
>>          unsigned long prescale = PRESCALE_MIN, pc, dc;
>> -       unsigned int value, chan = pwm->hwpwm;
>> +       unsigned int ret, chan = pwm->hwpwm;
>>
>>          /*
>>           * Find period count, duty count and prescale to suit duty_ns and
>> @@ -133,19 +179,30 @@ static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm,
>>                          return -EINVAL;
>>          }
>>
>> -       /* If the PWM channel is enabled, write the settings to the HW */
>> -       if (test_bit(PWMF_ENABLED, &pwm->flags)) {
>> -               value = readl(kp->base + PRESCALE_OFFSET);
>> -               value &= ~PRESCALE_MASK(chan);
>> -               value |= prescale << PRESCALE_SHIFT(chan);
>> -               writel(value, kp->base + PRESCALE_OFFSET);
>>
>> -               writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
>> +       /* If the PWM channel is not enabled, enable the clock */
>> +       if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
>> +               ret = clk_prepare_enable(kp->clk);
>> +               if (ret < 0) {
>> +                       dev_err(chip->dev, "failed to enable clock: %d\n", ret);
>> +                       return ret;
>> +               }
>> +       }
>>
>> -               writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
>> +       /* Set smooth bit to maintain old output */
>> +       kona_pwmc_set_smooth(kp, chan);
>> +       kona_pwmc_clear_trigger(kp, chan);
>> +
>> +       /* apply new settings */
>> +       kona_pwmc_write_settings(kp, chan, prescale, pc, dc);
>> +
>> +       /*If the PWM is enabled, enable the channel with the new settings
>> +        and if not  disable the clock*/
>> +       if (test_bit(PWMF_ENABLED, &pwm->flags))
>> +               kona_pwmc_set_trigger(kp, chan);
>> +       else
>> +               clk_disable_unprepare(kp->clk);
>>
>> -               kona_pwmc_apply_settings(kp, chan);
>> -       }
>>
>>          return 0;
>>   }
>> @@ -188,7 +245,6 @@ static int kona_pwmc_enable(struct pwm_chip *chip, struct pwm_device *pwm)
>>                  dev_err(chip->dev, "failed to enable clock: %d\n", ret);
>>                  return ret;
>>          }
>> -
>>          ret = kona_pwmc_config(chip, pwm, pwm->duty_cycle, pwm->period);
>>          if (ret < 0) {
>>                  clk_disable_unprepare(kp->clk);
>> @@ -203,12 +259,12 @@ static void kona_pwmc_disable(struct pwm_chip *chip, struct pwm_device *pwm)
>>          struct kona_pwmc *kp = to_kona_pwmc(chip);
>>          unsigned int chan = pwm->hwpwm;
>>
>> +       kona_pwmc_clear_smooth(kp, chan);
>> +       kona_pwmc_clear_trigger(kp, chan);
>
> I believe the output will spike high here.  Likely not what you want...
>
>>          /* Simulate a disable by configuring for zero duty */
>> -       writel(0, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
>> -       kona_pwmc_apply_settings(kp, chan);
>> -
>> -       /* Wait for waveform to settle before gating off the clock */
>> -       ndelay(400);
>> +       kona_pwmc_write_settings(kp, chan, 0, 0, 0);
>> +       kona_pwmc_set_polarity(chip, pwm, PWM_POLARITY_NORMAL);
>
> This is wrong.  You shouldn't change the polarity when the PWM is disabled.
>
> The original polarity isn't even restored when it is re-enabled...
>
>> +       kona_pwmc_set_trigger(kp, chan);
>>
>>          clk_disable_unprepare(kp->clk);
>>   }
>> --
>> 2.1.3
>>

Re: [PATCH] mtd: nand: added nand_shutdown

[Scott Branden]

On 14-11-26 01:10 AM, Brian Norris wrote:
> +	mtd->_reboot = nand_shutdown;
Ah, I see you added this here.  This is great.  We'll try out your 
patchset on our driver and remove the reboot notifier from it.

Re: [PATCH v2 1/4] pwm: kona: Remove setting default smooth type and polarity for all channels

[Arun Ramamurthy]

On 14-11-25 09:51 PM, Tim Kryger wrote:
> On Tue, Nov 25, 2014 at 11:40 AM, Scott Branden <sbranden@broadcom.com> wrote:
>> From: Arun Ramamurthy <arunrama@broadcom.com>
>>
>> The probe routine unnecessarily sets the smooth type and polarity for
>> all channels. This causes the channel for the speaker to click at the same
>> time the backlight turns on. The smooth type and polarity should be set individually
>> for each channel as required and no defaults need to be set.
>
> I am guessing you are talking about a PWM controlled beeper/buzzer.
>
This change is more so to remove setting smooth type and polarity for 
all channels during probe and to leave them as their default values. 
Infact, setting the PWM_CONTROL_TYPE_SHIT is also redundant cause the 
default value is already 1 for all channels. We can remove that loop 
entirely and this will be done in the next patch set. The smooth type 
and polarity are only changed when the particular pwm channel is enabled 
or polarity is changed.

> Can you mention what board you are observing this issue on?
>
> Also please explain why setting these bits result in an audible click.
>
We observe this on the bcm958300K board where one of the
PWM channels is connected to the buzzer and changing the
smooth type and polarity from its default values causes a click

>>
>> Signed-off-by: Arun Ramamurthy <arunrama@broadcom.com>
>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>> ---
>>   drivers/pwm/pwm-bcm-kona.c | 7 ++-----
>>   1 file changed, 2 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
>> index 02bc048..29eef9e 100644
>> --- a/drivers/pwm/pwm-bcm-kona.c
>> +++ b/drivers/pwm/pwm-bcm-kona.c
>> @@ -266,12 +266,9 @@ static int kona_pwmc_probe(struct platform_device *pdev)
>>                  return ret;
>>          }
>>
>> -       /* Set smooth mode, push/pull, and normal polarity for all channels */
>> -       for (chan = 0; chan < kp->chip.npwm; chan++) {
>> -               value |= (1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
>> +       /* Set push/pull for all channels */
>> +       for (chan = 0; chan < kp->chip.npwm; chan++)
>>                  value |= (1 << PWM_CONTROL_TYPE_SHIFT(chan));
>> -               value |= (1 << PWM_CONTROL_POLARITY_SHIFT(chan));
>> -       }
>>
>>          writel(value, kp->base + PWM_CONTROL_OFFSET);
>
> While the smooth bit need not be set here, it is important that the
> polarity bit be set.
>
The default value for polarity is 0 which is normal polarity, so setting 
it to 1 here in the probe function without a sysfs call is
when the software will report the polarity as normal when it is actually 
inversed.
> Otherwise software will report the polarity as normal when it it is
> actually inversed.
>
> Consider the case where a userspace process is controlling the PWM via sysfs.
>
I agree with you about the sysfs case Tim, but since this is the probe 
function and not a sysfs callback, should we not leave it as the default 
value?

Re: [PATCH v2 2/4] pwm: kona: Fix incorrect enable after channel polarity change

[Arun Ramamurthy]

On 14-11-25 10:22 PM, Tim Kryger wrote:
> On Tue, Nov 25, 2014 at 11:40 AM, Scott Branden <sbranden@broadcom.com> wrote:
>> From: Arun Ramamurthy <arunrama@broadcom.com>
>>
>> The pwm core code requires a separate call for enabling the channel
>> and hence the driver does not need to set pwm_trigger after a
>> polarity change
>
> The framework does restrict when polarity changes can occur but it
> isn't clear to me that there is any reason to delay applying the
> polarity change.
I examined several other drivers such as pwm-atmel-tcb.c, pwm-ep93xx.c, 
pwm-renesas-tpu.c, pwm-samsung.c in the 3.17 kernel tree and none of 
them enable the channel after changing polarity. We would be the first 
driver to do so.

> Keep in mind that polarity matters even when a PWM
> is disabled.  While disabled, the output should be equivalent to an
> enabled configuration with zero duty.  Thus for normal polarity the
> output is constant low and for inversed polarity the output is
> constant high.
The driver does set the duty cycle to zero when disabling the pwm 
channel.However since the frame work prevents polarity change when the 
pwm is enabled, I don’t see how one could expect the polarity change to 
be reflected immediately without a separate call to pwm enable.


I believe there is an expectation that the output is
> updated to reflect the requested polarity change prior to returning to
> the caller.

Once again I disagree with this based on other pwm drivers which only 
change the polarity and do not enable the channel when their set 
polarity functions are called.

>
>>
>> Signed-off-by: Arun Ramamurthy <arunrama@broadcom.com>
>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>> ---
>>   drivers/pwm/pwm-bcm-kona.c | 5 -----
>>   1 file changed, 5 deletions(-)
>>
>> diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
>> index 29eef9e..fa0b5bf 100644
>> --- a/drivers/pwm/pwm-bcm-kona.c
>> +++ b/drivers/pwm/pwm-bcm-kona.c
>> @@ -173,11 +173,6 @@ static int kona_pwmc_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
>>
>>          writel(value, kp->base + PWM_CONTROL_OFFSET);
>>
>> -       kona_pwmc_apply_settings(kp, chan);
>> -
>> -       /* Wait for waveform to settle before gating off the clock */
>> -       ndelay(400);
>> -
>>          clk_disable_unprepare(kp->clk);
>>
>>          return 0;
>> --
>> 2.1.3
>>

Re: [PATCH v2 3/4] pwm: kona: Fix enable, disable and config procedures

[Arun Ramamurthy]

On 14-11-25 11:29 PM, Tim Kryger wrote:
> On Tue, Nov 25, 2014 at 11:40 AM, Scott Branden <sbranden@broadcom.com> wrote:
>> From: Arun Ramamurthy <arunrama@broadcom.com>
>>
>> - Added helper functions to set and clear smooth and trigger bits
>> - Added 400ns delays when clearing and setting trigger bit as requied
>>    by spec
>> - Added helper function to write prescale and other settings
>> - Updated config procedure to match spec
>> - Added code to handle pwn config when channel is disabled
>> - Updated disable procedure to match spec
>>
>> Signed-off-by: Arun Ramamurthy <arunrama@broadcom.com>
>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>> ---
>>   drivers/pwm/pwm-bcm-kona.c | 100 +++++++++++++++++++++++++++++++++++----------
>>   1 file changed, 78 insertions(+), 22 deletions(-)
>
> The driver is fairly small and this change rewrites a considerable amount of it.
>
> Is there a actually specific deficiency that this change is intended to address?
>
The main issue this patchset addresses is setting the period and duty 
cycle when the pwm is disabled. This is done by turning on the clock and 
writing to the PWM registers. Additionally it also adds the 400ns
delays specified by the PWM spec when setting or clearing certain bits. 
It also updates the PWM programming procedure to match the spec more 
closely. Although there is considerable change, all of it addresses the 
core functionality and it would not make sense to split it into multiple 
patches.

> I'm not sure all the extra helper functions improve readability.
>
There was a lot of repeated code in various different functions. It 
seemed more efficient to consolidate them into helper functions. It also 
helped when comparing the spec to the code to check if we were
setting the bits in the right order.

>>
>> diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
>> index fa0b5bf..06fa983 100644
>> --- a/drivers/pwm/pwm-bcm-kona.c
>> +++ b/drivers/pwm/pwm-bcm-kona.c
>> @@ -65,6 +65,10 @@
>>   #define DUTY_CYCLE_HIGH_MIN                    (0x00000000)
>>   #define DUTY_CYCLE_HIGH_MAX                    (0x00ffffff)
>>
>> +/* The delay required after clearing or setting
>> +   PWMOUT_ENABLE*/
>> +#define PWMOUT_ENABLE_HOLD_DELAY 400
>> +
>>   struct kona_pwmc {
>>          struct pwm_chip chip;
>>          void __iomem *base;
>> @@ -76,28 +80,70 @@ static inline struct kona_pwmc *to_kona_pwmc(struct pwm_chip *_chip)
>>          return container_of(_chip, struct kona_pwmc, chip);
>>   }
>>
>> -static void kona_pwmc_apply_settings(struct kona_pwmc *kp, unsigned int chan)
>> +static inline void kona_pwmc_set_trigger(struct kona_pwmc *kp,
>> +                                        unsigned int chan)
>>   {
>>          unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
>>
>> -       /* Clear trigger bit but set smooth bit to maintain old output */
>> -       value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);
>> +       /* set trigger bit to enable channel */
>> +       value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
>> +       writel(value, kp->base + PWM_CONTROL_OFFSET);
>> +       ndelay(PWMOUT_ENABLE_HOLD_DELAY);
>> +}
>> +static inline void kona_pwmc_clear_trigger(struct kona_pwmc *kp,
>> +                                          unsigned int chan)
>> +{
>> +       unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
>> +
>> +       /* Clear trigger bit */
>>          value &= ~(1 << PWM_CONTROL_TRIGGER_SHIFT(chan));
>>          writel(value, kp->base + PWM_CONTROL_OFFSET);
>> +       ndelay(PWMOUT_ENABLE_HOLD_DELAY);
>> +}
>>
>> -       /* Set trigger bit and clear smooth bit to apply new settings */
>> +static inline void kona_pwmc_clear_smooth(struct kona_pwmc *kp,
>> +                                         unsigned int chan)
>> +{
>> +       unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
>> +
>> +       /* Clear smooth bit */
>>          value &= ~(1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
>> -       value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
>>          writel(value, kp->base + PWM_CONTROL_OFFSET);
>>   }
>>
>> +static inline void kona_pwmc_set_smooth(struct kona_pwmc *kp, unsigned int chan)
>> +{
>> +       unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
>> +
>> +       /*  set smooth bit to maintain old output */
>> +       value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);
>> +       writel(value, kp->base + PWM_CONTROL_OFFSET);
>> +}
>> +
>> +static void kona_pwmc_write_settings(struct kona_pwmc *kp, unsigned int chan,
>> +                                    unsigned long prescale, unsigned long pc,
>> +                                    unsigned long dc)
>> +{
>> +       unsigned int value;
>> +
>> +       value = readl(kp->base + PRESCALE_OFFSET);
>> +       value &= ~PRESCALE_MASK(chan);
>> +       value |= prescale << PRESCALE_SHIFT(chan);
>> +       writel(value, kp->base + PRESCALE_OFFSET);
>> +
>> +       writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
>> +
>> +       writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
>> +
>> +}
>> +
>>   static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm,
>>                              int duty_ns, int period_ns)
>>   {
>>          struct kona_pwmc *kp = to_kona_pwmc(chip);
>>          u64 val, div, rate;
>>          unsigned long prescale = PRESCALE_MIN, pc, dc;
>> -       unsigned int value, chan = pwm->hwpwm;
>> +       unsigned int ret, chan = pwm->hwpwm;
>>
>>          /*
>>           * Find period count, duty count and prescale to suit duty_ns and
>> @@ -133,19 +179,30 @@ static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm,
>>                          return -EINVAL;
>>          }
>>
>> -       /* If the PWM channel is enabled, write the settings to the HW */
>> -       if (test_bit(PWMF_ENABLED, &pwm->flags)) {
>> -               value = readl(kp->base + PRESCALE_OFFSET);
>> -               value &= ~PRESCALE_MASK(chan);
>> -               value |= prescale << PRESCALE_SHIFT(chan);
>> -               writel(value, kp->base + PRESCALE_OFFSET);
>>
>> -               writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
>> +       /* If the PWM channel is not enabled, enable the clock */
>> +       if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
>> +               ret = clk_prepare_enable(kp->clk);
>> +               if (ret < 0) {
>> +                       dev_err(chip->dev, "failed to enable clock: %d\n", ret);
>> +                       return ret;
>> +               }
>> +       }
>>
>> -               writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
>> +       /* Set smooth bit to maintain old output */
>> +       kona_pwmc_set_smooth(kp, chan);
>> +       kona_pwmc_clear_trigger(kp, chan);
>> +
>> +       /* apply new settings */
>> +       kona_pwmc_write_settings(kp, chan, prescale, pc, dc);
>> +
>> +       /*If the PWM is enabled, enable the channel with the new settings
>> +        and if not  disable the clock*/
>> +       if (test_bit(PWMF_ENABLED, &pwm->flags))
>> +               kona_pwmc_set_trigger(kp, chan);
>> +       else
>> +               clk_disable_unprepare(kp->clk);
>>
>> -               kona_pwmc_apply_settings(kp, chan);
>> -       }
>>
>>          return 0;
>>   }
>> @@ -188,7 +245,6 @@ static int kona_pwmc_enable(struct pwm_chip *chip, struct pwm_device *pwm)
>>                  dev_err(chip->dev, "failed to enable clock: %d\n", ret);
>>                  return ret;
>>          }
>> -
>>          ret = kona_pwmc_config(chip, pwm, pwm->duty_cycle, pwm->period);
>>          if (ret < 0) {
>>                  clk_disable_unprepare(kp->clk);
>> @@ -203,12 +259,12 @@ static void kona_pwmc_disable(struct pwm_chip *chip, struct pwm_device *pwm)
>>          struct kona_pwmc *kp = to_kona_pwmc(chip);
>>          unsigned int chan = pwm->hwpwm;
>>
>> +       kona_pwmc_clear_smooth(kp, chan);
>> +       kona_pwmc_clear_trigger(kp, chan);
>
> I believe the output will spike high here.  Likely not what you want...

According to spec, this is the procedure to program the PWM and the code 
follows that:

STEP0: Program SMOOTH_TYPE=1. That will only allow changing of PWM 
setting at the PWM period boundary.
  STEP1: Program PWMOUT_ENABLE=0. At this time, PWM internal logic will 
continue to run with the previous settings. (i.e. If PWM is at 50Hz 40% 
duty cycle before, during the time when PWMOUT_ENABLE=0, it will still 
run at 50MHz 40% duty cycle.)
  STEP2: Program PWM register for new setting (i.e. PRESCALE, DUTY, 
PERIOD etc)
  STEP3: Program PWMOUT_ENABLE=1. That will load the new PWM setting 
from APB into PWM internal register. (Note. Minimum of 400ns is needed 
between step1 and step3. )
  STEP4: Keep PWMOUT ENABLE=1. (Note: If user didn't hold 
PWMOUT_ENABLE=1 for longer than 400ns, PWM internal logic will discard 
the new PWM setting in step2. User should hold the PWMOUT_ENABLE=1 
unless new PWM settings is needed.)



>
>>          /* Simulate a disable by configuring for zero duty */
>> -       writel(0, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
>> -       kona_pwmc_apply_settings(kp, chan);
>> -
>> -       /* Wait for waveform to settle before gating off the clock */
>> -       ndelay(400);
>> +       kona_pwmc_write_settings(kp, chan, 0, 0, 0);
>> +       kona_pwmc_set_polarity(chip, pwm, PWM_POLARITY_NORMAL);
>
> This is wrong.  You shouldn't change the polarity when the PWM is disabled.
>
> The original polarity isn't even restored when it is re-enabled...
>
this is procedure from the PWM spec to disable :

STEP0: Program SMOOTH_TYPE=0.
  STEP1: Program PWMOUT_ENABLE=0. Now, PWM internal logic will be at 
reset, PWM output will be default at 1.
  STEP2: Program PWM register to these setting. PRESCALE=0, POLARITY=1, 
DUTY=0, PERIOD=0.
  STEP3: Program PWMOUT_ENABLE=1, and Keep SMOOTH_TYPE=0.
  STEP4: Turn off PWM clock from CCU, and Keep PWMOUT ENABLE=1. (Note, 
It takes 400ns from STEP3 to turn off the LCD backlight, and user should 
guarantee that the PWM clock will not be disabled in less than 400ns 
after STEP3.

I agree with you that the original polarity isnt restored. I will need 
to add some code to check the syfs polarity value when the PWM is 
enabled. However, if i was to comply with the above spec, I would still 
have set the polarity. I just realized it should be set to inverted and 
I will fix this in the next patchset

>> +       kona_pwmc_set_trigger(kp, chan);
>>
>>          clk_disable_unprepare(kp->clk);
>>   }
>> --
>> 2.1.3
>>

Re: [PATCH v2 1/4] pwm: kona: Remove setting default smooth type and polarity for all channels

[Tim Kryger]

On Fri, Nov 28, 2014 at 3:47 PM, Arun Ramamurthy
<arun.ramamurthy@broadcom.com> wrote:
>
>
> On 14-11-25 09:51 PM, Tim Kryger wrote:
>>
>> On Tue, Nov 25, 2014 at 11:40 AM, Scott Branden <sbranden@broadcom.com>
>> wrote:
>>>
>>> From: Arun Ramamurthy <arunrama@broadcom.com>
>>>
>>> The probe routine unnecessarily sets the smooth type and polarity for
>>> all channels. This causes the channel for the speaker to click at the
>>> same
>>> time the backlight turns on. The smooth type and polarity should be set
>>> individually
>>> for each channel as required and no defaults need to be set.
>>
>>
>> I am guessing you are talking about a PWM controlled beeper/buzzer.
>>
> This change is more so to remove setting smooth type and polarity for all
> channels during probe and to leave them as their default values. Infact,
> setting the PWM_CONTROL_TYPE_SHIT is also redundant cause the default value
> is already 1 for all channels. We can remove that loop entirely and this
> will be done in the next patch set. The smooth type and polarity are only
> changed when the particular pwm channel is enabled or polarity is changed.
>
>> Can you mention what board you are observing this issue on?
>>
>> Also please explain why setting these bits result in an audible click.
>>
> We observe this on the bcm958300K board where one of the
> PWM channels is connected to the buzzer and changing the
> smooth type and polarity from its default values causes a click
>

Which of these two bits is causing the click?

I've already said that I'm open to removing the smooth bit here if that helps.

>>>
>>> Signed-off-by: Arun Ramamurthy <arunrama@broadcom.com>
>>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>>> ---
>>>   drivers/pwm/pwm-bcm-kona.c | 7 ++-----
>>>   1 file changed, 2 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
>>> index 02bc048..29eef9e 100644
>>> --- a/drivers/pwm/pwm-bcm-kona.c
>>> +++ b/drivers/pwm/pwm-bcm-kona.c
>>> @@ -266,12 +266,9 @@ static int kona_pwmc_probe(struct platform_device
>>> *pdev)
>>>                  return ret;
>>>          }
>>>
>>> -       /* Set smooth mode, push/pull, and normal polarity for all
>>> channels */
>>> -       for (chan = 0; chan < kp->chip.npwm; chan++) {
>>> -               value |= (1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
>>> +       /* Set push/pull for all channels */
>>> +       for (chan = 0; chan < kp->chip.npwm; chan++)
>>>                  value |= (1 << PWM_CONTROL_TYPE_SHIFT(chan));
>>> -               value |= (1 << PWM_CONTROL_POLARITY_SHIFT(chan));
>>> -       }
>>>
>>>          writel(value, kp->base + PWM_CONTROL_OFFSET);
>>
>>
>> While the smooth bit need not be set here, it is important that the
>> polarity bit be set.
>>
> The default value for polarity is 0 which is normal polarity, so setting it
> to 1 here in the probe function without a sysfs call is
> when the software will report the polarity as normal when it is actually
> inversed.

Please double check the meaning of the polarity bits for the revision
of PWM IP in your chip.  I suspect you are mistaken here.

This driver is for PWM blocks compatible those found in bcm28145,
bcm28155, bcm21664, and other mobile chips of that generation.

Apparently in contrast to the chip you are using, a set polarity bit
in the control register means normal polarity for the chips I
mentioned.

A default of zero for these bits means they must be set to meet the
PWM framework's expectation that channels begin with normal polarity.

>>
>> Otherwise software will report the polarity as normal when it it is
>> actually inversed.
>>
>> Consider the case where a userspace process is controlling the PWM via
>> sysfs.
>>
> I agree with you about the sysfs case Tim, but since this is the probe
> function and not a sysfs callback, should we not leave it as the default
> value?

Re: [PATCH v2 1/4] pwm: kona: Remove setting default smooth type and polarity for all channels

[Arun Ramamurthy]

On 14-11-28 05:08 PM, Tim Kryger wrote:
> On Fri, Nov 28, 2014 at 3:47 PM, Arun Ramamurthy
> <arun.ramamurthy@broadcom.com> wrote:
>>
>>
>> On 14-11-25 09:51 PM, Tim Kryger wrote:
>>>
>>> On Tue, Nov 25, 2014 at 11:40 AM, Scott Branden <sbranden@broadcom.com>
>>> wrote:
>>>>
>>>> From: Arun Ramamurthy <arunrama@broadcom.com>
>>>>
>>>> The probe routine unnecessarily sets the smooth type and polarity for
>>>> all channels. This causes the channel for the speaker to click at the
>>>> same
>>>> time the backlight turns on. The smooth type and polarity should be set
>>>> individually
>>>> for each channel as required and no defaults need to be set.
>>>
>>>
>>> I am guessing you are talking about a PWM controlled beeper/buzzer.
>>>
>> This change is more so to remove setting smooth type and polarity for all
>> channels during probe and to leave them as their default values. Infact,
>> setting the PWM_CONTROL_TYPE_SHIT is also redundant cause the default value
>> is already 1 for all channels. We can remove that loop entirely and this
>> will be done in the next patch set. The smooth type and polarity are only
>> changed when the particular pwm channel is enabled or polarity is changed.
>>
>>> Can you mention what board you are observing this issue on?
>>>
>>> Also please explain why setting these bits result in an audible click.
>>>
>> We observe this on the bcm958300K board where one of the
>> PWM channels is connected to the buzzer and changing the
>> smooth type and polarity from its default values causes a click
>>
>
> Which of these two bits is causing the click?
>
> I've already said that I'm open to removing the smooth bit here if that helps.
>
Thank you for your quick reply Tim. It is setting the polarity bit that 
causes the click. I am planning on removing this entire loop in the next 
patch set, are you okay with that?
>>>>
>>>> Signed-off-by: Arun Ramamurthy <arunrama@broadcom.com>
>>>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>>>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>>>> ---
>>>>    drivers/pwm/pwm-bcm-kona.c | 7 ++-----
>>>>    1 file changed, 2 insertions(+), 5 deletions(-)
>>>>
>>>> diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
>>>> index 02bc048..29eef9e 100644
>>>> --- a/drivers/pwm/pwm-bcm-kona.c
>>>> +++ b/drivers/pwm/pwm-bcm-kona.c
>>>> @@ -266,12 +266,9 @@ static int kona_pwmc_probe(struct platform_device
>>>> *pdev)
>>>>                   return ret;
>>>>           }
>>>>
>>>> -       /* Set smooth mode, push/pull, and normal polarity for all
>>>> channels */
>>>> -       for (chan = 0; chan < kp->chip.npwm; chan++) {
>>>> -               value |= (1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
>>>> +       /* Set push/pull for all channels */
>>>> +       for (chan = 0; chan < kp->chip.npwm; chan++)
>>>>                   value |= (1 << PWM_CONTROL_TYPE_SHIFT(chan));
>>>> -               value |= (1 << PWM_CONTROL_POLARITY_SHIFT(chan));
>>>> -       }
>>>>
>>>>           writel(value, kp->base + PWM_CONTROL_OFFSET);
>>>
>>>
>>> While the smooth bit need not be set here, it is important that the
>>> polarity bit be set.
>>>
>> The default value for polarity is 0 which is normal polarity, so setting it
>> to 1 here in the probe function without a sysfs call is
>> when the software will report the polarity as normal when it is actually
>> inversed.
>
> Please double check the meaning of the polarity bits for the revision
> of PWM IP in your chip.  I suspect you are mistaken here.
>
> This driver is for PWM blocks compatible those found in bcm28145,
> bcm28155, bcm21664, and other mobile chips of that generation.
>
> Apparently in contrast to the chip you are using, a set polarity bit
> in the control register means normal polarity for the chips I
> mentioned.
>
> A default of zero for these bits means they must be set to meet the
> PWM framework's expectation that channels begin with normal polarity.
>
Tim, this is from the RDB of our new chip which is supposed to have the 
same IP as the mobile chip sets you mentioned:

When set to 1 the output polarity for the PWM Output signal will be 
active hight; When set to 0, the output polarity for the PWM Output 
signal will be active low. Default State is 0.

My understanding is that the frameworks normal polarity means active 
low, am I mistaken in that?

>>>
>>> Otherwise software will report the polarity as normal when it it is
>>> actually inversed.
>>>
>>> Consider the case where a userspace process is controlling the PWM via
>>> sysfs.
>>>
>> I agree with you about the sysfs case Tim, but since this is the probe
>> function and not a sysfs callback, should we not leave it as the default
>> value?

Re: [PATCH v2 2/4] pwm: kona: Fix incorrect enable after channel polarity change

[Tim Kryger]

On Fri, Nov 28, 2014 at 3:48 PM, Arun Ramamurthy
<arun.ramamurthy@broadcom.com> wrote:
>
>
> On 14-11-25 10:22 PM, Tim Kryger wrote:
>>
>> On Tue, Nov 25, 2014 at 11:40 AM, Scott Branden <sbranden@broadcom.com>
>> wrote:
>>>
>>> From: Arun Ramamurthy <arunrama@broadcom.com>
>>>
>>> The pwm core code requires a separate call for enabling the channel
>>> and hence the driver does not need to set pwm_trigger after a
>>> polarity change
>>
>>
>> The framework does restrict when polarity changes can occur but it
>> isn't clear to me that there is any reason to delay applying the
>> polarity change.
>
> I examined several other drivers such as pwm-atmel-tcb.c, pwm-ep93xx.c,
> pwm-renesas-tpu.c, pwm-samsung.c in the 3.17 kernel tree and none of them
> enable the channel after changing polarity. We would be the first driver to
> do so.

We are not "enabling" the channel as much as we are "triggering an
application of settings" by hardware.

Both pwm-ep93xx and pwm-samsung write polarity settings to the
hardware immediately, presumably resulting in an immediate change in
output.

Alternatively, the pwm-atmel-tcb and pwm-renesas-tpu drivers save the
polarity and write it to hardware later.

There may be advantages to deferring the application of the polarity
till a subsequent enable but both approaches appear to be acceptable.

>
>> Keep in mind that polarity matters even when a PWM
>> is disabled.  While disabled, the output should be equivalent to an
>> enabled configuration with zero duty.  Thus for normal polarity the
>> output is constant low and for inversed polarity the output is
>> constant high.
>
> The driver does set the duty cycle to zero when disabling the pwm
> channel.However since the frame work prevents polarity change when the pwm
> is enabled, I don’t see how one could expect the polarity change to be
> reflected immediately without a separate call to pwm enable.
>
>
>> I believe there is an expectation that the output is
>> updated to reflect the requested polarity change prior to returning to
>> the caller.
>
>
> Once again I disagree with this based on other pwm drivers which only change
> the polarity and do not enable the channel when their set polarity functions
> are called.

I don't know why you keep calling this an enable.  Its not an enable,
it is only a trigger.

Perhaps this would be best explained with an example:

# Export PWM for access by userspace
cd /sys/class/pwm/pwmchip0
echo 0 > export
cd pwm0

# Request 50% duty output when PWM is enabled
echo 50000 > duty_cycle
echo 100000 > period

# Command Inversed Polarity
echo inversed > polarity

# Command Normal Polarity
echo normal > polarity

# Enable PWM
echo 1 > enable

The polarity changes trigger immediate output updates but the PWM is
not enabled until the end.

Prior to the last step the output is either a constant high or low
signal, not the 50% duty waveform.

>
>
>>
>>>
>>> Signed-off-by: Arun Ramamurthy <arunrama@broadcom.com>
>>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>>> ---
>>>   drivers/pwm/pwm-bcm-kona.c | 5 -----
>>>   1 file changed, 5 deletions(-)
>>>
>>> diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
>>> index 29eef9e..fa0b5bf 100644
>>> --- a/drivers/pwm/pwm-bcm-kona.c
>>> +++ b/drivers/pwm/pwm-bcm-kona.c
>>> @@ -173,11 +173,6 @@ static int kona_pwmc_set_polarity(struct pwm_chip
>>> *chip, struct pwm_device *pwm,
>>>
>>>          writel(value, kp->base + PWM_CONTROL_OFFSET);
>>>
>>> -       kona_pwmc_apply_settings(kp, chan);
>>> -
>>> -       /* Wait for waveform to settle before gating off the clock */
>>> -       ndelay(400);
>>> -
>>>          clk_disable_unprepare(kp->clk);
>>>
>>>          return 0;
>>> --
>>> 2.1.3
>>>
>

Re: [PATCH v2 3/4] pwm: kona: Fix enable, disable and config procedures

[Tim Kryger]

On Fri, Nov 28, 2014 at 3:49 PM, Arun Ramamurthy
<arun.ramamurthy@broadcom.com> wrote:
>
>
> On 14-11-25 11:29 PM, Tim Kryger wrote:
>>
>> On Tue, Nov 25, 2014 at 11:40 AM, Scott Branden <sbranden@broadcom.com>
>> wrote:
>>>
>>> From: Arun Ramamurthy <arunrama@broadcom.com>
>>>
>>> - Added helper functions to set and clear smooth and trigger bits
>>> - Added 400ns delays when clearing and setting trigger bit as requied
>>>    by spec
>>> - Added helper function to write prescale and other settings
>>> - Updated config procedure to match spec
>>> - Added code to handle pwn config when channel is disabled
>>> - Updated disable procedure to match spec
>>>
>>> Signed-off-by: Arun Ramamurthy <arunrama@broadcom.com>
>>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>>> ---
>>>   drivers/pwm/pwm-bcm-kona.c | 100
>>> +++++++++++++++++++++++++++++++++++----------
>>>   1 file changed, 78 insertions(+), 22 deletions(-)
>>
>>
>> The driver is fairly small and this change rewrites a considerable amount
>> of it.
>>
>> Is there a actually specific deficiency that this change is intended to
>> address?
>>
> The main issue this patchset addresses is setting the period and duty cycle
> when the pwm is disabled. This is done by turning on the clock and writing
> to the PWM registers. Additionally it also adds the 400ns
> delays specified by the PWM spec when setting or clearing certain bits. It
> also updates the PWM programming procedure to match the spec more closely.
> Although there is considerable change, all of it addresses the core
> functionality and it would not make sense to split it into multiple patches.

So what you are saying is that there isn't any known issue that this resolves.

This only changes the driver to use an alternate programming sequence?

The benefit here seems uncertain.

>
>> I'm not sure all the extra helper functions improve readability.
>>
> There was a lot of repeated code in various different functions. It seemed
> more efficient to consolidate them into helper functions. It also helped
> when comparing the spec to the code to check if we were
> setting the bits in the right order.
>
>
>>>
>>> diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
>>> index fa0b5bf..06fa983 100644
>>> --- a/drivers/pwm/pwm-bcm-kona.c
>>> +++ b/drivers/pwm/pwm-bcm-kona.c
>>> @@ -65,6 +65,10 @@
>>>   #define DUTY_CYCLE_HIGH_MIN                    (0x00000000)
>>>   #define DUTY_CYCLE_HIGH_MAX                    (0x00ffffff)
>>>
>>> +/* The delay required after clearing or setting
>>> +   PWMOUT_ENABLE*/
>>> +#define PWMOUT_ENABLE_HOLD_DELAY 400
>>> +
>>>   struct kona_pwmc {
>>>          struct pwm_chip chip;
>>>          void __iomem *base;
>>> @@ -76,28 +80,70 @@ static inline struct kona_pwmc *to_kona_pwmc(struct
>>> pwm_chip *_chip)
>>>          return container_of(_chip, struct kona_pwmc, chip);
>>>   }
>>>
>>> -static void kona_pwmc_apply_settings(struct kona_pwmc *kp, unsigned int
>>> chan)
>>> +static inline void kona_pwmc_set_trigger(struct kona_pwmc *kp,
>>> +                                        unsigned int chan)
>>>   {
>>>          unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
>>>
>>> -       /* Clear trigger bit but set smooth bit to maintain old output */
>>> -       value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);
>>> +       /* set trigger bit to enable channel */
>>> +       value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
>>> +       writel(value, kp->base + PWM_CONTROL_OFFSET);
>>> +       ndelay(PWMOUT_ENABLE_HOLD_DELAY);
>>> +}
>>> +static inline void kona_pwmc_clear_trigger(struct kona_pwmc *kp,
>>> +                                          unsigned int chan)
>>> +{
>>> +       unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
>>> +
>>> +       /* Clear trigger bit */
>>>          value &= ~(1 << PWM_CONTROL_TRIGGER_SHIFT(chan));
>>>          writel(value, kp->base + PWM_CONTROL_OFFSET);
>>> +       ndelay(PWMOUT_ENABLE_HOLD_DELAY);
>>> +}
>>>
>>> -       /* Set trigger bit and clear smooth bit to apply new settings */
>>> +static inline void kona_pwmc_clear_smooth(struct kona_pwmc *kp,
>>> +                                         unsigned int chan)
>>> +{
>>> +       unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
>>> +
>>> +       /* Clear smooth bit */
>>>          value &= ~(1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
>>> -       value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
>>>          writel(value, kp->base + PWM_CONTROL_OFFSET);
>>>   }
>>>
>>> +static inline void kona_pwmc_set_smooth(struct kona_pwmc *kp, unsigned
>>> int chan)
>>> +{
>>> +       unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
>>> +
>>> +       /*  set smooth bit to maintain old output */
>>> +       value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);
>>> +       writel(value, kp->base + PWM_CONTROL_OFFSET);
>>> +}
>>> +
>>> +static void kona_pwmc_write_settings(struct kona_pwmc *kp, unsigned int
>>> chan,
>>> +                                    unsigned long prescale, unsigned
>>> long pc,
>>> +                                    unsigned long dc)
>>> +{
>>> +       unsigned int value;
>>> +
>>> +       value = readl(kp->base + PRESCALE_OFFSET);
>>> +       value &= ~PRESCALE_MASK(chan);
>>> +       value |= prescale << PRESCALE_SHIFT(chan);
>>> +       writel(value, kp->base + PRESCALE_OFFSET);
>>> +
>>> +       writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
>>> +
>>> +       writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
>>> +
>>> +}
>>> +
>>>   static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device
>>> *pwm,
>>>                              int duty_ns, int period_ns)
>>>   {
>>>          struct kona_pwmc *kp = to_kona_pwmc(chip);
>>>          u64 val, div, rate;
>>>          unsigned long prescale = PRESCALE_MIN, pc, dc;
>>> -       unsigned int value, chan = pwm->hwpwm;
>>> +       unsigned int ret, chan = pwm->hwpwm;
>>>
>>>          /*
>>>           * Find period count, duty count and prescale to suit duty_ns
>>> and
>>> @@ -133,19 +179,30 @@ static int kona_pwmc_config(struct pwm_chip *chip,
>>> struct pwm_device *pwm,
>>>                          return -EINVAL;
>>>          }
>>>
>>> -       /* If the PWM channel is enabled, write the settings to the HW */
>>> -       if (test_bit(PWMF_ENABLED, &pwm->flags)) {
>>> -               value = readl(kp->base + PRESCALE_OFFSET);
>>> -               value &= ~PRESCALE_MASK(chan);
>>> -               value |= prescale << PRESCALE_SHIFT(chan);
>>> -               writel(value, kp->base + PRESCALE_OFFSET);
>>>
>>> -               writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
>>> +       /* If the PWM channel is not enabled, enable the clock */
>>> +       if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
>>> +               ret = clk_prepare_enable(kp->clk);
>>> +               if (ret < 0) {
>>> +                       dev_err(chip->dev, "failed to enable clock:
>>> %d\n", ret);
>>> +                       return ret;
>>> +               }
>>> +       }
>>>
>>> -               writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
>>> +       /* Set smooth bit to maintain old output */
>>> +       kona_pwmc_set_smooth(kp, chan);
>>> +       kona_pwmc_clear_trigger(kp, chan);
>>> +
>>> +       /* apply new settings */
>>> +       kona_pwmc_write_settings(kp, chan, prescale, pc, dc);
>>> +
>>> +       /*If the PWM is enabled, enable the channel with the new settings
>>> +        and if not  disable the clock*/
>>> +       if (test_bit(PWMF_ENABLED, &pwm->flags))
>>> +               kona_pwmc_set_trigger(kp, chan);
>>> +       else
>>> +               clk_disable_unprepare(kp->clk);
>>>
>>> -               kona_pwmc_apply_settings(kp, chan);
>>> -       }
>>>
>>>          return 0;
>>>   }
>>> @@ -188,7 +245,6 @@ static int kona_pwmc_enable(struct pwm_chip *chip,
>>> struct pwm_device *pwm)
>>>                  dev_err(chip->dev, "failed to enable clock: %d\n", ret);
>>>                  return ret;
>>>          }
>>> -
>>>          ret = kona_pwmc_config(chip, pwm, pwm->duty_cycle, pwm->period);
>>>          if (ret < 0) {
>>>                  clk_disable_unprepare(kp->clk);
>>> @@ -203,12 +259,12 @@ static void kona_pwmc_disable(struct pwm_chip
>>> *chip, struct pwm_device *pwm)
>>>          struct kona_pwmc *kp = to_kona_pwmc(chip);
>>>          unsigned int chan = pwm->hwpwm;
>>>
>>> +       kona_pwmc_clear_smooth(kp, chan);
>>> +       kona_pwmc_clear_trigger(kp, chan);
>>
>>
>> I believe the output will spike high here.  Likely not what you want...
>
>
> According to spec, this is the procedure to program the PWM and the code
> follows that:
>
> STEP0: Program SMOOTH_TYPE=1. That will only allow changing of PWM setting
> at the PWM period boundary.
>  STEP1: Program PWMOUT_ENABLE=0. At this time, PWM internal logic will
> continue to run with the previous settings. (i.e. If PWM is at 50Hz 40% duty
> cycle before, during the time when PWMOUT_ENABLE=0, it will still run at
> 50MHz 40% duty cycle.)
>  STEP2: Program PWM register for new setting (i.e. PRESCALE, DUTY, PERIOD
> etc)
>  STEP3: Program PWMOUT_ENABLE=1. That will load the new PWM setting from APB
> into PWM internal register. (Note. Minimum of 400ns is needed between step1
> and step3. )
>  STEP4: Keep PWMOUT ENABLE=1. (Note: If user didn't hold PWMOUT_ENABLE=1 for
> longer than 400ns, PWM internal logic will discard the new PWM setting in
> step2. User should hold the PWMOUT_ENABLE=1 unless new PWM settings is
> needed.)
>
>
>
>>
>>>          /* Simulate a disable by configuring for zero duty */
>>> -       writel(0, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
>>> -       kona_pwmc_apply_settings(kp, chan);
>>> -
>>> -       /* Wait for waveform to settle before gating off the clock */
>>> -       ndelay(400);
>>> +       kona_pwmc_write_settings(kp, chan, 0, 0, 0);
>>> +       kona_pwmc_set_polarity(chip, pwm, PWM_POLARITY_NORMAL);
>>
>>
>> This is wrong.  You shouldn't change the polarity when the PWM is
>> disabled.
>>
>> The original polarity isn't even restored when it is re-enabled...
>>
> this is procedure from the PWM spec to disable :
>
> STEP0: Program SMOOTH_TYPE=0.
>  STEP1: Program PWMOUT_ENABLE=0. Now, PWM internal logic will be at reset,
> PWM output will be default at 1.

This is exactly what I was saying before.  You glitch the output high
for no good reason.

The sequence in the document isn't gospel.  From what I recall, it was
just a verification engineer's best guess at how to get a very unusual
PWM controller to do the normal PWM things.

>  STEP2: Program PWM register to these setting. PRESCALE=0, POLARITY=1,
> DUTY=0, PERIOD=0.
>  STEP3: Program PWMOUT_ENABLE=1, and Keep SMOOTH_TYPE=0.
>  STEP4: Turn off PWM clock from CCU, and Keep PWMOUT ENABLE=1. (Note, It
> takes 400ns from STEP3 to turn off the LCD backlight, and user should
> guarantee that the PWM clock will not be disabled in less than 400ns after
> STEP3.
>
> I agree with you that the original polarity isnt restored. I will need to
> add some code to check the syfs polarity value when the PWM is enabled.
> However, if i was to comply with the above spec, I would still have set the
> polarity. I just realized it should be set to inverted and I will fix this
> in the next patchset
>
>
>>> +       kona_pwmc_set_trigger(kp, chan);
>>>
>>>          clk_disable_unprepare(kp->clk);
>>>   }
>>> --
>>> 2.1.3
>>>
>

Re: [PATCH v2 1/4] pwm: kona: Remove setting default smooth type and polarity for all channels

[Tim Kryger]

On Fri, Nov 28, 2014 at 5:19 PM, Arun Ramamurthy
<arun.ramamurthy@broadcom.com> wrote:
>
>
> On 14-11-28 05:08 PM, Tim Kryger wrote:
>>
>> On Fri, Nov 28, 2014 at 3:47 PM, Arun Ramamurthy
>> <arun.ramamurthy@broadcom.com> wrote:
>>>
>>>
>>>
>>> On 14-11-25 09:51 PM, Tim Kryger wrote:
>>>>
>>>>
>>>> On Tue, Nov 25, 2014 at 11:40 AM, Scott Branden <sbranden@broadcom.com>
>>>> wrote:
>>>>>
>>>>>
>>>>> From: Arun Ramamurthy <arunrama@broadcom.com>
>>>>>
>>>>> The probe routine unnecessarily sets the smooth type and polarity for
>>>>> all channels. This causes the channel for the speaker to click at the
>>>>> same
>>>>> time the backlight turns on. The smooth type and polarity should be set
>>>>> individually
>>>>> for each channel as required and no defaults need to be set.
>>>>
>>>>
>>>>
>>>> I am guessing you are talking about a PWM controlled beeper/buzzer.
>>>>
>>> This change is more so to remove setting smooth type and polarity for all
>>> channels during probe and to leave them as their default values. Infact,
>>> setting the PWM_CONTROL_TYPE_SHIT is also redundant cause the default
>>> value
>>> is already 1 for all channels. We can remove that loop entirely and this
>>> will be done in the next patch set. The smooth type and polarity are only
>>> changed when the particular pwm channel is enabled or polarity is
>>> changed.
>>>
>>>> Can you mention what board you are observing this issue on?
>>>>
>>>> Also please explain why setting these bits result in an audible click.
>>>>
>>> We observe this on the bcm958300K board where one of the
>>> PWM channels is connected to the buzzer and changing the
>>> smooth type and polarity from its default values causes a click
>>>
>>
>> Which of these two bits is causing the click?
>>
>> I've already said that I'm open to removing the smooth bit here if that
>> helps.
>>
> Thank you for your quick reply Tim. It is setting the polarity bit that
> causes the click. I am planning on removing this entire loop in the next
> patch set, are you okay with that?

Does it cause a click at this moment or at a later point in time?

Is the click your sole motivation for this series?  If so, can you
propose a more targeted fix?

I would be amenable to deferring polarity changes until subsequent
enable operations:

- kona_pwmc_probe doesn't do any hardware writes
- kona_pwmc_set_polarity only updates a polarity variable
- kona_pwmc_enable sets hardware polarity according to the variable

Would this be sufficient to satisfy your needs?

I am still worried that deferring polarity changes may negatively
impact some PWM users who set polarity but don't immediately enable
the PWM.

>>>>>
>>>>> Signed-off-by: Arun Ramamurthy <arunrama@broadcom.com>
>>>>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>>>>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>>>>> ---
>>>>>    drivers/pwm/pwm-bcm-kona.c | 7 ++-----
>>>>>    1 file changed, 2 insertions(+), 5 deletions(-)
>>>>>
>>>>> diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
>>>>> index 02bc048..29eef9e 100644
>>>>> --- a/drivers/pwm/pwm-bcm-kona.c
>>>>> +++ b/drivers/pwm/pwm-bcm-kona.c
>>>>> @@ -266,12 +266,9 @@ static int kona_pwmc_probe(struct platform_device
>>>>> *pdev)
>>>>>                   return ret;
>>>>>           }
>>>>>
>>>>> -       /* Set smooth mode, push/pull, and normal polarity for all
>>>>> channels */
>>>>> -       for (chan = 0; chan < kp->chip.npwm; chan++) {
>>>>> -               value |= (1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
>>>>> +       /* Set push/pull for all channels */
>>>>> +       for (chan = 0; chan < kp->chip.npwm; chan++)
>>>>>                   value |= (1 << PWM_CONTROL_TYPE_SHIFT(chan));
>>>>> -               value |= (1 << PWM_CONTROL_POLARITY_SHIFT(chan));
>>>>> -       }
>>>>>
>>>>>           writel(value, kp->base + PWM_CONTROL_OFFSET);
>>>>
>>>>
>>>>
>>>> While the smooth bit need not be set here, it is important that the
>>>> polarity bit be set.
>>>>
>>> The default value for polarity is 0 which is normal polarity, so setting
>>> it
>>> to 1 here in the probe function without a sysfs call is
>>> when the software will report the polarity as normal when it is actually
>>> inversed.
>>
>>
>> Please double check the meaning of the polarity bits for the revision
>> of PWM IP in your chip.  I suspect you are mistaken here.
>>
>> This driver is for PWM blocks compatible those found in bcm28145,
>> bcm28155, bcm21664, and other mobile chips of that generation.
>>
>> Apparently in contrast to the chip you are using, a set polarity bit
>> in the control register means normal polarity for the chips I
>> mentioned.
>>
>> A default of zero for these bits means they must be set to meet the
>> PWM framework's expectation that channels begin with normal polarity.
>>
> Tim, this is from the RDB of our new chip which is supposed to have the same
> IP as the mobile chip sets you mentioned:
>
> When set to 1 the output polarity for the PWM Output signal will be active
> hight; When set to 0, the output polarity for the PWM Output signal will be
> active low. Default State is 0.
>
> My understanding is that the frameworks normal polarity means active low, am
> I mistaken in that?

That is not how I would interpret things.

Perhaps this paragraph from Documentation/pwm.txt will help you:

When implementing polarity support in a PWM driver, make sure to respect the
signal conventions in the PWM framework. By definition, normal polarity
characterizes a signal starts high for the duration of the duty cycle and
goes low for the remainder of the period. Conversely, a signal with inversed
polarity starts low for the duration of the duty cycle and goes high for the
remainder of the period.

>
>>>>
>>>> Otherwise software will report the polarity as normal when it it is
>>>> actually inversed.
>>>>
>>>> Consider the case where a userspace process is controlling the PWM via
>>>> sysfs.
>>>>
>>> I agree with you about the sysfs case Tim, but since this is the probe
>>> function and not a sysfs callback, should we not leave it as the default
>>> value?

Re: [PATCH v2 3/4] pwm: kona: Fix enable, disable and config procedures

[Arun Ramamurthy]

On 14-11-28 06:30 PM, Tim Kryger wrote:
> On Fri, Nov 28, 2014 at 3:49 PM, Arun Ramamurthy
> <arun.ramamurthy@broadcom.com> wrote:
>>
>>
>> On 14-11-25 11:29 PM, Tim Kryger wrote:
>>>
>>> On Tue, Nov 25, 2014 at 11:40 AM, Scott Branden <sbranden@broadcom.com>
>>> wrote:
>>>>
>>>> From: Arun Ramamurthy <arunrama@broadcom.com>
>>>>
>>>> - Added helper functions to set and clear smooth and trigger bits
>>>> - Added 400ns delays when clearing and setting trigger bit as requied
>>>>     by spec
>>>> - Added helper function to write prescale and other settings
>>>> - Updated config procedure to match spec
>>>> - Added code to handle pwn config when channel is disabled
>>>> - Updated disable procedure to match spec
>>>>
>>>> Signed-off-by: Arun Ramamurthy <arunrama@broadcom.com>
>>>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>>>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>>>> ---
>>>>    drivers/pwm/pwm-bcm-kona.c | 100
>>>> +++++++++++++++++++++++++++++++++++----------
>>>>    1 file changed, 78 insertions(+), 22 deletions(-)
>>>
>>>
>>> The driver is fairly small and this change rewrites a considerable amount
>>> of it.
>>>
>>> Is there a actually specific deficiency that this change is intended to
>>> address?
>>>
>> The main issue this patchset addresses is setting the period and duty cycle
>> when the pwm is disabled. This is done by turning on the clock and writing
>> to the PWM registers. Additionally it also adds the 400ns
>> delays specified by the PWM spec when setting or clearing certain bits. It
>> also updates the PWM programming procedure to match the spec more closely.
>> Although there is considerable change, all of it addresses the core
>> functionality and it would not make sense to split it into multiple patches.
>
> So what you are saying is that there isn't any known issue that this resolves.
>
> This only changes the driver to use an alternate programming sequence?
>
> The benefit here seems uncertain.
>
Actually Tim, it addresses the bug where period and duty cycle are not 
set if the PWM channel is not enabled in sysfs. Following up on your 
example you provided in your other email:

# Disable PWM
echo 0 > enable

# Change to a 25% duty output when PWM is enabled
echo 25000 > duty_cycle

The original code would not write this duty cycle change to the 
registers as the PWmF_ENABLED bit is not set and the clocks are turned off.

I can remove all the helper functions and address only this particular 
bug if you prefer that.
>>
>>> I'm not sure all the extra helper functions improve readability.
>>>
>> There was a lot of repeated code in various different functions. It seemed
>> more efficient to consolidate them into helper functions. It also helped
>> when comparing the spec to the code to check if we were
>> setting the bits in the right order.
>>
>>
>>>>
>>>> diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
>>>> index fa0b5bf..06fa983 100644
>>>> --- a/drivers/pwm/pwm-bcm-kona.c
>>>> +++ b/drivers/pwm/pwm-bcm-kona.c
>>>> @@ -65,6 +65,10 @@
>>>>    #define DUTY_CYCLE_HIGH_MIN                    (0x00000000)
>>>>    #define DUTY_CYCLE_HIGH_MAX                    (0x00ffffff)
>>>>
>>>> +/* The delay required after clearing or setting
>>>> +   PWMOUT_ENABLE*/
>>>> +#define PWMOUT_ENABLE_HOLD_DELAY 400
>>>> +
>>>>    struct kona_pwmc {
>>>>           struct pwm_chip chip;
>>>>           void __iomem *base;
>>>> @@ -76,28 +80,70 @@ static inline struct kona_pwmc *to_kona_pwmc(struct
>>>> pwm_chip *_chip)
>>>>           return container_of(_chip, struct kona_pwmc, chip);
>>>>    }
>>>>
>>>> -static void kona_pwmc_apply_settings(struct kona_pwmc *kp, unsigned int
>>>> chan)
>>>> +static inline void kona_pwmc_set_trigger(struct kona_pwmc *kp,
>>>> +                                        unsigned int chan)
>>>>    {
>>>>           unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
>>>>
>>>> -       /* Clear trigger bit but set smooth bit to maintain old output */
>>>> -       value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);
>>>> +       /* set trigger bit to enable channel */
>>>> +       value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
>>>> +       writel(value, kp->base + PWM_CONTROL_OFFSET);
>>>> +       ndelay(PWMOUT_ENABLE_HOLD_DELAY);
>>>> +}
>>>> +static inline void kona_pwmc_clear_trigger(struct kona_pwmc *kp,
>>>> +                                          unsigned int chan)
>>>> +{
>>>> +       unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
>>>> +
>>>> +       /* Clear trigger bit */
>>>>           value &= ~(1 << PWM_CONTROL_TRIGGER_SHIFT(chan));
>>>>           writel(value, kp->base + PWM_CONTROL_OFFSET);
>>>> +       ndelay(PWMOUT_ENABLE_HOLD_DELAY);
>>>> +}
>>>>
>>>> -       /* Set trigger bit and clear smooth bit to apply new settings */
>>>> +static inline void kona_pwmc_clear_smooth(struct kona_pwmc *kp,
>>>> +                                         unsigned int chan)
>>>> +{
>>>> +       unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
>>>> +
>>>> +       /* Clear smooth bit */
>>>>           value &= ~(1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
>>>> -       value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
>>>>           writel(value, kp->base + PWM_CONTROL_OFFSET);
>>>>    }
>>>>
>>>> +static inline void kona_pwmc_set_smooth(struct kona_pwmc *kp, unsigned
>>>> int chan)
>>>> +{
>>>> +       unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
>>>> +
>>>> +       /*  set smooth bit to maintain old output */
>>>> +       value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);
>>>> +       writel(value, kp->base + PWM_CONTROL_OFFSET);
>>>> +}
>>>> +
>>>> +static void kona_pwmc_write_settings(struct kona_pwmc *kp, unsigned int
>>>> chan,
>>>> +                                    unsigned long prescale, unsigned
>>>> long pc,
>>>> +                                    unsigned long dc)
>>>> +{
>>>> +       unsigned int value;
>>>> +
>>>> +       value = readl(kp->base + PRESCALE_OFFSET);
>>>> +       value &= ~PRESCALE_MASK(chan);
>>>> +       value |= prescale << PRESCALE_SHIFT(chan);
>>>> +       writel(value, kp->base + PRESCALE_OFFSET);
>>>> +
>>>> +       writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
>>>> +
>>>> +       writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
>>>> +
>>>> +}
>>>> +
>>>>    static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device
>>>> *pwm,
>>>>                               int duty_ns, int period_ns)
>>>>    {
>>>>           struct kona_pwmc *kp = to_kona_pwmc(chip);
>>>>           u64 val, div, rate;
>>>>           unsigned long prescale = PRESCALE_MIN, pc, dc;
>>>> -       unsigned int value, chan = pwm->hwpwm;
>>>> +       unsigned int ret, chan = pwm->hwpwm;
>>>>
>>>>           /*
>>>>            * Find period count, duty count and prescale to suit duty_ns
>>>> and
>>>> @@ -133,19 +179,30 @@ static int kona_pwmc_config(struct pwm_chip *chip,
>>>> struct pwm_device *pwm,
>>>>                           return -EINVAL;
>>>>           }
>>>>
>>>> -       /* If the PWM channel is enabled, write the settings to the HW */
>>>> -       if (test_bit(PWMF_ENABLED, &pwm->flags)) {
>>>> -               value = readl(kp->base + PRESCALE_OFFSET);
>>>> -               value &= ~PRESCALE_MASK(chan);
>>>> -               value |= prescale << PRESCALE_SHIFT(chan);
>>>> -               writel(value, kp->base + PRESCALE_OFFSET);
>>>>
>>>> -               writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
>>>> +       /* If the PWM channel is not enabled, enable the clock */
>>>> +       if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
>>>> +               ret = clk_prepare_enable(kp->clk);
>>>> +               if (ret < 0) {
>>>> +                       dev_err(chip->dev, "failed to enable clock:
>>>> %d\n", ret);
>>>> +                       return ret;
>>>> +               }
>>>> +       }
>>>>
>>>> -               writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
>>>> +       /* Set smooth bit to maintain old output */
>>>> +       kona_pwmc_set_smooth(kp, chan);
>>>> +       kona_pwmc_clear_trigger(kp, chan);
>>>> +
>>>> +       /* apply new settings */
>>>> +       kona_pwmc_write_settings(kp, chan, prescale, pc, dc);
>>>> +
>>>> +       /*If the PWM is enabled, enable the channel with the new settings
>>>> +        and if not  disable the clock*/
>>>> +       if (test_bit(PWMF_ENABLED, &pwm->flags))
>>>> +               kona_pwmc_set_trigger(kp, chan);
>>>> +       else
>>>> +               clk_disable_unprepare(kp->clk);
>>>>
>>>> -               kona_pwmc_apply_settings(kp, chan);
>>>> -       }
>>>>
>>>>           return 0;
>>>>    }
>>>> @@ -188,7 +245,6 @@ static int kona_pwmc_enable(struct pwm_chip *chip,
>>>> struct pwm_device *pwm)
>>>>                   dev_err(chip->dev, "failed to enable clock: %d\n", ret);
>>>>                   return ret;
>>>>           }
>>>> -
>>>>           ret = kona_pwmc_config(chip, pwm, pwm->duty_cycle, pwm->period);
>>>>           if (ret < 0) {
>>>>                   clk_disable_unprepare(kp->clk);
>>>> @@ -203,12 +259,12 @@ static void kona_pwmc_disable(struct pwm_chip
>>>> *chip, struct pwm_device *pwm)
>>>>           struct kona_pwmc *kp = to_kona_pwmc(chip);
>>>>           unsigned int chan = pwm->hwpwm;
>>>>
>>>> +       kona_pwmc_clear_smooth(kp, chan);
>>>> +       kona_pwmc_clear_trigger(kp, chan);
>>>
>>>
>>> I believe the output will spike high here.  Likely not what you want...
>>
>>
>> According to spec, this is the procedure to program the PWM and the code
>> follows that:
>>
>> STEP0: Program SMOOTH_TYPE=1. That will only allow changing of PWM setting
>> at the PWM period boundary.
>>   STEP1: Program PWMOUT_ENABLE=0. At this time, PWM internal logic will
>> continue to run with the previous settings. (i.e. If PWM is at 50Hz 40% duty
>> cycle before, during the time when PWMOUT_ENABLE=0, it will still run at
>> 50MHz 40% duty cycle.)
>>   STEP2: Program PWM register for new setting (i.e. PRESCALE, DUTY, PERIOD
>> etc)
>>   STEP3: Program PWMOUT_ENABLE=1. That will load the new PWM setting from APB
>> into PWM internal register. (Note. Minimum of 400ns is needed between step1
>> and step3. )
>>   STEP4: Keep PWMOUT ENABLE=1. (Note: If user didn't hold PWMOUT_ENABLE=1 for
>> longer than 400ns, PWM internal logic will discard the new PWM setting in
>> step2. User should hold the PWMOUT_ENABLE=1 unless new PWM settings is
>> needed.)
>>
>>
>>
>>>
>>>>           /* Simulate a disable by configuring for zero duty */
>>>> -       writel(0, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
>>>> -       kona_pwmc_apply_settings(kp, chan);
>>>> -
>>>> -       /* Wait for waveform to settle before gating off the clock */
>>>> -       ndelay(400);
>>>> +       kona_pwmc_write_settings(kp, chan, 0, 0, 0);
>>>> +       kona_pwmc_set_polarity(chip, pwm, PWM_POLARITY_NORMAL);
>>>
>>>
>>> This is wrong.  You shouldn't change the polarity when the PWM is
>>> disabled.
>>>
>>> The original polarity isn't even restored when it is re-enabled...
>>>
>> this is procedure from the PWM spec to disable :
>>
>> STEP0: Program SMOOTH_TYPE=0.
>>   STEP1: Program PWMOUT_ENABLE=0. Now, PWM internal logic will be at reset,
>> PWM output will be default at 1.
>
> This is exactly what I was saying before.  You glitch the output high
> for no good reason.
>
> The sequence in the document isn't gospel.  From what I recall, it was
> just a verification engineer's best guess at how to get a very unusual
> PWM controller to do the normal PWM things.

So to summarize, you would prefer that the disable procedure be left 
unchanged which is to set the duty cycle to zero.
>
>>   STEP2: Program PWM register to these setting. PRESCALE=0, POLARITY=1,
>> DUTY=0, PERIOD=0.
>>   STEP3: Program PWMOUT_ENABLE=1, and Keep SMOOTH_TYPE=0.
>>   STEP4: Turn off PWM clock from CCU, and Keep PWMOUT ENABLE=1. (Note, It
>> takes 400ns from STEP3 to turn off the LCD backlight, and user should
>> guarantee that the PWM clock will not be disabled in less than 400ns after
>> STEP3.
>>
>> I agree with you that the original polarity isnt restored. I will need to
>> add some code to check the syfs polarity value when the PWM is enabled.
>> However, if i was to comply with the above spec, I would still have set the
>> polarity. I just realized it should be set to inverted and I will fix this
>> in the next patchset
>>
>>
>>>> +       kona_pwmc_set_trigger(kp, chan);
>>>>
>>>>           clk_disable_unprepare(kp->clk);
>>>>    }
>>>> --
>>>> 2.1.3
>>>>
>>

Re: [PATCH v2 1/4] pwm: kona: Remove setting default smooth type and polarity for all channels

[Arun Ramamurthy]

On 14-11-28 07:19 PM, Tim Kryger wrote:
> On Fri, Nov 28, 2014 at 5:19 PM, Arun Ramamurthy
> <arun.ramamurthy@broadcom.com> wrote:
>>
>>
>> On 14-11-28 05:08 PM, Tim Kryger wrote:
>>>
>>> On Fri, Nov 28, 2014 at 3:47 PM, Arun Ramamurthy
>>> <arun.ramamurthy@broadcom.com> wrote:
>>>>
>>>>
>>>>
>>>> On 14-11-25 09:51 PM, Tim Kryger wrote:
>>>>>
>>>>>
>>>>> On Tue, Nov 25, 2014 at 11:40 AM, Scott Branden <sbranden@broadcom.com>
>>>>> wrote:
>>>>>>
>>>>>>
>>>>>> From: Arun Ramamurthy <arunrama@broadcom.com>
>>>>>>
>>>>>> The probe routine unnecessarily sets the smooth type and polarity for
>>>>>> all channels. This causes the channel for the speaker to click at the
>>>>>> same
>>>>>> time the backlight turns on. The smooth type and polarity should be set
>>>>>> individually
>>>>>> for each channel as required and no defaults need to be set.
>>>>>
>>>>>
>>>>>
>>>>> I am guessing you are talking about a PWM controlled beeper/buzzer.
>>>>>
>>>> This change is more so to remove setting smooth type and polarity for all
>>>> channels during probe and to leave them as their default values. Infact,
>>>> setting the PWM_CONTROL_TYPE_SHIT is also redundant cause the default
>>>> value
>>>> is already 1 for all channels. We can remove that loop entirely and this
>>>> will be done in the next patch set. The smooth type and polarity are only
>>>> changed when the particular pwm channel is enabled or polarity is
>>>> changed.
>>>>
>>>>> Can you mention what board you are observing this issue on?
>>>>>
>>>>> Also please explain why setting these bits result in an audible click.
>>>>>
>>>> We observe this on the bcm958300K board where one of the
>>>> PWM channels is connected to the buzzer and changing the
>>>> smooth type and polarity from its default values causes a click
>>>>
>>>
>>> Which of these two bits is causing the click?
>>>
>>> I've already said that I'm open to removing the smooth bit here if that
>>> helps.
>>>
>> Thank you for your quick reply Tim. It is setting the polarity bit that
>> causes the click. I am planning on removing this entire loop in the next
>> patch set, are you okay with that?
>
> Does it cause a click at this moment or at a later point in time?
>
> Is the click your sole motivation for this series?  If so, can you
> propose a more targeted fix?
>
> I would be amenable to deferring polarity changes until subsequent
> enable operations:
>
> - kona_pwmc_probe doesn't do any hardware writes
> - kona_pwmc_set_polarity only updates a polarity variable
> - kona_pwmc_enable sets hardware polarity according to the variable
>
> Would this be sufficient to satisfy your needs?
>
It clicks at time of boot up, I can agree to the above changes and will 
update the next patch set accordingly.
> I am still worried that deferring polarity changes may negatively
> impact some PWM users who set polarity but don't immediately enable
> the PWM.
>
>>>>>>
>>>>>> Signed-off-by: Arun Ramamurthy <arunrama@broadcom.com>
>>>>>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>>>>>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>>>>>> ---
>>>>>>     drivers/pwm/pwm-bcm-kona.c | 7 ++-----
>>>>>>     1 file changed, 2 insertions(+), 5 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
>>>>>> index 02bc048..29eef9e 100644
>>>>>> --- a/drivers/pwm/pwm-bcm-kona.c
>>>>>> +++ b/drivers/pwm/pwm-bcm-kona.c
>>>>>> @@ -266,12 +266,9 @@ static int kona_pwmc_probe(struct platform_device
>>>>>> *pdev)
>>>>>>                    return ret;
>>>>>>            }
>>>>>>
>>>>>> -       /* Set smooth mode, push/pull, and normal polarity for all
>>>>>> channels */
>>>>>> -       for (chan = 0; chan < kp->chip.npwm; chan++) {
>>>>>> -               value |= (1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
>>>>>> +       /* Set push/pull for all channels */
>>>>>> +       for (chan = 0; chan < kp->chip.npwm; chan++)
>>>>>>                    value |= (1 << PWM_CONTROL_TYPE_SHIFT(chan));
>>>>>> -               value |= (1 << PWM_CONTROL_POLARITY_SHIFT(chan));
>>>>>> -       }
>>>>>>
>>>>>>            writel(value, kp->base + PWM_CONTROL_OFFSET);
>>>>>
>>>>>
>>>>>
>>>>> While the smooth bit need not be set here, it is important that the
>>>>> polarity bit be set.
>>>>>
>>>> The default value for polarity is 0 which is normal polarity, so setting
>>>> it
>>>> to 1 here in the probe function without a sysfs call is
>>>> when the software will report the polarity as normal when it is actually
>>>> inversed.
>>>
>>>
>>> Please double check the meaning of the polarity bits for the revision
>>> of PWM IP in your chip.  I suspect you are mistaken here.
>>>
>>> This driver is for PWM blocks compatible those found in bcm28145,
>>> bcm28155, bcm21664, and other mobile chips of that generation.
>>>
>>> Apparently in contrast to the chip you are using, a set polarity bit
>>> in the control register means normal polarity for the chips I
>>> mentioned.
>>>
>>> A default of zero for these bits means they must be set to meet the
>>> PWM framework's expectation that channels begin with normal polarity.
>>>
>> Tim, this is from the RDB of our new chip which is supposed to have the same
>> IP as the mobile chip sets you mentioned:
>>
>> When set to 1 the output polarity for the PWM Output signal will be active
>> hight; When set to 0, the output polarity for the PWM Output signal will be
>> active low. Default State is 0.
>>
>> My understanding is that the frameworks normal polarity means active low, am
>> I mistaken in that?
>
> That is not how I would interpret things.
>
> Perhaps this paragraph from Documentation/pwm.txt will help you:
>
> When implementing polarity support in a PWM driver, make sure to respect the
> signal conventions in the PWM framework. By definition, normal polarity
> characterizes a signal starts high for the duration of the duty cycle and
> goes low for the remainder of the period. Conversely, a signal with inversed
> polarity starts low for the duration of the duty cycle and goes high for the
> remainder of the period.
>
I had it mixed up, I will update the polarity to match the PWM framework.
>>
>>>>>
>>>>> Otherwise software will report the polarity as normal when it it is
>>>>> actually inversed.
>>>>>
>>>>> Consider the case where a userspace process is controlling the PWM via
>>>>> sysfs.
>>>>>
>>>> I agree with you about the sysfs case Tim, but since this is the probe
>>>> function and not a sysfs callback, should we not leave it as the default
>>>> value?

Re: [PATCH v2 3/4] pwm: kona: Fix enable, disable and config procedures

[Tim Kryger]

On Mon, Dec 1, 2014 at 11:37 AM, Arun Ramamurthy
<arun.ramamurthy@broadcom.com> wrote:
>
>
> On 14-11-28 06:30 PM, Tim Kryger wrote:
>>
>> On Fri, Nov 28, 2014 at 3:49 PM, Arun Ramamurthy
>> <arun.ramamurthy@broadcom.com> wrote:
>>>
>>>
>>>
>>> On 14-11-25 11:29 PM, Tim Kryger wrote:
>>>>
>>>>
>>>> On Tue, Nov 25, 2014 at 11:40 AM, Scott Branden <sbranden@broadcom.com>
>>>> wrote:
>>>>>
>>>>>
>>>>> From: Arun Ramamurthy <arunrama@broadcom.com>
>>>>>
>>>>> - Added helper functions to set and clear smooth and trigger bits
>>>>> - Added 400ns delays when clearing and setting trigger bit as requied
>>>>>     by spec
>>>>> - Added helper function to write prescale and other settings
>>>>> - Updated config procedure to match spec
>>>>> - Added code to handle pwn config when channel is disabled
>>>>> - Updated disable procedure to match spec
>>>>>
>>>>> Signed-off-by: Arun Ramamurthy <arunrama@broadcom.com>
>>>>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>>>>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>>>>> ---
>>>>>    drivers/pwm/pwm-bcm-kona.c | 100
>>>>> +++++++++++++++++++++++++++++++++++----------
>>>>>    1 file changed, 78 insertions(+), 22 deletions(-)
>>>>
>>>>
>>>>
>>>> The driver is fairly small and this change rewrites a considerable
>>>> amount
>>>> of it.
>>>>
>>>> Is there a actually specific deficiency that this change is intended to
>>>> address?
>>>>
>>> The main issue this patchset addresses is setting the period and duty
>>> cycle
>>> when the pwm is disabled. This is done by turning on the clock and
>>> writing
>>> to the PWM registers. Additionally it also adds the 400ns
>>> delays specified by the PWM spec when setting or clearing certain bits.
>>> It
>>> also updates the PWM programming procedure to match the spec more
>>> closely.
>>> Although there is considerable change, all of it addresses the core
>>> functionality and it would not make sense to split it into multiple
>>> patches.
>>
>>
>> So what you are saying is that there isn't any known issue that this
>> resolves.
>>
>> This only changes the driver to use an alternate programming sequence?
>>
>> The benefit here seems uncertain.
>>
> Actually Tim, it addresses the bug where period and duty cycle are not set
> if the PWM channel is not enabled in sysfs. Following up on your example you
> provided in your other email:
>
> # Disable PWM
> echo 0 > enable
>
> # Change to a 25% duty output when PWM is enabled
> echo 25000 > duty_cycle
>
> The original code would not write this duty cycle change to the registers as
> the PWmF_ENABLED bit is not set and the clocks are turned off.

You are mistaken.  There is no bug here.  This is by design.

A subsequent enable results in the requested duty and period being set.

> I can remove all the helper functions and address only this particular bug
> if you prefer that.
>
>>>
>>>> I'm not sure all the extra helper functions improve readability.
>>>>
>>> There was a lot of repeated code in various different functions. It
>>> seemed
>>> more efficient to consolidate them into helper functions. It also helped
>>> when comparing the spec to the code to check if we were
>>> setting the bits in the right order.
>>>
>>>
>>>>>
>>>>> diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
>>>>> index fa0b5bf..06fa983 100644
>>>>> --- a/drivers/pwm/pwm-bcm-kona.c
>>>>> +++ b/drivers/pwm/pwm-bcm-kona.c
>>>>> @@ -65,6 +65,10 @@
>>>>>    #define DUTY_CYCLE_HIGH_MIN                    (0x00000000)
>>>>>    #define DUTY_CYCLE_HIGH_MAX                    (0x00ffffff)
>>>>>
>>>>> +/* The delay required after clearing or setting
>>>>> +   PWMOUT_ENABLE*/
>>>>> +#define PWMOUT_ENABLE_HOLD_DELAY 400
>>>>> +
>>>>>    struct kona_pwmc {
>>>>>           struct pwm_chip chip;
>>>>>           void __iomem *base;
>>>>> @@ -76,28 +80,70 @@ static inline struct kona_pwmc *to_kona_pwmc(struct
>>>>> pwm_chip *_chip)
>>>>>           return container_of(_chip, struct kona_pwmc, chip);
>>>>>    }
>>>>>
>>>>> -static void kona_pwmc_apply_settings(struct kona_pwmc *kp, unsigned
>>>>> int
>>>>> chan)
>>>>> +static inline void kona_pwmc_set_trigger(struct kona_pwmc *kp,
>>>>> +                                        unsigned int chan)
>>>>>    {
>>>>>           unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
>>>>>
>>>>> -       /* Clear trigger bit but set smooth bit to maintain old output
>>>>> */
>>>>> -       value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);
>>>>> +       /* set trigger bit to enable channel */
>>>>> +       value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
>>>>> +       writel(value, kp->base + PWM_CONTROL_OFFSET);
>>>>> +       ndelay(PWMOUT_ENABLE_HOLD_DELAY);
>>>>> +}
>>>>> +static inline void kona_pwmc_clear_trigger(struct kona_pwmc *kp,
>>>>> +                                          unsigned int chan)
>>>>> +{
>>>>> +       unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
>>>>> +
>>>>> +       /* Clear trigger bit */
>>>>>           value &= ~(1 << PWM_CONTROL_TRIGGER_SHIFT(chan));
>>>>>           writel(value, kp->base + PWM_CONTROL_OFFSET);
>>>>> +       ndelay(PWMOUT_ENABLE_HOLD_DELAY);
>>>>> +}
>>>>>
>>>>> -       /* Set trigger bit and clear smooth bit to apply new settings
>>>>> */
>>>>> +static inline void kona_pwmc_clear_smooth(struct kona_pwmc *kp,
>>>>> +                                         unsigned int chan)
>>>>> +{
>>>>> +       unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
>>>>> +
>>>>> +       /* Clear smooth bit */
>>>>>           value &= ~(1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
>>>>> -       value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
>>>>>           writel(value, kp->base + PWM_CONTROL_OFFSET);
>>>>>    }
>>>>>
>>>>> +static inline void kona_pwmc_set_smooth(struct kona_pwmc *kp, unsigned
>>>>> int chan)
>>>>> +{
>>>>> +       unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
>>>>> +
>>>>> +       /*  set smooth bit to maintain old output */
>>>>> +       value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);
>>>>> +       writel(value, kp->base + PWM_CONTROL_OFFSET);
>>>>> +}
>>>>> +
>>>>> +static void kona_pwmc_write_settings(struct kona_pwmc *kp, unsigned
>>>>> int
>>>>> chan,
>>>>> +                                    unsigned long prescale, unsigned
>>>>> long pc,
>>>>> +                                    unsigned long dc)
>>>>> +{
>>>>> +       unsigned int value;
>>>>> +
>>>>> +       value = readl(kp->base + PRESCALE_OFFSET);
>>>>> +       value &= ~PRESCALE_MASK(chan);
>>>>> +       value |= prescale << PRESCALE_SHIFT(chan);
>>>>> +       writel(value, kp->base + PRESCALE_OFFSET);
>>>>> +
>>>>> +       writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
>>>>> +
>>>>> +       writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
>>>>> +
>>>>> +}
>>>>> +
>>>>>    static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device
>>>>> *pwm,
>>>>>                               int duty_ns, int period_ns)
>>>>>    {
>>>>>           struct kona_pwmc *kp = to_kona_pwmc(chip);
>>>>>           u64 val, div, rate;
>>>>>           unsigned long prescale = PRESCALE_MIN, pc, dc;
>>>>> -       unsigned int value, chan = pwm->hwpwm;
>>>>> +       unsigned int ret, chan = pwm->hwpwm;
>>>>>
>>>>>           /*
>>>>>            * Find period count, duty count and prescale to suit duty_ns
>>>>> and
>>>>> @@ -133,19 +179,30 @@ static int kona_pwmc_config(struct pwm_chip
>>>>> *chip,
>>>>> struct pwm_device *pwm,
>>>>>                           return -EINVAL;
>>>>>           }
>>>>>
>>>>> -       /* If the PWM channel is enabled, write the settings to the HW
>>>>> */
>>>>> -       if (test_bit(PWMF_ENABLED, &pwm->flags)) {
>>>>> -               value = readl(kp->base + PRESCALE_OFFSET);
>>>>> -               value &= ~PRESCALE_MASK(chan);
>>>>> -               value |= prescale << PRESCALE_SHIFT(chan);
>>>>> -               writel(value, kp->base + PRESCALE_OFFSET);
>>>>>
>>>>> -               writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
>>>>> +       /* If the PWM channel is not enabled, enable the clock */
>>>>> +       if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
>>>>> +               ret = clk_prepare_enable(kp->clk);
>>>>> +               if (ret < 0) {
>>>>> +                       dev_err(chip->dev, "failed to enable clock:
>>>>> %d\n", ret);
>>>>> +                       return ret;
>>>>> +               }
>>>>> +       }
>>>>>
>>>>> -               writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
>>>>> +       /* Set smooth bit to maintain old output */
>>>>> +       kona_pwmc_set_smooth(kp, chan);
>>>>> +       kona_pwmc_clear_trigger(kp, chan);
>>>>> +
>>>>> +       /* apply new settings */
>>>>> +       kona_pwmc_write_settings(kp, chan, prescale, pc, dc);
>>>>> +
>>>>> +       /*If the PWM is enabled, enable the channel with the new
>>>>> settings
>>>>> +        and if not  disable the clock*/
>>>>> +       if (test_bit(PWMF_ENABLED, &pwm->flags))
>>>>> +               kona_pwmc_set_trigger(kp, chan);
>>>>> +       else
>>>>> +               clk_disable_unprepare(kp->clk);
>>>>>
>>>>> -               kona_pwmc_apply_settings(kp, chan);
>>>>> -       }
>>>>>
>>>>>           return 0;
>>>>>    }
>>>>> @@ -188,7 +245,6 @@ static int kona_pwmc_enable(struct pwm_chip *chip,
>>>>> struct pwm_device *pwm)
>>>>>                   dev_err(chip->dev, "failed to enable clock: %d\n",
>>>>> ret);
>>>>>                   return ret;
>>>>>           }
>>>>> -
>>>>>           ret = kona_pwmc_config(chip, pwm, pwm->duty_cycle,
>>>>> pwm->period);
>>>>>           if (ret < 0) {
>>>>>                   clk_disable_unprepare(kp->clk);
>>>>> @@ -203,12 +259,12 @@ static void kona_pwmc_disable(struct pwm_chip
>>>>> *chip, struct pwm_device *pwm)
>>>>>           struct kona_pwmc *kp = to_kona_pwmc(chip);
>>>>>           unsigned int chan = pwm->hwpwm;
>>>>>
>>>>> +       kona_pwmc_clear_smooth(kp, chan);
>>>>> +       kona_pwmc_clear_trigger(kp, chan);
>>>>
>>>>
>>>>
>>>> I believe the output will spike high here.  Likely not what you want...
>>>
>>>
>>>
>>> According to spec, this is the procedure to program the PWM and the code
>>> follows that:
>>>
>>> STEP0: Program SMOOTH_TYPE=1. That will only allow changing of PWM
>>> setting
>>> at the PWM period boundary.
>>>   STEP1: Program PWMOUT_ENABLE=0. At this time, PWM internal logic will
>>> continue to run with the previous settings. (i.e. If PWM is at 50Hz 40%
>>> duty
>>> cycle before, during the time when PWMOUT_ENABLE=0, it will still run at
>>> 50MHz 40% duty cycle.)
>>>   STEP2: Program PWM register for new setting (i.e. PRESCALE, DUTY,
>>> PERIOD
>>> etc)
>>>   STEP3: Program PWMOUT_ENABLE=1. That will load the new PWM setting from
>>> APB
>>> into PWM internal register. (Note. Minimum of 400ns is needed between
>>> step1
>>> and step3. )
>>>   STEP4: Keep PWMOUT ENABLE=1. (Note: If user didn't hold PWMOUT_ENABLE=1
>>> for
>>> longer than 400ns, PWM internal logic will discard the new PWM setting in
>>> step2. User should hold the PWMOUT_ENABLE=1 unless new PWM settings is
>>> needed.)
>>>
>>>
>>>
>>>>
>>>>>           /* Simulate a disable by configuring for zero duty */
>>>>> -       writel(0, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
>>>>> -       kona_pwmc_apply_settings(kp, chan);
>>>>> -
>>>>> -       /* Wait for waveform to settle before gating off the clock */
>>>>> -       ndelay(400);
>>>>> +       kona_pwmc_write_settings(kp, chan, 0, 0, 0);
>>>>> +       kona_pwmc_set_polarity(chip, pwm, PWM_POLARITY_NORMAL);
>>>>
>>>>
>>>>
>>>> This is wrong.  You shouldn't change the polarity when the PWM is
>>>> disabled.
>>>>
>>>> The original polarity isn't even restored when it is re-enabled...
>>>>
>>> this is procedure from the PWM spec to disable :
>>>
>>> STEP0: Program SMOOTH_TYPE=0.
>>>   STEP1: Program PWMOUT_ENABLE=0. Now, PWM internal logic will be at
>>> reset,
>>> PWM output will be default at 1.
>>
>>
>> This is exactly what I was saying before.  You glitch the output high
>> for no good reason.
>>
>> The sequence in the document isn't gospel.  From what I recall, it was
>> just a verification engineer's best guess at how to get a very unusual
>> PWM controller to do the normal PWM things.
>
>
> So to summarize, you would prefer that the disable procedure be left
> unchanged which is to set the duty cycle to zero.

I would be much more likely to give my approval to a patch that
identified a specific issue and resolved it without unnecessarily
rewriting large parts of the driver.

>
>>
>>>   STEP2: Program PWM register to these setting. PRESCALE=0, POLARITY=1,
>>> DUTY=0, PERIOD=0.
>>>   STEP3: Program PWMOUT_ENABLE=1, and Keep SMOOTH_TYPE=0.
>>>   STEP4: Turn off PWM clock from CCU, and Keep PWMOUT ENABLE=1. (Note, It
>>> takes 400ns from STEP3 to turn off the LCD backlight, and user should
>>> guarantee that the PWM clock will not be disabled in less than 400ns
>>> after
>>> STEP3.
>>>
>>> I agree with you that the original polarity isnt restored. I will need to
>>> add some code to check the syfs polarity value when the PWM is enabled.
>>> However, if i was to comply with the above spec, I would still have set
>>> the
>>> polarity. I just realized it should be set to inverted and I will fix
>>> this
>>> in the next patchset
>>>
>>>
>>>>> +       kona_pwmc_set_trigger(kp, chan);
>>>>>
>>>>>           clk_disable_unprepare(kp->clk);
>>>>>    }
>>>>> --
>>>>> 2.1.3
>>>>>
>>>
>

Re: [PATCH v2 1/4] pwm: kona: Remove setting default smooth type and polarity for all channels

[Jonathan Richardson]

Hi Tim,

I'm going to take over this submission because I made the changes to the
driver. Arun was filling in for me while I was on leave. Now I'm back
and I think I can help clarify why these changes were made. A summary
for all the changes should help.

There were two problems. First was a problem caused by setting the
polarity in probe. It caused the speaker to click when the polarity was
set so we took that out as it didn't seem to serve any useful purpose
that I could see. The polarity changes should be made in the polarity
callback.

The second and bigger problem was the smooth type sequence. If it isn't
done according to the spec then one in ten or twenty times you won't
even get a signal when it's enabled. Following the correct sequence with
the 400 ns delays solves this problem.

Additionally, by not following the sequence you won't get a smooth
transition. You'll get a change in the settings (duty cycle, period) but
may get a non smooth transition. So it's important to follow the spec
here. We don't want non-smooth transitions.

More comments below.

On 14-11-28 07:19 PM, Tim Kryger wrote:
> On Fri, Nov 28, 2014 at 5:19 PM, Arun Ramamurthy
> <arun.ramamurthy@broadcom.com> wrote:
>>
>>
>> On 14-11-28 05:08 PM, Tim Kryger wrote:
>>>
>>> On Fri, Nov 28, 2014 at 3:47 PM, Arun Ramamurthy
>>> <arun.ramamurthy@broadcom.com> wrote:
>>>>
>>>>
>>>>
>>>> On 14-11-25 09:51 PM, Tim Kryger wrote:
>>>>>
>>>>>
>>>>> On Tue, Nov 25, 2014 at 11:40 AM, Scott Branden <sbranden@broadcom.com>
>>>>> wrote:
>>>>>>
>>>>>>
>>>>>> From: Arun Ramamurthy <arunrama@broadcom.com>
>>>>>>
>>>>>> The probe routine unnecessarily sets the smooth type and polarity for
>>>>>> all channels. This causes the channel for the speaker to click at the
>>>>>> same
>>>>>> time the backlight turns on. The smooth type and polarity should be set
>>>>>> individually
>>>>>> for each channel as required and no defaults need to be set.
>>>>>
>>>>>
>>>>>
>>>>> I am guessing you are talking about a PWM controlled beeper/buzzer.
>>>>>
>>>> This change is more so to remove setting smooth type and polarity for all
>>>> channels during probe and to leave them as their default values. Infact,
>>>> setting the PWM_CONTROL_TYPE_SHIT is also redundant cause the default
>>>> value
>>>> is already 1 for all channels. We can remove that loop entirely and this
>>>> will be done in the next patch set. The smooth type and polarity are only
>>>> changed when the particular pwm channel is enabled or polarity is
>>>> changed.
>>>>
>>>>> Can you mention what board you are observing this issue on?
>>>>>
>>>>> Also please explain why setting these bits result in an audible click.
>>>>>
>>>> We observe this on the bcm958300K board where one of the
>>>> PWM channels is connected to the buzzer and changing the
>>>> smooth type and polarity from its default values causes a click
>>>>
>>>
>>> Which of these two bits is causing the click?
>>>
>>> I've already said that I'm open to removing the smooth bit here if that
>>> helps.
>>>
>> Thank you for your quick reply Tim. It is setting the polarity bit that
>> causes the click. I am planning on removing this entire loop in the next
>> patch set, are you okay with that?
> 
> Does it cause a click at this moment or at a later point in time?
> 
> Is the click your sole motivation for this series?  If so, can you
> propose a more targeted fix?
> 
> I would be amenable to deferring polarity changes until subsequent
> enable operations:
> 
> - kona_pwmc_probe doesn't do any hardware writes
> - kona_pwmc_set_polarity only updates a polarity variable
> - kona_pwmc_enable sets hardware polarity according to the variable
> 
> Would this be sufficient to satisfy your needs?
> 
> I am still worried that deferring polarity changes may negatively
> impact some PWM users who set polarity but don't immediately enable
> the PWM.
> 
>>>>>>
>>>>>> Signed-off-by: Arun Ramamurthy <arunrama@broadcom.com>
>>>>>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>>>>>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>>>>>> ---
>>>>>>    drivers/pwm/pwm-bcm-kona.c | 7 ++-----
>>>>>>    1 file changed, 2 insertions(+), 5 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
>>>>>> index 02bc048..29eef9e 100644
>>>>>> --- a/drivers/pwm/pwm-bcm-kona.c
>>>>>> +++ b/drivers/pwm/pwm-bcm-kona.c
>>>>>> @@ -266,12 +266,9 @@ static int kona_pwmc_probe(struct platform_device
>>>>>> *pdev)
>>>>>>                   return ret;
>>>>>>           }
>>>>>>
>>>>>> -       /* Set smooth mode, push/pull, and normal polarity for all
>>>>>> channels */
>>>>>> -       for (chan = 0; chan < kp->chip.npwm; chan++) {
>>>>>> -               value |= (1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
>>>>>> +       /* Set push/pull for all channels */
>>>>>> +       for (chan = 0; chan < kp->chip.npwm; chan++)
>>>>>>                   value |= (1 << PWM_CONTROL_TYPE_SHIFT(chan));
>>>>>> -               value |= (1 << PWM_CONTROL_POLARITY_SHIFT(chan));
>>>>>> -       }
>>>>>>
>>>>>>           writel(value, kp->base + PWM_CONTROL_OFFSET);
>>>>>
>>>>>
>>>>>
>>>>> While the smooth bit need not be set here, it is important that the
>>>>> polarity bit be set.
>>>>>
>>>> The default value for polarity is 0 which is normal polarity, so setting
>>>> it
>>>> to 1 here in the probe function without a sysfs call is
>>>> when the software will report the polarity as normal when it is actually
>>>> inversed.
>>>
>>>
>>> Please double check the meaning of the polarity bits for the revision
>>> of PWM IP in your chip.  I suspect you are mistaken here.
>>>
>>> This driver is for PWM blocks compatible those found in bcm28145,
>>> bcm28155, bcm21664, and other mobile chips of that generation.
>>>
>>> Apparently in contrast to the chip you are using, a set polarity bit
>>> in the control register means normal polarity for the chips I
>>> mentioned.
>>>
>>> A default of zero for these bits means they must be set to meet the
>>> PWM framework's expectation that channels begin with normal polarity.
>>>
>> Tim, this is from the RDB of our new chip which is supposed to have the same
>> IP as the mobile chip sets you mentioned:
>>
>> When set to 1 the output polarity for the PWM Output signal will be active
>> hight; When set to 0, the output polarity for the PWM Output signal will be
>> active low. Default State is 0.
>>
>> My understanding is that the frameworks normal polarity means active low, am
>> I mistaken in that?
> 
> That is not how I would interpret things.
> 
> Perhaps this paragraph from Documentation/pwm.txt will help you:
> 
> When implementing polarity support in a PWM driver, make sure to respect the
> signal conventions in the PWM framework. By definition, normal polarity
> characterizes a signal starts high for the duration of the duty cycle and
> goes low for the remainder of the period. Conversely, a signal with inversed
> polarity starts low for the duration of the duty cycle and goes high for the
> remainder of the period.
> 

Agreed. When using DT, the polarity will be set properly. When using
sysfs there is a discrepancy and this needs to be addressed. Because the
hw default is active low, the polarity will be inversed when the sysfs
says polarity is "normal". I'll have to account for this in the driver.

>>
>>>>>
>>>>> Otherwise software will report the polarity as normal when it it is
>>>>> actually inversed.
>>>>>
>>>>> Consider the case where a userspace process is controlling the PWM via
>>>>> sysfs.
>>>>>
>>>> I agree with you about the sysfs case Tim, but since this is the probe
>>>> function and not a sysfs callback, should we not leave it as the default
>>>> value?
> --
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> 

Re: [PATCH v2 3/4] pwm: kona: Fix enable, disable and config procedures

[Jonathan Richardson]

Hi Tim,

Comments below.

On 14-11-25 11:29 PM, Tim Kryger wrote:
> On Tue, Nov 25, 2014 at 11:40 AM, Scott Branden <sbranden@broadcom.com> wrote:
>> From: Arun Ramamurthy <arunrama@broadcom.com>
>>
>> - Added helper functions to set and clear smooth and trigger bits
>> - Added 400ns delays when clearing and setting trigger bit as requied
>>   by spec
>> - Added helper function to write prescale and other settings
>> - Updated config procedure to match spec
>> - Added code to handle pwn config when channel is disabled
>> - Updated disable procedure to match spec
>>
>> Signed-off-by: Arun Ramamurthy <arunrama@broadcom.com>
>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>> ---
>>  drivers/pwm/pwm-bcm-kona.c | 100 +++++++++++++++++++++++++++++++++++----------
>>  1 file changed, 78 insertions(+), 22 deletions(-)
> 
> The driver is fairly small and this change rewrites a considerable amount of it.
> 
> Is there a actually specific deficiency that this change is intended to address?
> 
> I'm not sure all the extra helper functions improve readability.
> 

Hopefully my summary in the previous reply helps clarify. I'm going to
remove all the helper functions to make the changes as simple as possible.

>>
>> diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
>> index fa0b5bf..06fa983 100644
>> --- a/drivers/pwm/pwm-bcm-kona.c
>> +++ b/drivers/pwm/pwm-bcm-kona.c
>> @@ -65,6 +65,10 @@
>>  #define DUTY_CYCLE_HIGH_MIN                    (0x00000000)
>>  #define DUTY_CYCLE_HIGH_MAX                    (0x00ffffff)
>>
>> +/* The delay required after clearing or setting
>> +   PWMOUT_ENABLE*/
>> +#define PWMOUT_ENABLE_HOLD_DELAY 400
>> +
>>  struct kona_pwmc {
>>         struct pwm_chip chip;
>>         void __iomem *base;
>> @@ -76,28 +80,70 @@ static inline struct kona_pwmc *to_kona_pwmc(struct pwm_chip *_chip)
>>         return container_of(_chip, struct kona_pwmc, chip);
>>  }
>>
>> -static void kona_pwmc_apply_settings(struct kona_pwmc *kp, unsigned int chan)
>> +static inline void kona_pwmc_set_trigger(struct kona_pwmc *kp,
>> +                                        unsigned int chan)
>>  {
>>         unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
>>
>> -       /* Clear trigger bit but set smooth bit to maintain old output */
>> -       value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);
>> +       /* set trigger bit to enable channel */
>> +       value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
>> +       writel(value, kp->base + PWM_CONTROL_OFFSET);
>> +       ndelay(PWMOUT_ENABLE_HOLD_DELAY);
>> +}
>> +static inline void kona_pwmc_clear_trigger(struct kona_pwmc *kp,
>> +                                          unsigned int chan)
>> +{
>> +       unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
>> +
>> +       /* Clear trigger bit */
>>         value &= ~(1 << PWM_CONTROL_TRIGGER_SHIFT(chan));
>>         writel(value, kp->base + PWM_CONTROL_OFFSET);
>> +       ndelay(PWMOUT_ENABLE_HOLD_DELAY);
>> +}
>>
>> -       /* Set trigger bit and clear smooth bit to apply new settings */
>> +static inline void kona_pwmc_clear_smooth(struct kona_pwmc *kp,
>> +                                         unsigned int chan)
>> +{
>> +       unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
>> +
>> +       /* Clear smooth bit */
>>         value &= ~(1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
>> -       value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
>>         writel(value, kp->base + PWM_CONTROL_OFFSET);
>>  }
>>
>> +static inline void kona_pwmc_set_smooth(struct kona_pwmc *kp, unsigned int chan)
>> +{
>> +       unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET);
>> +
>> +       /*  set smooth bit to maintain old output */
>> +       value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan);
>> +       writel(value, kp->base + PWM_CONTROL_OFFSET);
>> +}
>> +
>> +static void kona_pwmc_write_settings(struct kona_pwmc *kp, unsigned int chan,
>> +                                    unsigned long prescale, unsigned long pc,
>> +                                    unsigned long dc)
>> +{
>> +       unsigned int value;
>> +
>> +       value = readl(kp->base + PRESCALE_OFFSET);
>> +       value &= ~PRESCALE_MASK(chan);
>> +       value |= prescale << PRESCALE_SHIFT(chan);
>> +       writel(value, kp->base + PRESCALE_OFFSET);
>> +
>> +       writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
>> +
>> +       writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
>> +
>> +}
>> +
>>  static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm,
>>                             int duty_ns, int period_ns)
>>  {
>>         struct kona_pwmc *kp = to_kona_pwmc(chip);
>>         u64 val, div, rate;
>>         unsigned long prescale = PRESCALE_MIN, pc, dc;
>> -       unsigned int value, chan = pwm->hwpwm;
>> +       unsigned int ret, chan = pwm->hwpwm;
>>
>>         /*
>>          * Find period count, duty count and prescale to suit duty_ns and
>> @@ -133,19 +179,30 @@ static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm,
>>                         return -EINVAL;
>>         }
>>
>> -       /* If the PWM channel is enabled, write the settings to the HW */
>> -       if (test_bit(PWMF_ENABLED, &pwm->flags)) {
>> -               value = readl(kp->base + PRESCALE_OFFSET);
>> -               value &= ~PRESCALE_MASK(chan);
>> -               value |= prescale << PRESCALE_SHIFT(chan);
>> -               writel(value, kp->base + PRESCALE_OFFSET);
>>
>> -               writel(pc, kp->base + PERIOD_COUNT_OFFSET(chan));
>> +       /* If the PWM channel is not enabled, enable the clock */
>> +       if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
>> +               ret = clk_prepare_enable(kp->clk);
>> +               if (ret < 0) {
>> +                       dev_err(chip->dev, "failed to enable clock: %d\n", ret);
>> +                       return ret;
>> +               }
>> +       }
>>
>> -               writel(dc, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
>> +       /* Set smooth bit to maintain old output */
>> +       kona_pwmc_set_smooth(kp, chan);
>> +       kona_pwmc_clear_trigger(kp, chan);
>> +
>> +       /* apply new settings */
>> +       kona_pwmc_write_settings(kp, chan, prescale, pc, dc);
>> +
>> +       /*If the PWM is enabled, enable the channel with the new settings
>> +        and if not  disable the clock*/
>> +       if (test_bit(PWMF_ENABLED, &pwm->flags))
>> +               kona_pwmc_set_trigger(kp, chan);
>> +       else
>> +               clk_disable_unprepare(kp->clk);
>>
>> -               kona_pwmc_apply_settings(kp, chan);
>> -       }
>>
>>         return 0;
>>  }
>> @@ -188,7 +245,6 @@ static int kona_pwmc_enable(struct pwm_chip *chip, struct pwm_device *pwm)
>>                 dev_err(chip->dev, "failed to enable clock: %d\n", ret);
>>                 return ret;
>>         }
>> -
>>         ret = kona_pwmc_config(chip, pwm, pwm->duty_cycle, pwm->period);
>>         if (ret < 0) {
>>                 clk_disable_unprepare(kp->clk);
>> @@ -203,12 +259,12 @@ static void kona_pwmc_disable(struct pwm_chip *chip, struct pwm_device *pwm)
>>         struct kona_pwmc *kp = to_kona_pwmc(chip);
>>         unsigned int chan = pwm->hwpwm;
>>
>> +       kona_pwmc_clear_smooth(kp, chan);
>> +       kona_pwmc_clear_trigger(kp, chan);
> 
> I believe the output will spike high here.  Likely not what you want...
> 
>>         /* Simulate a disable by configuring for zero duty */
>> -       writel(0, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan));
>> -       kona_pwmc_apply_settings(kp, chan);
>> -
>> -       /* Wait for waveform to settle before gating off the clock */
>> -       ndelay(400);
>> +       kona_pwmc_write_settings(kp, chan, 0, 0, 0);
>> +       kona_pwmc_set_polarity(chip, pwm, PWM_POLARITY_NORMAL);
> 
> This is wrong.  You shouldn't change the polarity when the PWM is disabled.

Agreed. No need to set polarity on disable.

> 
> The original polarity isn't even restored when it is re-enabled...
> 
>> +       kona_pwmc_set_trigger(kp, chan);
>>
>>         clk_disable_unprepare(kp->clk);
>>  }
>> --
>> 2.1.3
>>
> --
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> Please read the FAQ at  http://www.tux.org/lkml/
> 

Re: [PATCH v2 2/4] pwm: kona: Fix incorrect enable after channel polarity change

[Jonathan Richardson]

Comments below.

On 14-11-28 06:02 PM, Tim Kryger wrote:
> On Fri, Nov 28, 2014 at 3:48 PM, Arun Ramamurthy
> <arun.ramamurthy@broadcom.com> wrote:
>>
>>
>> On 14-11-25 10:22 PM, Tim Kryger wrote:
>>>
>>> On Tue, Nov 25, 2014 at 11:40 AM, Scott Branden <sbranden@broadcom.com>
>>> wrote:
>>>>
>>>> From: Arun Ramamurthy <arunrama@broadcom.com>
>>>>
>>>> The pwm core code requires a separate call for enabling the channel
>>>> and hence the driver does not need to set pwm_trigger after a
>>>> polarity change
>>>
>>>
>>> The framework does restrict when polarity changes can occur but it
>>> isn't clear to me that there is any reason to delay applying the
>>> polarity change.
>>
>> I examined several other drivers such as pwm-atmel-tcb.c, pwm-ep93xx.c,
>> pwm-renesas-tpu.c, pwm-samsung.c in the 3.17 kernel tree and none of them
>> enable the channel after changing polarity. We would be the first driver to
>> do so.
> 
> We are not "enabling" the channel as much as we are "triggering an
> application of settings" by hardware.
> 
> Both pwm-ep93xx and pwm-samsung write polarity settings to the
> hardware immediately, presumably resulting in an immediate change in
> output.
> 
> Alternatively, the pwm-atmel-tcb and pwm-renesas-tpu drivers save the
> polarity and write it to hardware later.
> 
> There may be advantages to deferring the application of the polarity
> till a subsequent enable but both approaches appear to be acceptable.
> 
>>
>>> Keep in mind that polarity matters even when a PWM
>>> is disabled.  While disabled, the output should be equivalent to an
>>> enabled configuration with zero duty.  Thus for normal polarity the
>>> output is constant low and for inversed polarity the output is
>>> constant high.
>>
>> The driver does set the duty cycle to zero when disabling the pwm
>> channel.However since the frame work prevents polarity change when the pwm
>> is enabled, I don’t see how one could expect the polarity change to be
>> reflected immediately without a separate call to pwm enable.
>>
>>
>>> I believe there is an expectation that the output is
>>> updated to reflect the requested polarity change prior to returning to
>>> the caller.
>>
>>
>> Once again I disagree with this based on other pwm drivers which only change
>> the polarity and do not enable the channel when their set polarity functions
>> are called.
> 
> I don't know why you keep calling this an enable.  Its not an enable,
> it is only a trigger.
> 
> Perhaps this would be best explained with an example:
> 
> # Export PWM for access by userspace
> cd /sys/class/pwm/pwmchip0
> echo 0 > export
> cd pwm0
> 
> # Request 50% duty output when PWM is enabled
> echo 50000 > duty_cycle
> echo 100000 > period
> 
> # Command Inversed Polarity
> echo inversed > polarity
> 
> # Command Normal Polarity
> echo normal > polarity
> 
> # Enable PWM
> echo 1 > enable
> 
> The polarity changes trigger immediate output updates but the PWM is
> not enabled until the end.
> 
> Prior to the last step the output is either a constant high or low
> signal, not the 50% duty waveform.
> 

I just want to clarify so we're on the same page here. The pwm channel
needs to be disabled when polarity is set. When the set polarity
callback is called it just needs to update the polarity so that when the
channel is enabled again the new polarity value is used. We write this
to the polarity register in the callback which seems appropriate. Also
note that the clock is disabled at the end of the routine so the signal
is just going to be floating anyway. Hopefully this makes sense.


>>
>>
>>>
>>>>
>>>> Signed-off-by: Arun Ramamurthy <arunrama@broadcom.com>
>>>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>>>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>>>> ---
>>>>   drivers/pwm/pwm-bcm-kona.c | 5 -----
>>>>   1 file changed, 5 deletions(-)
>>>>
>>>> diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
>>>> index 29eef9e..fa0b5bf 100644
>>>> --- a/drivers/pwm/pwm-bcm-kona.c
>>>> +++ b/drivers/pwm/pwm-bcm-kona.c
>>>> @@ -173,11 +173,6 @@ static int kona_pwmc_set_polarity(struct pwm_chip
>>>> *chip, struct pwm_device *pwm,
>>>>
>>>>          writel(value, kp->base + PWM_CONTROL_OFFSET);
>>>>
>>>> -       kona_pwmc_apply_settings(kp, chan);
>>>> -
>>>> -       /* Wait for waveform to settle before gating off the clock */
>>>> -       ndelay(400);
>>>> -
>>>>          clk_disable_unprepare(kp->clk);
>>>>
>>>>          return 0;
>>>> --
>>>> 2.1.3
>>>>
>>
> --
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> Please read the FAQ at  http://www.tux.org/lkml/
> 

[PATCH] mtd: add reboot notifier to mtdcore and register nand_shutdown with notifier

[Scott Branden]

add (optional) reboot notifier field to struct mtd_info, and use it to
register a system reboot notifier on behalf of the lower layers.

Add nand_shutdown to wait for current nand operations to finish and prevent
further operations by changing the nand flash state to FL_SHUTDOWN.
Register the nand_shutdown with the reboot notifier in nand_base.c

This is addressing a problem observed during reboot tests using UBIFS
root file system: NAND erase operations that are in progress during
system reboot/shutdown are causing partial erased blocks. Although UBI should
be able to detect and recover from this error, this change will avoid
the creation of partial erased blocks on reboot in the middle of a NAND erase
operation.

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Corneliu Doban <cdoban@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/mtd/mtdcore.c        | 20 ++++++++++++++++++++
 drivers/mtd/nand/nand_base.c | 11 +++++++++++
 include/linux/mtd/mtd.h      |  1 +
 3 files changed, 32 insertions(+)

diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c
index 4c61187..b80d44f 100644
--- a/drivers/mtd/mtdcore.c
+++ b/drivers/mtd/mtdcore.c
@@ -37,6 +37,7 @@
 #include <linux/backing-dev.h>
 #include <linux/gfp.h>
 #include <linux/slab.h>
+#include <linux/reboot.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
@@ -365,6 +366,17 @@ static struct device_type mtd_devtype = {
 	.release	= mtd_release,
 };
 
+static int mtd_reboot_notifier(struct notifier_block *n, unsigned long state,
+			       void *cmd)
+{
+       struct mtd_info *mtd;
+
+       mtd = container_of(n, struct mtd_info, reboot_notifier);
+       mtd->_reboot(mtd);
+
+       return NOTIFY_DONE;
+}
+
 /**
  *	add_mtd_device - register an MTD device
  *	@mtd: pointer to new MTD device info structure
@@ -565,6 +577,11 @@ int mtd_device_parse_register(struct mtd_info *mtd, const char * const *types,
 			err = -ENODEV;
 	}
 
+	if (mtd->_reboot) {
+		mtd->reboot_notifier.notifier_call = mtd_reboot_notifier;
+		register_reboot_notifier(&mtd->reboot_notifier);
+	}
+
 	return err;
 }
 EXPORT_SYMBOL_GPL(mtd_device_parse_register);
@@ -579,6 +596,9 @@ int mtd_device_unregister(struct mtd_info *master)
 {
 	int err;
 
+	if (master->_reboot)
+		unregister_reboot_notifier(&master->reboot_notifier);
+
 	err = del_mtd_partitions(master);
 	if (err)
 		return err;
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 5b5c627..e18165b 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2944,6 +2944,16 @@ static void nand_resume(struct mtd_info *mtd)
 			__func__);
 }
 
+/**
+ * nand_shutdown - [MTD Interface] Finish the current NAND operation and
+ *                 prevent further operations
+ * @mtd: MTD device structure
+ */
+static void nand_shutdown(struct mtd_info *mtd)
+{
+	nand_get_device(mtd, FL_SHUTDOWN);
+}
+
 /* Set default functions */
 static void nand_set_defaults(struct nand_chip *chip, int busw)
 {
@@ -4146,6 +4156,7 @@ int nand_scan_tail(struct mtd_info *mtd)
 	mtd->_unlock = NULL;
 	mtd->_suspend = nand_suspend;
 	mtd->_resume = nand_resume;
+	mtd->_reboot = nand_shutdown;
 	mtd->_block_isreserved = nand_block_isreserved;
 	mtd->_block_isbad = nand_block_isbad;
 	mtd->_block_markbad = nand_block_markbad;
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 031ff3a..c06f537 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -227,6 +227,7 @@ struct mtd_info {
 	int (*_block_markbad) (struct mtd_info *mtd, loff_t ofs);
 	int (*_suspend) (struct mtd_info *mtd);
 	void (*_resume) (struct mtd_info *mtd);
+	void (*_reboot) (struct mtd_info *mtd);
 	/*
 	 * If the driver is something smart, like UBI, it may need to maintain
 	 * its own reference counting. The below functions are only for driver.
-- 
2.2.0

Re: [PATCH] mtd: nand: added nand_shutdown

[Scott Branden]

Hi Brian,

I just sent out a new patch with your changes incorporated.

Thanks,
  Scott


On 14-11-26 01:10 AM, Brian Norris wrote:
> On Thu, Nov 20, 2014 at 11:18:05AM -0800, Scott Branden wrote:
>> Add nand_shutdown to wait for current nand operations to finish and prevent
>> further operations by changing the nand flash state to FL_SHUTDOWN.
>>
>> This is addressing a problem observed during reboot tests using UBIFS
>> root file system: NAND erase operations that are in progress during
>> system reboot/shutdown are causing partial erased blocks. Although UBI should
>> be able to detect and recover from this error, this change will avoid
>> the creation of partial erased blocks on reboot in the middle of a NAND erase
>> operation.
> [...]
>> diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
>> index e4d451e..80e4367 100644
>> --- a/include/linux/mtd/nand.h
>> +++ b/include/linux/mtd/nand.h
>> @@ -48,6 +48,13 @@ extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
>>   /* unlocks specified locked blocks */
>>   extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
>>
>> +/*
>> + * Internal helper for board drivers which need to make sure that the current
>> + * nand operation is finished and further operations are prevented before
>> + * rebooting the system.
>> + */
>> +extern int nand_shutdown(struct mtd_info *mtd);
>
> I don't think we should push this out to the board drivers. And I
> definitely don't want to merge this function without any user. It'd turn
> out like our useless nand_lock() and nand_unlock() functions.
>
>> +
>>   /* The maximum number of NAND chips in an array */
>>   #define NAND_MAX_CHIPS		8
>>
>
> So, to do this right, I think maybe we should add an (optional)
> reboot_notifier field to struct mtd_info, and use it to register a
> system reboot notifier on behalf of the lower layers. We can do the
> registration in mtd_device_parse_register(), I think, and any
> unregistration in mtd_device_unregister().
>
> With this approach, we can actually move the cfi_cmdset_000{1,2}.c
> reboot notifiers over to the same common code. They just will have to
> fill out their mtd->reboot_notifier field.
>
> How about the following two untested patches?
>
> From: Brian Norris <computersforpeace@gmail.com>
>
> cfi_cmdset_000{1,2}.c already implement their own reboot notifiers, and
> we're going to add one for NAND. Let's put the boilerplate in one place.
>
> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
> ---
>   drivers/mtd/mtdcore.c   | 20 ++++++++++++++++++++
>   include/linux/mtd/mtd.h |  1 +
>   2 files changed, 21 insertions(+)
>
> diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c
> index 4c611871d7e6..b80d44f9751d 100644
> --- a/drivers/mtd/mtdcore.c
> +++ b/drivers/mtd/mtdcore.c
> @@ -37,6 +37,7 @@
>   #include <linux/backing-dev.h>
>   #include <linux/gfp.h>
>   #include <linux/slab.h>
> +#include <linux/reboot.h>
>
>   #include <linux/mtd/mtd.h>
>   #include <linux/mtd/partitions.h>
> @@ -365,6 +366,17 @@ static struct device_type mtd_devtype = {
>   	.release	= mtd_release,
>   };
>
> +static int mtd_reboot_notifier(struct notifier_block *n, unsigned long state,
> +			       void *cmd)
> +{
> +       struct mtd_info *mtd;
> +
> +       mtd = container_of(n, struct mtd_info, reboot_notifier);
> +       mtd->_reboot(mtd);
> +
> +       return NOTIFY_DONE;
> +}
> +
>   /**
>    *	add_mtd_device - register an MTD device
>    *	@mtd: pointer to new MTD device info structure
> @@ -565,6 +577,11 @@ int mtd_device_parse_register(struct mtd_info *mtd, const char * const *types,
>   			err = -ENODEV;
>   	}
>
> +	if (mtd->_reboot) {
> +		mtd->reboot_notifier.notifier_call = mtd_reboot_notifier;
> +		register_reboot_notifier(&mtd->reboot_notifier);
> +	}
> +
>   	return err;
>   }
>   EXPORT_SYMBOL_GPL(mtd_device_parse_register);
> @@ -579,6 +596,9 @@ int mtd_device_unregister(struct mtd_info *master)
>   {
>   	int err;
>
> +	if (master->_reboot)
> +		unregister_reboot_notifier(&master->reboot_notifier);
> +
>   	err = del_mtd_partitions(master);
>   	if (err)
>   		return err;
> diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
> index 031ff3a9a0bd..c06f5373d870 100644
> --- a/include/linux/mtd/mtd.h
> +++ b/include/linux/mtd/mtd.h
> @@ -227,6 +227,7 @@ struct mtd_info {
>   	int (*_block_markbad) (struct mtd_info *mtd, loff_t ofs);
>   	int (*_suspend) (struct mtd_info *mtd);
>   	void (*_resume) (struct mtd_info *mtd);
> +	void (*_reboot) (struct mtd_info *mtd);
>   	/*
>   	 * If the driver is something smart, like UBI, it may need to maintain
>   	 * its own reference counting. The below functions are only for driver.
>

[PATCH] mmc: sdhci: add quirk for ACMD23 broken

[Scott Branden]

Add quick to handle broken auto-CMD23
Some controllers do not respond after the first auto-CMD23 is issued.

This allows CMD23 to still work (mandatory for the faster UHS-I mode)
rather than disabling CMD23 entirely via SDHCI_QUIRK2_HOST_NO_CMD23.

Signed-off by: Corneliu Doban <cdoban@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/mmc/host/sdhci.c  | 3 ++-
 include/linux/mmc/sdhci.h | 2 ++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index ada1a3e..b37331f 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -2985,7 +2985,8 @@ int sdhci_add_host(struct sdhci_host *host)
 	/* Auto-CMD23 stuff only works in ADMA or PIO. */
 	if ((host->version >= SDHCI_SPEC_300) &&
 	    ((host->flags & SDHCI_USE_ADMA) ||
-	     !(host->flags & SDHCI_USE_SDMA))) {
+	     !(host->flags & SDHCI_USE_SDMA)) &&
+	     !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
 		host->flags |= SDHCI_AUTO_CMD23;
 		DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
 	} else {
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index dba793e..d979cf9 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -100,6 +100,8 @@ struct sdhci_host {
 #define SDHCI_QUIRK2_BROKEN_DDR50			(1<<7)
 /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */
 #define SDHCI_QUIRK2_STOP_WITH_TC			(1<<8)
+/* Controller broken with using ACMD23 */
+#define SDHCI_QUIRK2_ACMD23_BROKEN			(1<<9)
 
 	int irq;		/* Device IRQ */
 	void __iomem *ioaddr;	/* Mapped address */
-- 
2.2.0

Re: [PATCH] mtd: add reboot notifier to mtdcore and register nand_shutdown with notifier

[Scott Branden]

Apologies:  patch fails checkpatch due to spaces instead of tabs during 
cut and paste.

But, please comment on this patch before I create a new version.

On 14-12-04 02:37 PM, Scott Branden wrote:
> add (optional) reboot notifier field to struct mtd_info, and use it to
> register a system reboot notifier on behalf of the lower layers.
>
> Add nand_shutdown to wait for current nand operations to finish and prevent
> further operations by changing the nand flash state to FL_SHUTDOWN.
> Register the nand_shutdown with the reboot notifier in nand_base.c
>
> This is addressing a problem observed during reboot tests using UBIFS
> root file system: NAND erase operations that are in progress during
> system reboot/shutdown are causing partial erased blocks. Although UBI should
> be able to detect and recover from this error, this change will avoid
> the creation of partial erased blocks on reboot in the middle of a NAND erase
> operation.
>
> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
> Signed-off-by: Corneliu Doban <cdoban@broadcom.com>
> Signed-off-by: Scott Branden <sbranden@broadcom.com>
> ---
>   drivers/mtd/mtdcore.c        | 20 ++++++++++++++++++++
>   drivers/mtd/nand/nand_base.c | 11 +++++++++++
>   include/linux/mtd/mtd.h      |  1 +
>   3 files changed, 32 insertions(+)
>
> diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c
> index 4c61187..b80d44f 100644
> --- a/drivers/mtd/mtdcore.c
> +++ b/drivers/mtd/mtdcore.c
> @@ -37,6 +37,7 @@
>   #include <linux/backing-dev.h>
>   #include <linux/gfp.h>
>   #include <linux/slab.h>
> +#include <linux/reboot.h>
>
>   #include <linux/mtd/mtd.h>
>   #include <linux/mtd/partitions.h>
> @@ -365,6 +366,17 @@ static struct device_type mtd_devtype = {
>   	.release	= mtd_release,
>   };
>
> +static int mtd_reboot_notifier(struct notifier_block *n, unsigned long state,
> +			       void *cmd)
> +{
> +       struct mtd_info *mtd;
> +
> +       mtd = container_of(n, struct mtd_info, reboot_notifier);
> +       mtd->_reboot(mtd);
> +
> +       return NOTIFY_DONE;
> +}
> +
>   /**
>    *	add_mtd_device - register an MTD device
>    *	@mtd: pointer to new MTD device info structure
> @@ -565,6 +577,11 @@ int mtd_device_parse_register(struct mtd_info *mtd, const char * const *types,
>   			err = -ENODEV;
>   	}
>
> +	if (mtd->_reboot) {
> +		mtd->reboot_notifier.notifier_call = mtd_reboot_notifier;
> +		register_reboot_notifier(&mtd->reboot_notifier);
> +	}
> +
>   	return err;
>   }
>   EXPORT_SYMBOL_GPL(mtd_device_parse_register);
> @@ -579,6 +596,9 @@ int mtd_device_unregister(struct mtd_info *master)
>   {
>   	int err;
>
> +	if (master->_reboot)
> +		unregister_reboot_notifier(&master->reboot_notifier);
> +
>   	err = del_mtd_partitions(master);
>   	if (err)
>   		return err;
> diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
> index 5b5c627..e18165b 100644
> --- a/drivers/mtd/nand/nand_base.c
> +++ b/drivers/mtd/nand/nand_base.c
> @@ -2944,6 +2944,16 @@ static void nand_resume(struct mtd_info *mtd)
>   			__func__);
>   }
>
> +/**
> + * nand_shutdown - [MTD Interface] Finish the current NAND operation and
> + *                 prevent further operations
> + * @mtd: MTD device structure
> + */
> +static void nand_shutdown(struct mtd_info *mtd)
> +{
> +	nand_get_device(mtd, FL_SHUTDOWN);
> +}
> +
>   /* Set default functions */
>   static void nand_set_defaults(struct nand_chip *chip, int busw)
>   {
> @@ -4146,6 +4156,7 @@ int nand_scan_tail(struct mtd_info *mtd)
>   	mtd->_unlock = NULL;
>   	mtd->_suspend = nand_suspend;
>   	mtd->_resume = nand_resume;
> +	mtd->_reboot = nand_shutdown;
>   	mtd->_block_isreserved = nand_block_isreserved;
>   	mtd->_block_isbad = nand_block_isbad;
>   	mtd->_block_markbad = nand_block_markbad;
> diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
> index 031ff3a..c06f537 100644
> --- a/include/linux/mtd/mtd.h
> +++ b/include/linux/mtd/mtd.h
> @@ -227,6 +227,7 @@ struct mtd_info {
>   	int (*_block_markbad) (struct mtd_info *mtd, loff_t ofs);
>   	int (*_suspend) (struct mtd_info *mtd);
>   	void (*_resume) (struct mtd_info *mtd);
> +	void (*_reboot) (struct mtd_info *mtd);
>   	/*
>   	 * If the driver is something smart, like UBI, it may need to maintain
>   	 * its own reference counting. The below functions are only for driver.
>

[PATCH v2] mmc: sdhci: add quirk for ACMD23 broken

[Scott Branden]

Add quirk to handle broken auto-CMD23.
Some controllers do not respond after the first auto-CMD23 is issued.

This allows CMD23 to still work (mandatory for the faster UHS-I mode)
rather than disabling CMD23 entirely via SDHCI_QUIRK2_HOST_NO_CMD23.

Signed-off by: Corneliu Doban <cdoban@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/mmc/host/sdhci.c  | 3 ++-
 include/linux/mmc/sdhci.h | 2 ++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index ada1a3e..b37331f 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -2985,7 +2985,8 @@ int sdhci_add_host(struct sdhci_host *host)
 	/* Auto-CMD23 stuff only works in ADMA or PIO. */
 	if ((host->version >= SDHCI_SPEC_300) &&
 	    ((host->flags & SDHCI_USE_ADMA) ||
-	     !(host->flags & SDHCI_USE_SDMA))) {
+	     !(host->flags & SDHCI_USE_SDMA)) &&
+	     !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
 		host->flags |= SDHCI_AUTO_CMD23;
 		DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
 	} else {
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index dba793e..d979cf9 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -100,6 +100,8 @@ struct sdhci_host {
 #define SDHCI_QUIRK2_BROKEN_DDR50			(1<<7)
 /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */
 #define SDHCI_QUIRK2_STOP_WITH_TC			(1<<8)
+/* Controller broken with using ACMD23 */
+#define SDHCI_QUIRK2_ACMD23_BROKEN			(1<<9)
 
 	int irq;		/* Device IRQ */
 	void __iomem *ioaddr;	/* Mapped address */
-- 
2.2.0

Re: [PATCH] mtd: add reboot notifier to mtdcore and register nand_shutdown with notifier

[Brian Norris]

On Thu, Dec 04, 2014 at 04:13:01PM -0800, Scott Branden wrote:
> Apologies:  patch fails checkpatch due to spaces instead of tabs
> during cut and paste.
> 
> But, please comment on this patch before I create a new version.

I'd prefer the separation to be as I sent in the first place; one patch
to add a generic hook for all MTD's, and one to implement the hook in
NAND.

I can just resend my patch (fixed up to compile correctly; I had an
error previously), then you can just add your Tested-by.

Brian

Re: [PATCH v2 1/4] pwm: kona: Remove setting default smooth type and polarity for all channels

[Tim Kryger]

On Thu, Dec 4, 2014 at 12:22 PM, Jonathan Richardson
<jonathar@broadcom.com> wrote:
> Hi Tim,
>
> I'm going to take over this submission because I made the changes to the
> driver. Arun was filling in for me while I was on leave. Now I'm back
> and I think I can help clarify why these changes were made. A summary
> for all the changes should help.
>
> There were two problems. First was a problem caused by setting the
> polarity in probe. It caused the speaker to click when the polarity was
> set so we took that out as it didn't seem to serve any useful purpose
> that I could see. The polarity changes should be made in the polarity
> callback.

Please provide more details about your configuration.

Are you using the pwm-beeper driver with a piezo?

After a reset, all PWM output will be low until the PWM clock is
enabled at which point it will be constant high.  Are you confident
that this transition is not responsible for the click you are hearing?

> The second and bigger problem was the smooth type sequence. If it isn't
> done according to the spec then one in ten or twenty times you won't
> even get a signal when it's enabled. Following the correct sequence with
> the 400 ns delays solves this problem.

Would the following minor change be sufficient to fix the issue?

diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
index 02bc048..c537efd 100644
--- a/drivers/pwm/pwm-bcm-kona.c
+++ b/drivers/pwm/pwm-bcm-kona.c
@@ -85,6 +85,9 @@ static void kona_pwmc_apply_settings(struct kona_pwmc *kp, uns
        value &= ~(1 << PWM_CONTROL_TRIGGER_SHIFT(chan));
        writel(value, kp->base + PWM_CONTROL_OFFSET);

+       ndelay(400);
+
        /* Set trigger bit and clear smooth bit to apply new settings */
        value &= ~(1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
        value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);

>
> Additionally, by not following the sequence you won't get a smooth
> transition. You'll get a change in the settings (duty cycle, period) but
> may get a non smooth transition. So it's important to follow the spec
> here. We don't want non-smooth transitions.

Please provide your rationale for requiring smooth transitions.

Thanks,
Tim Kryger

Re: [PATCH v2 1/4] pwm: kona: Remove setting default smooth type and polarity for all channels

[Jonathan Richardson]

On 14-12-06 03:13 PM, Tim Kryger wrote:
> On Thu, Dec 4, 2014 at 12:22 PM, Jonathan Richardson
> <jonathar@broadcom.com> wrote:
>> Hi Tim,
>>
>> I'm going to take over this submission because I made the changes to the
>> driver. Arun was filling in for me while I was on leave. Now I'm back
>> and I think I can help clarify why these changes were made. A summary
>> for all the changes should help.
>>
>> There were two problems. First was a problem caused by setting the
>> polarity in probe. It caused the speaker to click when the polarity was
>> set so we took that out as it didn't seem to serve any useful purpose
>> that I could see. The polarity changes should be made in the polarity
>> callback.
> 
> Please provide more details about your configuration.
> 
> Are you using the pwm-beeper driver with a piezo?

Probably, but I don't know. We don't care about it and aren't using it
which underscores why we don't want to initialize pwm channels we aren't
using.

> 
> After a reset, all PWM output will be low until the PWM clock is
> enabled at which point it will be constant high.  Are you confident
> that this transition is not responsible for the click you are hearing?
> 
>> The second and bigger problem was the smooth type sequence. If it isn't
>> done according to the spec then one in ten or twenty times you won't
>> even get a signal when it's enabled. Following the correct sequence with
>> the 400 ns delays solves this problem.
> 
> Would the following minor change be sufficient to fix the issue?

Not quite but hopefully I can send a patch soon for your review.

> 
> diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
> index 02bc048..c537efd 100644
> --- a/drivers/pwm/pwm-bcm-kona.c
> +++ b/drivers/pwm/pwm-bcm-kona.c
> @@ -85,6 +85,9 @@ static void kona_pwmc_apply_settings(struct kona_pwmc *kp, uns
>         value &= ~(1 << PWM_CONTROL_TRIGGER_SHIFT(chan));
>         writel(value, kp->base + PWM_CONTROL_OFFSET);
> 
> +       ndelay(400);
> +
>         /* Set trigger bit and clear smooth bit to apply new settings */
>         value &= ~(1 << PWM_CONTROL_SMOOTH_SHIFT(chan));
>         value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan);
> 
>>
>> Additionally, by not following the sequence you won't get a smooth
>> transition. You'll get a change in the settings (duty cycle, period) but
>> may get a non smooth transition. So it's important to follow the spec
>> here. We don't want non-smooth transitions.
> 
> Please provide your rationale for requiring smooth transitions.

The rationale is we don't want to give customers a bad experience when
we can provide them with a better one. The driver attempts to use smooth
transitions already but due to the quirks in the procedure which were
sent out previously it doesn't quite work as intended. When changing the
waveform we want to always have smooth transitions. There are unused pwm
channels that vendors can hook up whatever they want.

Thanks,
Jon

> 
> Thanks,
> Tim Kryger
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
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> 

Re: [PATCH v2] mmc: sdhci: add quirk for ACMD23 broken

[Scott Branden]

Hi Chris,

I have not received any feedback on this patch for the SDHCI controller. 
  Anything I can do to help get this accepted into the codebase?

Thanks,
  Scott

On 14-12-04 04:16 PM, Scott Branden wrote:
> Add quirk to handle broken auto-CMD23.
> Some controllers do not respond after the first auto-CMD23 is issued.
>
> This allows CMD23 to still work (mandatory for the faster UHS-I mode)
> rather than disabling CMD23 entirely via SDHCI_QUIRK2_HOST_NO_CMD23.
>
> Signed-off by: Corneliu Doban <cdoban@broadcom.com>
> Signed-off-by: Scott Branden <sbranden@broadcom.com>
> ---
>   drivers/mmc/host/sdhci.c  | 3 ++-
>   include/linux/mmc/sdhci.h | 2 ++
>   2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index ada1a3e..b37331f 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -2985,7 +2985,8 @@ int sdhci_add_host(struct sdhci_host *host)
>   	/* Auto-CMD23 stuff only works in ADMA or PIO. */
>   	if ((host->version >= SDHCI_SPEC_300) &&
>   	    ((host->flags & SDHCI_USE_ADMA) ||
> -	     !(host->flags & SDHCI_USE_SDMA))) {
> +	     !(host->flags & SDHCI_USE_SDMA)) &&
> +	     !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
>   		host->flags |= SDHCI_AUTO_CMD23;
>   		DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
>   	} else {
> diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
> index dba793e..d979cf9 100644
> --- a/include/linux/mmc/sdhci.h
> +++ b/include/linux/mmc/sdhci.h
> @@ -100,6 +100,8 @@ struct sdhci_host {
>   #define SDHCI_QUIRK2_BROKEN_DDR50			(1<<7)
>   /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */
>   #define SDHCI_QUIRK2_STOP_WITH_TC			(1<<8)
> +/* Controller broken with using ACMD23 */
> +#define SDHCI_QUIRK2_ACMD23_BROKEN			(1<<9)
>
>   	int irq;		/* Device IRQ */
>   	void __iomem *ioaddr;	/* Mapped address */
>

Re: [PATCH v2] mmc: sdhci: add quirk for ACMD23 broken

[Chris Ball]

Hi Scott, sorry for the delay,

On Fri, Dec 05 2014, Scott Branden wrote:
> Add quirk to handle broken auto-CMD23.
> Some controllers do not respond after the first auto-CMD23 is issued.
>
> This allows CMD23 to still work (mandatory for the faster UHS-I mode)
> rather than disabling CMD23 entirely via SDHCI_QUIRK2_HOST_NO_CMD23.
>
> Signed-off by: Corneliu Doban <cdoban@broadcom.com>
> Signed-off-by: Scott Branden <sbranden@broadcom.com>
> ---
>  drivers/mmc/host/sdhci.c  | 3 ++-
>  include/linux/mmc/sdhci.h | 2 ++
>  2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index ada1a3e..b37331f 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -2985,7 +2985,8 @@ int sdhci_add_host(struct sdhci_host *host)
>  	/* Auto-CMD23 stuff only works in ADMA or PIO. */
>  	if ((host->version >= SDHCI_SPEC_300) &&
>  	    ((host->flags & SDHCI_USE_ADMA) ||
> -	     !(host->flags & SDHCI_USE_SDMA))) {
> +	     !(host->flags & SDHCI_USE_SDMA)) &&
> +	     !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
>  		host->flags |= SDHCI_AUTO_CMD23;
>  		DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
>  	} else {
> diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
> index dba793e..d979cf9 100644
> --- a/include/linux/mmc/sdhci.h
> +++ b/include/linux/mmc/sdhci.h
> @@ -100,6 +100,8 @@ struct sdhci_host {
>  #define SDHCI_QUIRK2_BROKEN_DDR50			(1<<7)
>  /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */
>  #define SDHCI_QUIRK2_STOP_WITH_TC			(1<<8)
> +/* Controller broken with using ACMD23 */
> +#define SDHCI_QUIRK2_ACMD23_BROKEN			(1<<9)
>  
>  	int irq;		/* Device IRQ */
>  	void __iomem *ioaddr;	/* Mapped address */

This patch doesn't apply the quirk to any chipsets, so the patch
doesn't actually change any behavior when run on a mainline kernel.
Do you have a patch to apply the quirk to your chipset too?  We don't
typically accept patches that "don't do anything" for mainline users,
so that's why we'd like to see the chipset patch too.

Thanks,

- Chris.
-- 
Chris Ball   <http://printf.net/>

Re: [PATCH v2] mmc: sdhci: add quirk for ACMD23 broken

[Scott Branden]

Hi Chris,

We'll finish off cleaning up our driver that uses this patch for review 
then.

Thanks,
  Scott

On 14-12-17 11:48 AM, Chris Ball wrote:
> Hi Scott, sorry for the delay,
>
> On Fri, Dec 05 2014, Scott Branden wrote:
>> Add quirk to handle broken auto-CMD23.
>> Some controllers do not respond after the first auto-CMD23 is issued.
>>
>> This allows CMD23 to still work (mandatory for the faster UHS-I mode)
>> rather than disabling CMD23 entirely via SDHCI_QUIRK2_HOST_NO_CMD23.
>>
>> Signed-off by: Corneliu Doban <cdoban@broadcom.com>
>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>> ---
>>   drivers/mmc/host/sdhci.c  | 3 ++-
>>   include/linux/mmc/sdhci.h | 2 ++
>>   2 files changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
>> index ada1a3e..b37331f 100644
>> --- a/drivers/mmc/host/sdhci.c
>> +++ b/drivers/mmc/host/sdhci.c
>> @@ -2985,7 +2985,8 @@ int sdhci_add_host(struct sdhci_host *host)
>>   	/* Auto-CMD23 stuff only works in ADMA or PIO. */
>>   	if ((host->version >= SDHCI_SPEC_300) &&
>>   	    ((host->flags & SDHCI_USE_ADMA) ||
>> -	     !(host->flags & SDHCI_USE_SDMA))) {
>> +	     !(host->flags & SDHCI_USE_SDMA)) &&
>> +	     !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
>>   		host->flags |= SDHCI_AUTO_CMD23;
>>   		DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
>>   	} else {
>> diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
>> index dba793e..d979cf9 100644
>> --- a/include/linux/mmc/sdhci.h
>> +++ b/include/linux/mmc/sdhci.h
>> @@ -100,6 +100,8 @@ struct sdhci_host {
>>   #define SDHCI_QUIRK2_BROKEN_DDR50			(1<<7)
>>   /* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */
>>   #define SDHCI_QUIRK2_STOP_WITH_TC			(1<<8)
>> +/* Controller broken with using ACMD23 */
>> +#define SDHCI_QUIRK2_ACMD23_BROKEN			(1<<9)
>>
>>   	int irq;		/* Device IRQ */
>>   	void __iomem *ioaddr;	/* Mapped address */
>
> This patch doesn't apply the quirk to any chipsets, so the patch
> doesn't actually change any behavior when run on a mainline kernel.
> Do you have a patch to apply the quirk to your chipset too?  We don't
> typically accept patches that "don't do anything" for mainline users,
> so that's why we'd like to see the chipset patch too.
>
> Thanks,
>
> - Chris.
>

[PATCH 0/4] Add support for IPROC SDHCI controller

[Scott Branden]

This series of patchsets contains the IPROC SDHCI driver used
in a series of Broadcom SoCs
Quirks are also added to support this controller.

Corneliu Doban (1):
  mmc: sdhci: do not set AUTO_CMD12 for multi-block CMD53

Scott Branden (3):
  mmc: sdhci: add quirk for ACMD23 broken
  mmc: sdhci-iproc: add IPROC SDHCI driver
  mmc: sdhci-iproc: add device tree bindings

 .../devicetree/bindings/mmc/brcm,sdhci-iproc.txt   |  23 ++
 drivers/mmc/host/Kconfig                           |  14 ++
 drivers/mmc/host/Makefile                          |   1 +
 drivers/mmc/host/sdhci-iproc.c                     | 241 +++++++++++++++++++++
 drivers/mmc/host/sdhci.c                           |   7 +-
 include/linux/mmc/sdhci.h                          |   2 +
 6 files changed, 286 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt
 create mode 100644 drivers/mmc/host/sdhci-iproc.c

-- 
2.2.2

[PATCH 1/4] mmc: sdhci: add quirk for ACMD23 broken

[Scott Branden]

Add quirk to handle broken auto-CMD23.
Some controllers do not respond after the first auto-CMD23 is issued.

This allows CMD23 to still work (mandatory for the faster UHS-I mode)
rather than disabling CMD23 entirely via SDHCI_QUIRK2_HOST_NO_CMD23.

Signed-off by: Corneliu Doban <cdoban@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>

Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/mmc/host/sdhci.c  | 3 ++-
 include/linux/mmc/sdhci.h | 2 ++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index f1a488e..fcf78ab 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -3085,7 +3085,8 @@ int sdhci_add_host(struct sdhci_host *host)
 	/* Auto-CMD23 stuff only works in ADMA or PIO. */
 	if ((host->version >= SDHCI_SPEC_300) &&
 	    ((host->flags & SDHCI_USE_ADMA) ||
-	     !(host->flags & SDHCI_USE_SDMA))) {
+	     !(host->flags & SDHCI_USE_SDMA)) &&
+	     !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
 		host->flags |= SDHCI_AUTO_CMD23;
 		DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
 	} else {
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index f767a0d..a29e9bb 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -106,6 +106,8 @@ struct sdhci_host {
 #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD	(1<<10)
 /* Capability register bit-63 indicates HS400 support */
 #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400		(1<<11)
+/* Controller broken with using ACMD23 */
+#define SDHCI_QUIRK2_ACMD23_BROKEN			(1<<12)
 
 	int irq;		/* Device IRQ */
 	void __iomem *ioaddr;	/* Mapped address */
-- 
2.2.2

[PATCH 2/4] mmc: sdhci: do not set AUTO_CMD12 for multi-block CMD53

[Scott Branden]

From: Corneliu Doban <cdoban@broadcom.com>

For CMD53 in block mode, the host does not need to stop the transfer,
as it stops when the block count (present in CMD53) is reached.

Signed-off-by: Corneliu Doban <cdoban@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/mmc/host/sdhci.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index fcf78ab..f35d413 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -28,6 +28,7 @@
 #include <linux/mmc/mmc.h>
 #include <linux/mmc/host.h>
 #include <linux/mmc/card.h>
+#include <linux/mmc/sdio.h>
 #include <linux/mmc/slot-gpio.h>
 
 #include "sdhci.h"
@@ -934,7 +935,8 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host,
 		 * If we are sending CMD23, CMD12 never gets sent
 		 * on successful completion (so no Auto-CMD12).
 		 */
-		if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
+		if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
+		    (cmd->opcode != SD_IO_RW_EXTENDED))
 			mode |= SDHCI_TRNS_AUTO_CMD12;
 		else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 			mode |= SDHCI_TRNS_AUTO_CMD23;
-- 
2.2.2

[PATCH 3/4] mmc: sdhci-iproc: add IPROC SDHCI driver

[Scott Branden]

Add IPROC SDHCI driver for IPROC family of Broadcom devices.

Acked-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Corneliu Doban <cdoban@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/mmc/host/Kconfig       |  14 +++
 drivers/mmc/host/Makefile      |   1 +
 drivers/mmc/host/sdhci-iproc.c | 241 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 256 insertions(+)
 create mode 100644 drivers/mmc/host/sdhci-iproc.c

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 2d6fbdd..d6a2ff1 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -292,6 +292,20 @@ config MMC_SDHCI_BCM2835
 
 	  If unsure, say N.
 
+config MMC_SDHCI_IPROC
+	tristate "SDHCI platform support for the iProc SD/MMC Controller"
+	depends on ARCH_BCM_IPROC || COMPILE_TEST
+	depends on MMC_SDHCI_PLTFM
+	default ARCH_BCM_IPROC
+	select MMC_SDHCI_IO_ACCESSORS
+	help
+	  This selects the iProc SD/MMC controller.
+
+	  If you have an IPROC platform with SD or MMC devices,
+	  say Y or M here.
+
+	  If unsure, say N.
+
 config MMC_MOXART
 	tristate "MOXART SD/MMC Host Controller support"
 	depends on ARCH_MOXART && MMC
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index f7b0a77..32f24bd 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -70,6 +70,7 @@ obj-$(CONFIG_MMC_SDHCI_OF_ESDHC)	+= sdhci-of-esdhc.o
 obj-$(CONFIG_MMC_SDHCI_OF_HLWD)		+= sdhci-of-hlwd.o
 obj-$(CONFIG_MMC_SDHCI_BCM_KONA)	+= sdhci-bcm-kona.o
 obj-$(CONFIG_MMC_SDHCI_BCM2835)		+= sdhci-bcm2835.o
+obj-$(CONFIG_MMC_SDHCI_IPROC)		+= sdhci-iproc.o
 obj-$(CONFIG_MMC_SDHCI_MSM)		+= sdhci-msm.o
 obj-$(CONFIG_MMC_SDHCI_ST)		+= sdhci-st.o
 
diff --git a/drivers/mmc/host/sdhci-iproc.c b/drivers/mmc/host/sdhci-iproc.c
new file mode 100644
index 0000000..4139d34
--- /dev/null
+++ b/drivers/mmc/host/sdhci-iproc.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * iProc SDHCI platform driver
+ */
+
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/mmc/host.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include "sdhci-pltfm.h"
+
+struct sdhci_iproc_data {
+	const struct sdhci_pltfm_data *pdata;
+	u32 caps;
+	u32 caps1;
+};
+
+struct sdhci_iproc_host {
+	const struct sdhci_iproc_data *data;
+	u32 shadow_cmd;
+	u32 shadow_blk;
+};
+
+#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
+
+static inline u32 sdhci_iproc_readl(struct sdhci_host *host, int reg)
+{
+	u32 val = readl(host->ioaddr + reg);
+
+	pr_debug("%s: readl [0x%02x] 0x%08x\n",
+		 mmc_hostname(host->mmc), reg, val);
+	return val;
+}
+
+static u16 sdhci_iproc_readw(struct sdhci_host *host, int reg)
+{
+	u32 val = sdhci_iproc_readl(host, (reg & ~3));
+	u16 word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
+	return word;
+}
+
+static u8 sdhci_iproc_readb(struct sdhci_host *host, int reg)
+{
+	u32 val = sdhci_iproc_readl(host, (reg & ~3));
+	u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
+	return byte;
+}
+
+static inline void sdhci_iproc_writel(struct sdhci_host *host, u32 val, int reg)
+{
+	pr_debug("%s: writel [0x%02x] 0x%08x\n",
+		 mmc_hostname(host->mmc), reg, val);
+
+	writel(val, host->ioaddr + reg);
+
+	if (host->clock <= 400000) {
+		/* Round up to micro-second four SD clock delay */
+		if (host->clock)
+			udelay((4 * 1000000 + host->clock - 1) / host->clock);
+		else
+			udelay(10);
+	}
+}
+
+/*
+ * The Arasan has a bugette whereby it may lose the content of successive
+ * writes to the same register that are within two SD-card clock cycles of
+ * each other (a clock domain crossing problem). The data
+ * register does not have this problem, which is just as well - otherwise we'd
+ * have to nobble the DMA engine too.
+ *
+ * This wouldn't be a problem with the code except that we can only write the
+ * controller with 32-bit writes.  So two different 16-bit registers are
+ * written back to back creates the problem.
+ *
+ * In reality, this only happens when SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT
+ * are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND.
+ * The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so
+ * the work around can be further optimized. We can keep shadow values of
+ * BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued.
+ * Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed
+ * by the TRANSFER+COMMAND in another 32-bit write.
+ */
+static void sdhci_iproc_writew(struct sdhci_host *host, u16 val, int reg)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_iproc_host *iproc_host = pltfm_host->priv;
+	u32 word_shift = REG_OFFSET_IN_BITS(reg);
+	u32 mask = 0xffff << word_shift;
+	u32 oldval, newval;
+
+	if (reg == SDHCI_COMMAND) {
+		/* Write the block now as we are issuing a command */
+		if (iproc_host->shadow_blk != 0) {
+			sdhci_iproc_writel(host, iproc_host->shadow_blk,
+				SDHCI_BLOCK_SIZE);
+			iproc_host->shadow_blk = 0;
+		}
+		oldval = iproc_host->shadow_cmd;
+	} else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
+		/* Block size and count are stored in shadow reg */
+		oldval = iproc_host->shadow_blk;
+	} else {
+		/* Read reg, all other registers are not shadowed */
+		oldval = sdhci_iproc_readl(host, (reg & ~3));
+	}
+	newval = (oldval & ~mask) | (val << word_shift);
+
+	if (reg == SDHCI_TRANSFER_MODE) {
+		/* Save the transfer mode until the command is issued */
+		iproc_host->shadow_cmd = newval;
+	} else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
+		/* Save the block info until the command is issued */
+		iproc_host->shadow_blk = newval;
+	} else {
+		/* Command or other regular 32-bit write */
+		sdhci_iproc_writel(host, newval, reg & ~3);
+	}
+}
+
+static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg)
+{
+	u32 oldval = sdhci_iproc_readl(host, (reg & ~3));
+	u32 byte_shift = REG_OFFSET_IN_BITS(reg);
+	u32 mask = 0xff << byte_shift;
+	u32 newval = (oldval & ~mask) | (val << byte_shift);
+
+	sdhci_iproc_writel(host, newval, reg & ~3);
+}
+
+static const struct sdhci_ops sdhci_iproc_ops = {
+	.read_l = sdhci_iproc_readl,
+	.read_w = sdhci_iproc_readw,
+	.read_b = sdhci_iproc_readb,
+	.write_l = sdhci_iproc_writel,
+	.write_w = sdhci_iproc_writew,
+	.write_b = sdhci_iproc_writeb,
+	.set_clock = sdhci_set_clock,
+	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
+	.set_bus_width = sdhci_set_bus_width,
+	.reset = sdhci_reset,
+	.set_uhs_signaling = sdhci_set_uhs_signaling,
+};
+
+static const struct sdhci_pltfm_data sdhci_iproc_pltfm_data = {
+	.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
+	.quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN,
+	.ops = &sdhci_iproc_ops,
+};
+
+static const struct sdhci_iproc_data iproc_data = {
+	.pdata = &sdhci_iproc_pltfm_data,
+	.caps = 0x05E90000,
+	.caps1 = 0x00000064,
+};
+
+static const struct of_device_id sdhci_iproc_of_match[] = {
+	{ .compatible = "brcm,sdhci-iproc-cygnus", .data = &iproc_data },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, sdhci_iproc_of_match);
+
+static int sdhci_iproc_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *match;
+	const struct sdhci_iproc_data *iproc_data;
+	struct sdhci_host *host;
+	struct sdhci_iproc_host *iproc_host;
+	struct sdhci_pltfm_host *pltfm_host;
+	int ret;
+
+	match = of_match_device(sdhci_iproc_of_match, &pdev->dev);
+	if (!match)
+		return -EINVAL;
+	iproc_data = match->data;
+
+	host = sdhci_pltfm_init(pdev, iproc_data->pdata, sizeof(*iproc_host));
+	if (IS_ERR(host))
+		return PTR_ERR(host);
+
+	pltfm_host = sdhci_priv(host);
+	iproc_host = sdhci_pltfm_priv(pltfm_host);
+
+	iproc_host->data = iproc_data;
+
+	mmc_of_parse(host->mmc);
+	sdhci_get_of_property(pdev);
+
+	/* Enable EMMC 1/8V DDR capable */
+	host->mmc->caps |= MMC_CAP_1_8V_DDR;
+
+	pltfm_host->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(pltfm_host->clk)) {
+		ret = PTR_ERR(pltfm_host->clk);
+		goto err;
+	}
+
+	if (iproc_host->data->pdata->quirks & SDHCI_QUIRK_MISSING_CAPS) {
+		host->caps = iproc_host->data->caps;
+		host->caps1 = iproc_host->data->caps1;
+	}
+
+	return sdhci_add_host(host);
+
+err:
+	sdhci_pltfm_free(pdev);
+	return ret;
+}
+
+static int sdhci_iproc_remove(struct platform_device *pdev)
+{
+	return sdhci_pltfm_unregister(pdev);
+}
+
+static struct platform_driver sdhci_iproc_driver = {
+	.driver = {
+		.name = "sdhci-iproc",
+		.of_match_table = sdhci_iproc_of_match,
+		.pm = SDHCI_PLTFM_PMOPS,
+	},
+	.probe = sdhci_iproc_probe,
+	.remove = sdhci_iproc_remove,
+};
+module_platform_driver(sdhci_iproc_driver);
+
+MODULE_AUTHOR("Broadcom");
+MODULE_DESCRIPTION("IPROC SDHCI driver");
+MODULE_LICENSE("GPL v2");
-- 
2.2.2

[PATCH 4/4] mmc: sdhci-iproc: add device tree bindings

[Scott Branden]

Add device tree binding documentation for IPROC SDHCI driver.

Acked-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Corneliu Doban <cdoban@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 .../devicetree/bindings/mmc/brcm,sdhci-iproc.txt   | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt

diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt b/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt
new file mode 100644
index 0000000..72cc9cc
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt
@@ -0,0 +1,23 @@
+Broadcom IPROC SDHCI controller
+
+This file documents differences between the core properties described
+by mmc.txt and the properties that represent the IPROC SDHCI controller.
+
+Required properties:
+- compatible : Should be "brcm,sdhci-iproc-cygnus".
+- clocks : The clock feeding the SDHCI controller.
+
+Optional properties:
+  - sdhci,auto-cmd12: specifies that controller should use auto CMD12.
+
+Example:
+
+sdhci0: sdhci@0x18041000 {
+	compatible = "brcm,sdhci-iproc-cygnus";
+	reg = <0x18041000 0x100>;
+	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+	clocks = <&lcpll0_clks BCM_CYGNUS_LCPLL0_SDIO_CLK>;
+	bus-width = <4>;
+	sdhci,auto-cmd12;
+	no-1-8-v;
+};
-- 
2.2.2

[PATCH 0/2] Add support for Broadcom RNG200

[Scott Branden]

This series of patchsets contains the Broadcom Random Number Generator
driver and device tree binding documentation.

Scott Branden (2):
  hwrng: iproc-rng200 - Add Broadcom IPROC RNG driver
  hwrng: iproc-rng200 - Add device tree bindings

 .../bindings/hwrng/brcm,iproc-rng200.txt           |  12 ++
 drivers/char/hw_random/Kconfig                     |  13 ++
 drivers/char/hw_random/Makefile                    |   1 +
 drivers/char/hw_random/iproc-rng200.c              | 239 +++++++++++++++++++++
 4 files changed, 265 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwrng/brcm,iproc-rng200.txt
 create mode 100644 drivers/char/hw_random/iproc-rng200.c

-- 
2.2.2

[PATCH 1/2] hwrng: iproc-rng200 - Add Broadcom IPROC RNG driver

[Scott Branden]

This adds a driver for random number generator present on Broadcom
IPROC devices.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/char/hw_random/Kconfig        |  13 ++
 drivers/char/hw_random/Makefile       |   1 +
 drivers/char/hw_random/iproc-rng200.c | 239 ++++++++++++++++++++++++++++++++++
 3 files changed, 253 insertions(+)
 create mode 100644 drivers/char/hw_random/iproc-rng200.c

diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index de57b38..f48cf11 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -101,6 +101,19 @@ config HW_RANDOM_BCM2835
 
 	  If unsure, say Y.
 
+config HW_RANDOM_IPROC_RNG200
+	tristate "Broadcom iProc RNG200 support"
+	depends on ARCH_BCM_IPROC
+	default HW_RANDOM
+	---help---
+	  This driver provides kernel-side support for the RNG200
+	  hardware found on the Broadcom iProc SoCs.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called iproc-rng200
+
+	  If unsure, say Y.
+
 config HW_RANDOM_GEODE
 	tristate "AMD Geode HW Random Number Generator support"
 	depends on X86_32 && PCI
diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
index 0b4cd57..055bb01 100644
--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
@@ -28,5 +28,6 @@ obj-$(CONFIG_HW_RANDOM_POWERNV) += powernv-rng.o
 obj-$(CONFIG_HW_RANDOM_EXYNOS)	+= exynos-rng.o
 obj-$(CONFIG_HW_RANDOM_TPM) += tpm-rng.o
 obj-$(CONFIG_HW_RANDOM_BCM2835) += bcm2835-rng.o
+obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) += iproc-rng200.o
 obj-$(CONFIG_HW_RANDOM_MSM) += msm-rng.o
 obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o
diff --git a/drivers/char/hw_random/iproc-rng200.c b/drivers/char/hw_random/iproc-rng200.c
new file mode 100644
index 0000000..0fef15d
--- /dev/null
+++ b/drivers/char/hw_random/iproc-rng200.c
@@ -0,0 +1,239 @@
+/*
+* Copyright (C) 2014 Broadcom Corporation
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation version 2.
+*
+* This program is distributed "as is" WITHOUT ANY WARRANTY of any
+* kind, whether express or implied; without even the implied warranty
+* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*/
+/*
+ * DESCRIPTION: The Broadcom iProc RNG200 Driver
+ */
+
+#include <linux/hw_random.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+
+
+/* Registers */
+#define RNG_CTRL_OFFSET					0x00
+#define RNG_CTRL_RNG_RBGEN_MASK				0x00001FFF
+#define RNG_CTRL_RNG_RBGEN_ENABLE			0x00000001
+#define RNG_CTRL_RNG_RBGEN_DISABLE			0x00000000
+
+#define RNG_SOFT_RESET_OFFSET				0x04
+#define RNG_SOFT_RESET_RNG_SOFT_RESET_MASK		0x00000001
+#define RNG_SOFT_RESET_RNG_SOFT_RESET_ACTIVE		0x00000001
+#define RNG_SOFT_RESET_RNG_SOFT_RESET_CLEAR		0x00000000
+
+#define RBG_SOFT_RESET_OFFSET				0x08
+#define RBG_SOFT_RESET_RNG_SOFT_RESET_MASK		0x00000001
+#define RBG_SOFT_RESET_RNG_SOFT_RESET_ACTIVE		0x00000001
+#define RBG_SOFT_RESET_RNG_SOFT_RESET_CLEAR		0x00000000
+
+#define RNG_INT_STATUS_OFFSET				0x18
+#define RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK	0x80000000
+#define RNG_INT_STATUS_STARTUP_TRANSITIONS_MET_IRQ_MASK	0x00020000
+#define RNG_INT_STATUS_NIST_FAIL_IRQ_MASK		0x00000020
+#define RNG_INT_STATUS_TOTAL_BITS_COUNT_IRQ_MASK	0x00000001
+
+#define RNG_FIFO_DATA_OFFSET				0x20
+
+#define RNG_FIFO_COUNT_OFFSET				0x24
+#define RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK		0x000000FF
+
+static void iproc_rng200_restart(void __iomem *rng_base)
+{
+	uint32_t val;
+
+	/* Disable RBG */
+	val = ioread32(rng_base + RNG_CTRL_OFFSET);
+	val &= ~RNG_CTRL_RNG_RBGEN_MASK;
+	val |= RNG_CTRL_RNG_RBGEN_DISABLE;
+	iowrite32(val, rng_base + RNG_CTRL_OFFSET);
+
+	/* Clear all interrupt status */
+	iowrite32(0xFFFFFFFFUL, rng_base + RNG_INT_STATUS_OFFSET);
+
+	/* Reset RNG and RBG */
+	val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
+	val &= ~RBG_SOFT_RESET_RNG_SOFT_RESET_MASK;
+	val |= RBG_SOFT_RESET_RNG_SOFT_RESET_ACTIVE;
+	iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
+
+	val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
+	val &= ~RNG_SOFT_RESET_RNG_SOFT_RESET_MASK;
+	val |= RNG_SOFT_RESET_RNG_SOFT_RESET_ACTIVE;
+	iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
+
+	val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
+	val &= ~RNG_SOFT_RESET_RNG_SOFT_RESET_MASK;
+	val |= RNG_SOFT_RESET_RNG_SOFT_RESET_CLEAR;
+	iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
+
+	val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
+	val &= ~RBG_SOFT_RESET_RNG_SOFT_RESET_MASK;
+	val |= RBG_SOFT_RESET_RNG_SOFT_RESET_CLEAR;
+	iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
+
+	/* Enable RBG */
+	val = ioread32(rng_base + RNG_CTRL_OFFSET);
+	val &= ~RNG_CTRL_RNG_RBGEN_MASK;
+	val |= RNG_CTRL_RNG_RBGEN_ENABLE;
+	iowrite32(val, rng_base + RNG_CTRL_OFFSET);
+}
+
+static int iproc_rng200_read(struct hwrng *rng, void *buf, size_t max,
+			       bool wait)
+{
+	uint32_t status = 0;
+	uint32_t num_remaining = max;
+
+	#define MAX_RESETS_PER_READ	1
+	uint32_t num_resets = 0;
+
+	#define MAX_IDLE_TIME	(1 * HZ)
+	unsigned long idle_endtime = jiffies + MAX_IDLE_TIME;
+
+	/* Retrieve HW RNG registers base address. */
+	void __iomem *rng_base = (void __iomem *)rng->priv;
+
+	while ((num_remaining > 0) && time_before(jiffies, idle_endtime)) {
+
+		/* Is RNG sane? If not, reset it. */
+		status = ioread32(rng_base + RNG_INT_STATUS_OFFSET);
+		if ((status & (RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK |
+			RNG_INT_STATUS_NIST_FAIL_IRQ_MASK)) != 0) {
+
+			if (num_resets >= MAX_RESETS_PER_READ)
+				return max - num_remaining;
+
+			iproc_rng200_restart(rng_base);
+			num_resets++;
+		}
+
+		/* Are there any random numbers available? */
+		if ((ioread32(rng_base + RNG_FIFO_COUNT_OFFSET) &
+				RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK) > 0) {
+
+			if (num_remaining >= sizeof(uint32_t)) {
+				/* Buffer has room to store entire word */
+				*(uint32_t *)buf = ioread32(rng_base +
+							RNG_FIFO_DATA_OFFSET);
+				buf += sizeof(uint32_t);
+				num_remaining -= sizeof(uint32_t);
+			} else {
+				/* Buffer can only store partial word */
+				uint32_t rnd_number = ioread32(rng_base +
+							RNG_FIFO_DATA_OFFSET);
+				memcpy(buf, &rnd_number, num_remaining);
+				buf += num_remaining;
+				num_remaining = 0;
+			}
+
+			/* Reset the IDLE timeout */
+			idle_endtime = jiffies + MAX_IDLE_TIME;
+		} else {
+			if (!wait)
+				/* Cannot wait, return immediately */
+				return max - num_remaining;
+
+			/* Can wait, give others chance to run */
+			cpu_relax();
+		}
+	}
+
+	return max - num_remaining;
+}
+
+static struct hwrng iproc_rng200_ops = {
+	.name	= "iproc-rng200",
+	.read	= iproc_rng200_read,
+};
+
+static int iproc_rng200_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	void __iomem *rng_base = 0;
+	uint32_t val = 0;
+	int err = 0;
+
+	/* Map peripheral */
+	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	if (!res) {
+		dev_err(dev, "failed to get rng resources");
+		return -ENODEV;
+	}
+
+	rng_base = devm_ioremap_resource(dev, res);
+	if (!rng_base) {
+		dev_err(dev, "failed to remap rng regs");
+		return -ENODEV;
+	}
+
+	iproc_rng200_ops.priv = (unsigned long)rng_base;
+
+	/* Setup RNG. */
+	val = ioread32(rng_base + RNG_CTRL_OFFSET);
+	val &= ~RNG_CTRL_RNG_RBGEN_MASK;
+	val |= RNG_CTRL_RNG_RBGEN_ENABLE;
+	iowrite32(val, rng_base + RNG_CTRL_OFFSET);
+
+	/* Register driver */
+	err = hwrng_register(&iproc_rng200_ops);
+	if (err) {
+		dev_err(dev, "hwrng registration failed\n");
+		return err;
+	}
+	dev_info(dev, "hwrng registered\n");
+
+	return 0;
+}
+
+static int iproc_rng200_remove(struct platform_device *pdev)
+{
+	uint32_t val = 0;
+	void __iomem *rng_base = (void __iomem *)iproc_rng200_ops.priv;
+
+	/* Unregister driver */
+	hwrng_unregister(&iproc_rng200_ops);
+
+	/* Disable RNG hardware */
+	val = ioread32(rng_base + RNG_CTRL_OFFSET);
+	val &= ~RNG_CTRL_RNG_RBGEN_MASK;
+	val |= RNG_CTRL_RNG_RBGEN_DISABLE;
+	iowrite32(val, rng_base + RNG_CTRL_OFFSET);
+
+	return 0;
+}
+
+static const struct of_device_id iproc_rng200_of_match[] = {
+	{ .compatible = "brcm,iproc-rng200", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, iproc_rng200_of_match);
+
+static struct platform_driver iproc_rng200_driver = {
+	.driver = {
+		.name = "iproc-rng200",
+		.of_match_table = iproc_rng200_of_match,
+	},
+	.probe		= iproc_rng200_probe,
+	.remove		= iproc_rng200_remove,
+};
+module_platform_driver(iproc_rng200_driver);
+
+MODULE_AUTHOR("Broadcom");
+MODULE_DESCRIPTION("iProc RNG200 Random Number Generator driver");
+MODULE_LICENSE("GPL v2");
-- 
2.2.2

[PATCH 2/2] hwrng: iproc-rng200 - Add device tree bindings

[Scott Branden]

Documents the IPROC random number generator device tree bindings
used in some Broadcom chipsets.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 .../devicetree/bindings/hwrng/brcm,iproc-rng200.txt          | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwrng/brcm,iproc-rng200.txt

diff --git a/Documentation/devicetree/bindings/hwrng/brcm,iproc-rng200.txt b/Documentation/devicetree/bindings/hwrng/brcm,iproc-rng200.txt
new file mode 100644
index 0000000..e25a456
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwrng/brcm,iproc-rng200.txt
@@ -0,0 +1,12 @@
+HWRNG support for the iproc-rng200 driver
+
+Required properties:
+- compatible : "brcm,iproc-rng200"
+- reg : base address and size of control register block
+
+Example:
+
+rng {
+        compatible = "brcm,iproc-rng200";
+        reg = <0x18032000 0x28>;
+};
-- 
2.2.2

[PATCH 0/2] Add support for Broadcom keypad controller

[Scott Branden]

This series of patchsets contains the Broadcom keypad controller driver
and device tree binding documentation.

Scott Branden (2):
  Input: bcm-keypad: add device tree bindings
  Input: bcm-keypad: Add Broadcom keypad controller

 .../devicetree/bindings/input/brcm,bcm-keypad.txt  | 118 +++++
 drivers/input/keyboard/Kconfig                     |  10 +
 drivers/input/keyboard/Makefile                    |   1 +
 drivers/input/keyboard/bcm-keypad.c                | 489 +++++++++++++++++++++
 4 files changed, 618 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
 create mode 100644 drivers/input/keyboard/bcm-keypad.c

-- 
2.2.2

[PATCH 1/2] Input: bcm-keypad: add device tree bindings

[Scott Branden]

Documents the Broadcom keypad controller device tree bindings.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 .../devicetree/bindings/input/brcm,bcm-keypad.txt  | 118 +++++++++++++++++++++
 1 file changed, 118 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt

diff --git a/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt b/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
new file mode 100644
index 0000000..645829d
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
@@ -0,0 +1,118 @@
+* Broadcom Keypad Controller device tree bindings
+
+Broadcom Keypad controller is used to interface a SoC with a matrix-type
+keypad device. The keypad controller supports multiple row and column lines.
+A key can be placed at each intersection of a unique row and a unique column.
+The keypad controller can sense a key-press and key-release and report the
+event using a interrupt to the cpu.
+
+This binding is based on the matrix-keymap binding with the following
+changes:
+
+keypad,num-rows and keypad,num-columns are required.
+
+Required SoC Specific Properties:
+- compatible: should be "brcm,bcm-keypad"
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- interrupts: The interrupt number to the cpu.
+
+Board Specific Properties:
+- keypad,num-rows: Number of row lines connected to the keypad
+  controller.
+
+- keypad,num-columns: Number of column lines connected to the
+  keypad controller.
+
+- key-interrupt-trigger-type: The type of interrupt trigger asociated with the Keypad matrix.
+
+	KEYPAD_INTERRUPT_NO_TRIGGER	=	0
+	KEYPAD_INTERRUPT_RISING_EDGE	=	1
+	KEYPAD_INTERRUPT_FALLING_EDGE	=	2
+	KEYPAD_INTERRUPT_BOTH_EDGES	=	3
+
+- col-debounce-filter-period: The debounce period for the Column filter.
+
+	KEYPAD_DEBOUNCE_1_ms	=	0
+	KEYPAD_DEBOUNCE_2_ms	=	1
+	KEYPAD_DEBOUNCE_4_ms	=	2
+	KEYPAD_DEBOUNCE_8_ms	=	3
+	KEYPAD_DEBOUNCE_16_ms	=	4
+	KEYPAD_DEBOUNCE_32_ms	=	5
+	KEYPAD_DEBOUNCE_64_ms	=	6
+	KEYPAD_DEBOUNCE_128_ms	=	7
+
+- status-debounce-filter-period: The debounce period for the Status filter.
+
+	KEYPAD_DEBOUNCE_1_ms	=	0
+	KEYPAD_DEBOUNCE_2_ms	=	1
+	KEYPAD_DEBOUNCE_4_ms	=	2
+	KEYPAD_DEBOUNCE_8_ms	=	3
+	KEYPAD_DEBOUNCE_16_ms	=	4
+	KEYPAD_DEBOUNCE_32_ms	=	5
+	KEYPAD_DEBOUNCE_64_ms	=	6
+	KEYPAD_DEBOUNCE_128_ms	=	7
+
+- row-output-enabled: An optional property indicating whether the row or
+  column is being used as output. If specified the row is being used
+  as the output. Else defaults to column.
+
+- pull-up-enabled: An optional property indicating the Keypad scan mode.
+  If specified implies the keypad scan pull-up has been enabled.
+
+- Keys represented as child nodes: Each key connected to the keypad
+  controller is represented as a child node to the keypad controller
+  device node and should include the following properties.
+  - row: the row number to which the key is connected.
+  - column: the column number to which the key is connected.
+  - code: the key-code to be reported when the key is pressed
+    and released.
+
+Example:
+#include "dt-bindings/input/input.h"
+
+/ {
+	keypad: keypad@180ac000 {
+		/* Required SoC specific properties */
+		compatible = "brcm,bcm-keypad";
+
+		/* Required Board specific properties */
+		keypad,num-rows = <5>;
+		keypad,num-columns = <5>;
+		status = "okay";
+
+		linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_F) /* key_forward */
+		MATRIX_KEY(0x00, 0x03, KEY_HOME) /* key_home */
+		MATRIX_KEY(0x00, 0x04, KEY_M) /* key_message */
+		MATRIX_KEY(0x01, 0x00, KEY_A) /* key_contacts */
+		MATRIX_KEY(0x01, 0x01, KEY_1) /* key_1 */
+		MATRIX_KEY(0x01, 0x02, KEY_2) /* key_2 */
+		MATRIX_KEY(0x01, 0x03, KEY_3) /* key_3 */
+		MATRIX_KEY(0x01, 0x04, KEY_S) /* key_speaker */
+		MATRIX_KEY(0x02, 0x00, KEY_P) /* key_phone */
+		MATRIX_KEY(0x02, 0x01, KEY_4) /* key_4 */
+		MATRIX_KEY(0x02, 0x02, KEY_5) /* key_5 */
+		MATRIX_KEY(0x02, 0x03, KEY_6) /* key_6 */
+		MATRIX_KEY(0x02, 0x04, KEY_VOLUMEUP) /* key_vol_up */
+		MATRIX_KEY(0x03, 0x00, KEY_C) /* key_call_log */
+		MATRIX_KEY(0x03, 0x01, KEY_7) /* key_7 */
+		MATRIX_KEY(0x03, 0x02, KEY_8) /* key_8 */
+		MATRIX_KEY(0x03, 0x03, KEY_9) /* key_9 */
+		MATRIX_KEY(0x03, 0x04, KEY_VOLUMEDOWN) /* key_vol_down */
+		MATRIX_KEY(0x04, 0x00, KEY_H) /* key_headset */
+		MATRIX_KEY(0x04, 0x01, KEY_KPASTERISK) /* key_* */
+		MATRIX_KEY(0x04, 0x02, KEY_0) /* key_0 */
+		MATRIX_KEY(0x04, 0x03, KEY_GRAVE) /* key_# */
+		MATRIX_KEY(0x04, 0x04, KEY_MUTE) /* key_mute */
+		>;
+
+		/* Optional board specific properties */
+		key-interrupt-trigger-type = <3>;
+		col-debounce-filter-period = <5>;
+		row-output-enabled;
+		pull-up-enabled;
+
+	};
+};
-- 
2.2.2

[PATCH 2/2] Input: bcm-keypad: Add Broadcom keypad controller

[Scott Branden]

Add driver for Broadcom's keypad controller.

Broadcom Keypad controller is used to interface a SoC with a matrix-type
keypad device. The keypad controller supports multiple row and column lines.
A key can be placed at each intersection of a unique row and a unique column.
The keypad controller can sense a key-press and key-release and report the
event using a interrupt to the cpu.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/input/keyboard/Kconfig      |  10 +
 drivers/input/keyboard/Makefile     |   1 +
 drivers/input/keyboard/bcm-keypad.c | 489 ++++++++++++++++++++++++++++++++++++
 3 files changed, 500 insertions(+)
 create mode 100644 drivers/input/keyboard/bcm-keypad.c

diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index a5d9b3f..3a0c0f2 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -676,4 +676,14 @@ config KEYBOARD_CAP11XX
 	  To compile this driver as a module, choose M here: the
 	  module will be called cap11xx.
 
+config KEYBOARD_BCM
+	tristate "Broadcom keypad driver"
+	select INPUT_MATRIXKMAP
+	default ARCH_BCM_CYGNUS
+	help
+	  Say Y here if you want to use Broadcom keypad.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called bcm-keypad.
+
 endif
diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
index febafa5..3cff8f6 100644
--- a/drivers/input/keyboard/Makefile
+++ b/drivers/input/keyboard/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_KEYBOARD_ADP5589)		+= adp5589-keys.o
 obj-$(CONFIG_KEYBOARD_AMIGA)		+= amikbd.o
 obj-$(CONFIG_KEYBOARD_ATARI)		+= atakbd.o
 obj-$(CONFIG_KEYBOARD_ATKBD)		+= atkbd.o
+obj-$(CONFIG_KEYBOARD_BCM)		+= bcm-keypad.o
 obj-$(CONFIG_KEYBOARD_BFIN)		+= bf54x-keys.o
 obj-$(CONFIG_KEYBOARD_CAP11XX)		+= cap11xx.o
 obj-$(CONFIG_KEYBOARD_CLPS711X)		+= clps711x-keypad.o
diff --git a/drivers/input/keyboard/bcm-keypad.c b/drivers/input/keyboard/bcm-keypad.c
new file mode 100644
index 0000000..b2c4bb7
--- /dev/null
+++ b/drivers/input/keyboard/bcm-keypad.c
@@ -0,0 +1,489 @@
+/*
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/bitops.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/sizes.h>
+#include <linux/stddef.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <asm/memory.h>
+#include <linux/io.h>
+#include <linux/input/matrix_keypad.h>
+
+#define DEFAULT_CLK_HZ                  31250
+/* Repeat period (ms) */
+#define KEY_REPEAT_PERIOD               100
+/* First time press dly (ms) */
+#define KEY_REPEAT_DELAY                400
+#define MAX_ROWS                        8
+#define MAX_COLS                        8
+
+/* Register/field definitions */
+#define KPCR_OFFSET                          0x00000080
+#define KPCR_MODE                       0x00000002
+#define KPCR_MODE_SHIFT                 1
+#define KPCR_MODE_MASK                  1
+#define KPCR_ENABLE                     0x00000001
+#define KPCR_STATUSFILTERENABLE         0x00008000
+#define KPCR_STATUSFILTERTYPE_SHIFT          12
+#define KPCR_COLFILTERENABLE            0x00000800
+#define KPCR_COLFILTERTYPE_SHIFT             8
+#define KPCR_ROWWIDTH_SHIFT                  20
+#define KPCR_COLUMNWIDTH_SHIFT               16
+
+#define KPIOR_OFFSET                         0x00000084
+#define KPIOR_ROWOCONTRL_SHIFT               24
+#define KPIOR_ROWOCONTRL_MASK                0xFF000000
+#define KPIOR_COLUMNOCONTRL_SHIFT            16
+#define KPIOR_COLUMNOCONTRL_MASK             0x00FF0000
+#define KPIOR_COLUMN_IO_DATA_SHIFT           0
+
+#define KPEMR0_OFFSET                        0x00000090
+#define KPEMR1_OFFSET                        0x00000094
+#define KPEMR2_OFFSET                        0x00000098
+#define KPEMR3_OFFSET                        0x0000009C
+#define KPEMR_EDGETYPE_MAX 3
+
+#define KPSSR0_OFFSET                        0x000000A0
+#define KPSSR1_OFFSET                        0x000000A4
+#define KPIMR0_OFFSET                        0x000000B0
+#define KPIMR1_OFFSET                        0x000000B4
+#define KPICR0_OFFSET                        0x000000B8
+#define KPICR1_OFFSET                        0x000000BC
+#define KPISR0_OFFSET                        0x000000C0
+#define KPISR1_OFFSET                        0x000000C4
+
+#define KPCR_STATUSFILTERTYPE_MAX 7
+#define KPCR_COLFILTERTYPE_MAX 7
+
+/* Macros to determine the row/column from a bit that is set in SSR0/1. */
+#define BIT_TO_ROW_SSR0(bit_nr)  (bit_nr >> 3)
+#define BIT_TO_ROW_SSR1(bit_nr)  ((bit_nr >> 3) + 4)
+#define BIT_TO_COL(bit_nr)       (bit_nr % 8)
+
+/* Structure representing various run-time entities */
+struct bcm_kp {
+	void __iomem *base;
+	int irq;
+	struct clk *clk;
+	struct input_dev *input_dev;
+	unsigned long last_state[2];
+	unsigned int n_rows;
+	unsigned int n_cols;
+	u32 kpcr;
+	u32 kpior;
+	u32 kpemr;
+	u32 imr0_val;
+	u32 imr1_val;
+};
+
+/*
+ * Returns the keycode from the input device keymap given the row and
+ * column.
+ */
+static inline int bcm_kp_get_keycode(struct bcm_kp *kp, int row, int col)
+{
+	unsigned int row_shift = get_count_order(kp->n_cols);
+	unsigned short *keymap = kp->input_dev->keycode;
+
+	return keymap[MATRIX_SCAN_CODE(row, col, row_shift)];
+}
+
+static irqreturn_t bcm_kp_isr_thread(int irq, void *dev_id)
+{
+	struct bcm_kp *kp = dev_id;
+	unsigned long state, change;
+	int bit_nr;
+	int pull_mode = (kp->kpcr >> KPCR_MODE_SHIFT) & KPCR_MODE_MASK;
+	int key_press;
+	int row, col;
+	unsigned int keycode;
+
+	/* Clear interrupts */
+	writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET);
+	writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET);
+
+	state = readl(kp->base + KPSSR0_OFFSET);
+	change = kp->last_state[0] ^ state;
+	kp->last_state[0] = state;
+
+	for_each_set_bit(bit_nr, &change, BITS_PER_LONG) {
+		key_press = state & BIT(bit_nr);
+		/* The meaning of SSR register depends on pull mode. */
+		key_press = pull_mode ? !key_press : key_press;
+		row = BIT_TO_ROW_SSR0(bit_nr);
+		col = BIT_TO_COL(bit_nr);
+		keycode = bcm_kp_get_keycode(kp, row, col);
+		input_report_key(kp->input_dev, keycode, key_press);
+	}
+
+	state = readl(kp->base + KPSSR1_OFFSET);
+	change = kp->last_state[1] ^ state;
+	kp->last_state[1] = state;
+
+	for_each_set_bit(bit_nr, &change, BITS_PER_LONG) {
+		key_press = state & BIT(bit_nr);
+		/* The meaning of SSR register depends on pull mode. */
+		key_press = pull_mode ? !key_press : key_press;
+		row = BIT_TO_ROW_SSR1(bit_nr);
+		col = BIT_TO_COL(bit_nr);
+		keycode = bcm_kp_get_keycode(kp, row, col);
+		input_report_key(kp->input_dev, keycode, key_press);
+	}
+
+	input_sync(kp->input_dev);
+
+	return IRQ_HANDLED;
+}
+
+static int bcm_kp_start(struct bcm_kp *kp)
+{
+	int error;
+
+	error = clk_prepare_enable(kp->clk);
+	if (error)
+		return error;
+
+	writel(kp->kpior, kp->base + KPIOR_OFFSET);
+
+	writel(kp->imr0_val, kp->base + KPIMR0_OFFSET);
+	writel(kp->imr1_val, kp->base + KPIMR1_OFFSET);
+
+	writel(kp->kpemr, kp->base + KPEMR0_OFFSET);
+	writel(kp->kpemr, kp->base + KPEMR1_OFFSET);
+	writel(kp->kpemr, kp->base + KPEMR2_OFFSET);
+	writel(kp->kpemr, kp->base + KPEMR3_OFFSET);
+
+	writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET);
+	writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET);
+
+	kp->last_state[0] = readl(kp->base + KPSSR0_OFFSET);
+	kp->last_state[0] = readl(kp->base + KPSSR1_OFFSET);
+
+	writel(kp->kpcr | KPCR_ENABLE, kp->base + KPCR_OFFSET);
+
+	return 0;
+}
+
+static void bcm_kp_stop(const struct bcm_kp *kp)
+{
+	u32 val;
+
+	val = readl(kp->base + KPCR_OFFSET);
+	val &= ~KPCR_ENABLE;
+	writel(0, kp->base + KPCR_OFFSET);
+	writel(0, kp->base + KPIMR0_OFFSET);
+	writel(0, kp->base + KPIMR1_OFFSET);
+	writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET);
+	writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET);
+
+	clk_disable_unprepare(kp->clk);
+}
+
+static int bcm_kp_open(struct input_dev *dev)
+{
+	struct bcm_kp *kp = input_get_drvdata(dev);
+
+	return bcm_kp_start(kp);
+}
+
+static void bcm_kp_close(struct input_dev *dev)
+{
+	struct bcm_kp *kp = input_get_drvdata(dev);
+
+	bcm_kp_stop(kp);
+}
+
+static int bcm_kp_matrix_key_parse_dt(struct bcm_kp *kp)
+{
+	struct device *dev = kp->input_dev->dev.parent;
+	struct device_node *np = dev->of_node;
+	int error;
+	unsigned int dt_val;
+	unsigned int i;
+
+	/* Initialize the KPCR Keypad Configuration Register */
+	kp->kpcr = KPCR_STATUSFILTERENABLE | KPCR_COLFILTERENABLE;
+
+	error = matrix_keypad_parse_of_params(dev, &kp->n_rows, &kp->n_cols);
+	if (error) {
+		dev_err(dev, "failed to parse kp params\n");
+		return error;
+	}
+	/* Set row width for the ASIC block. */
+	kp->kpcr |= (kp->n_rows - 1) << KPCR_ROWWIDTH_SHIFT;
+
+	/* Set column width for the ASIC block. */
+	kp->kpcr |= (kp->n_cols - 1) << KPCR_COLUMNWIDTH_SHIFT;
+
+	/* Configure the IMR registers */
+	{
+		unsigned int num_rows, col_mask, rows_set;
+
+		/* IMR registers contain interrupt enable bits for 8x8 matrix
+		 * IMR0 register format: <row3> <row2> <row1> <row0>
+		 * IMR1 register format: <row7> <row6> <row5> <row4>
+		 */
+
+		col_mask = (1 << (kp->n_cols)) - 1;
+		num_rows = kp->n_rows;
+
+		/* Set column bits in rows 0 to 3 in IMR0 */
+		kp->imr0_val = col_mask;
+
+		rows_set = 1;
+		while ((--num_rows) && (rows_set++ < 4))
+			kp->imr0_val |= (kp->imr0_val << MAX_COLS);
+
+		/* Set column bits in rows 4 to 7 in IMR1 */
+		kp->imr1_val = 0;
+		if (num_rows) {
+			kp->imr1_val = col_mask;
+			while (--num_rows)
+				kp->imr1_val |= (kp->imr1_val << MAX_COLS);
+		}
+	}
+
+	/*
+	 * Obtain the interrupt trigger type specified and verify against the
+	 * possible values specified in the DT binding.
+	 */
+	of_property_read_u32(np, "key-interrupt-trigger-type",
+		&dt_val);
+	if ((dt_val == 0) || (dt_val > KPEMR_EDGETYPE_MAX)) {
+		dev_err(dev, "Invalid interrupt trigger type %d\n", dt_val);
+		return -EINVAL;
+	}
+	/* Initialize the KPEMR Keypress Edge Mode Registers */
+	kp->kpemr = 0;
+	for (i = 0; i <= 30; i = i + 2)
+		kp->kpemr |= (dt_val << i);
+
+	/*
+	 * Obtain the Status filter debounce value and verify against the
+	 * possible values specified in the DT binding.
+	 */
+	of_property_read_u32(np, "status-debounce-filter-period",
+		&dt_val);
+	if (dt_val > KPCR_STATUSFILTERTYPE_MAX) {
+		dev_err(dev, "Invalid Status filter debounce value %d\n",
+			dt_val);
+		return -EINVAL;
+	}
+	kp->kpcr |= dt_val << KPCR_STATUSFILTERTYPE_SHIFT;
+
+
+	/*
+	 * Obtain the Column filter debounce value and verify against the
+	 * possible values specified in the DT binding.
+	 */
+	of_property_read_u32(np, "col-debounce-filter-period",
+		&dt_val);
+
+	if (dt_val > KPCR_COLFILTERTYPE_MAX) {
+		dev_err(dev, "Invalid Column filter debounce value %d\n",
+			dt_val);
+		return -EINVAL;
+	}
+	kp->kpcr |= dt_val << KPCR_COLFILTERTYPE_SHIFT;
+
+	/*
+	 * Determine between the row and column,
+	 * which should be configured as output.
+	 */
+	if (of_property_read_bool(np, "row-output-enabled")) {
+		/*
+		* Set RowOContrl or ColumnOContrl in KPIOR
+		* to the number of pins to drive as outputs
+		*/
+		kp->kpior = (((1 << kp->n_rows) - 1) <<
+				KPIOR_ROWOCONTRL_SHIFT);
+	} else {
+		kp->kpior = (((1 << kp->n_cols) - 1) <<
+				KPIOR_COLUMNOCONTRL_SHIFT);
+	}
+
+	/*
+	 * Determine if the scan pull up needs to be enabled
+	 */
+	if (of_property_read_bool(np, "pull-up-enabled"))
+		kp->kpcr |= KPCR_MODE;
+
+	dev_dbg(dev, "n_rows=%d n_col=%d kpcr=%x kpior=%x kpemr=%x\n",
+		kp->n_rows, kp->n_cols,
+		kp->kpcr, kp->kpior, kp->kpemr);
+
+	return 0;
+}
+
+
+static int bcm_kp_probe(struct platform_device *pdev)
+{
+	struct bcm_kp *kp;
+	struct input_dev *input_dev;
+	struct resource *res;
+	int error;
+
+	kp = devm_kzalloc(&pdev->dev, sizeof(*kp),
+				   GFP_KERNEL);
+	if (!kp)
+		return -ENOMEM;
+
+	input_dev = devm_input_allocate_device(&pdev->dev);
+	if (!input_dev) {
+		dev_err(&pdev->dev, "failed to allocate the input device\n");
+		return -ENOMEM;
+	}
+	__set_bit(EV_KEY, input_dev->evbit);
+	__set_bit(EV_REP, input_dev->evbit);
+	input_dev->rep[REP_PERIOD] = KEY_REPEAT_PERIOD;
+	input_dev->rep[REP_DELAY] = KEY_REPEAT_DELAY;
+	input_dev->name = pdev->name;
+	input_dev->phys = "keypad/input0";
+	input_dev->dev.parent = &pdev->dev;
+	input_dev->open = bcm_kp_open;
+	input_dev->close = bcm_kp_close;
+
+	input_dev->id.bustype = BUS_HOST;
+	input_dev->id.vendor = 0x0001;
+	input_dev->id.product = 0x0001;
+	input_dev->id.version = 0x0100;
+
+	input_set_drvdata(input_dev, kp);
+
+	kp->input_dev = input_dev;
+
+	platform_set_drvdata(pdev, kp);
+
+	error = bcm_kp_matrix_key_parse_dt(kp);
+	if (error)
+		return error;
+
+	error = matrix_keypad_build_keymap(NULL, NULL,
+					   kp->n_rows,
+					   kp->n_cols,
+					   NULL, input_dev);
+	if (error) {
+		dev_err(&pdev->dev, "failed to build keymap\n");
+		return error;
+	}
+
+	/* Get the KEYPAD base address */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "Missing keypad base address resource\n");
+		return -ENODEV;
+	}
+
+	kp->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(kp->base))
+		return PTR_ERR(kp->base);
+
+	/* Enable clock */
+
+	kp->clk = devm_clk_get(&pdev->dev, "peri_clk");
+	if (IS_ERR(kp->clk))
+		dev_info(&pdev->dev,
+			"No clock specified. Assuming it's enabled\n");
+	else {
+		unsigned int desired_rate;
+		long actual_rate;
+
+		error = of_property_read_u32(pdev->dev.of_node,
+				"clock-frequency", &desired_rate);
+		if (error < 0)
+			desired_rate = DEFAULT_CLK_HZ;
+
+		actual_rate = clk_round_rate(kp->clk, desired_rate);
+		if (actual_rate <= 0)
+			return -EINVAL;
+
+		error = clk_set_rate(kp->clk, actual_rate);
+		if (error)
+			return -EINVAL;
+
+		error = clk_prepare_enable(kp->clk);
+		if (error)
+			return -EINVAL;
+	}
+
+	/* Put the kp into a known sane state */
+	bcm_kp_stop(kp);
+
+	kp->irq = platform_get_irq(pdev, 0);
+	if (kp->irq < 0) {
+		dev_err(&pdev->dev, "no IRQ specified\n");
+		return -EINVAL;
+	}
+
+	error = devm_request_threaded_irq(&pdev->dev, kp->irq, NULL,
+		bcm_kp_isr_thread,
+		IRQF_ONESHOT, pdev->name, kp);
+	if (error) {
+		dev_err(&pdev->dev, "failed to request IRQ\n");
+		return error;
+	}
+
+	error = input_register_device(input_dev);
+	if (error) {
+		dev_err(&pdev->dev, "failed to register input device\n");
+		return error;
+	}
+
+	return 0;
+}
+
+/* Called to perform module cleanup when the module is unloaded. */
+static int bcm_kp_remove(struct platform_device *pdev)
+{
+	struct bcm_kp *kp = platform_get_drvdata(pdev);
+
+	pr_info("bcm_kp_remove\n");
+
+	/* Unregister everything */
+	input_unregister_device(kp->input_dev);
+	clk_disable_unprepare(kp->clk);
+
+	return 0;
+}
+
+static const struct of_device_id bcm_kp_of_match[] = {
+	{ .compatible = "brcm,bcm-keypad" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, bcm_kp_of_match);
+
+static struct platform_driver bcm_kp_device_driver = {
+	.probe		= bcm_kp_probe,
+	.remove = bcm_kp_remove,
+	.driver		= {
+		.name	= "bcm-keypad",
+		.of_match_table = of_match_ptr(bcm_kp_of_match),
+	}
+};
+
+module_platform_driver(bcm_kp_device_driver);
+
+MODULE_AUTHOR("Broadcom Corporation");
+MODULE_DESCRIPTION("BCM Keypad Driver");
+MODULE_LICENSE("GPL");
-- 
2.2.2

Re: [PATCH 1/2] hwrng: iproc-rng200 - Add Broadcom IPROC RNG driver

[Joe Perches]

On Mon, 2015-02-09 at 16:07 -0800, Scott Branden wrote:
> This adds a driver for random number generator present on Broadcom
> IPROC devices.

trivia:

> diff --git a/drivers/char/hw_random/iproc-rng200.c b/drivers/char/hw_random/iproc-rng200.c
[]
> +static int iproc_rng200_probe(struct platform_device *pdev)
> +{
[]
> +	if (!res) {
> +		dev_err(dev, "failed to get rng resources");

Missing terminating newline:

		dev_err(dev, "failed to get rng resources\n");

> +	rng_base = devm_ioremap_resource(dev, res);
> +	if (!rng_base) {
> +		dev_err(dev, "failed to remap rng regs");

here too.

Re: [PATCH 1/2] Input: bcm-keypad: add device tree bindings

[Dmitry Torokhov]

Hi Scott,

On Mon, Feb 09, 2015 at 04:07:40PM -0800, Scott Branden wrote:
> Documents the Broadcom keypad controller device tree bindings.
> 
> Reviewed-by: Ray Jui <rjui@broadcom.com>
> Signed-off-by: Scott Branden <sbranden@broadcom.com>
> ---
>  .../devicetree/bindings/input/brcm,bcm-keypad.txt  | 118 +++++++++++++++++++++
>  1 file changed, 118 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
> 
> diff --git a/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt b/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
> new file mode 100644
> index 0000000..645829d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
> @@ -0,0 +1,118 @@
> +* Broadcom Keypad Controller device tree bindings
> +
> +Broadcom Keypad controller is used to interface a SoC with a matrix-type
> +keypad device. The keypad controller supports multiple row and column lines.
> +A key can be placed at each intersection of a unique row and a unique column.
> +The keypad controller can sense a key-press and key-release and report the
> +event using a interrupt to the cpu.
> +
> +This binding is based on the matrix-keymap binding with the following
> +changes:
> +
> +keypad,num-rows and keypad,num-columns are required.
> +
> +Required SoC Specific Properties:
> +- compatible: should be "brcm,bcm-keypad"
> +
> +- reg: physical base address of the controller and length of memory mapped
> +  region.
> +
> +- interrupts: The interrupt number to the cpu.
> +
> +Board Specific Properties:
> +- keypad,num-rows: Number of row lines connected to the keypad
> +  controller.
> +
> +- keypad,num-columns: Number of column lines connected to the
> +  keypad controller.
> +
> +- key-interrupt-trigger-type: The type of interrupt trigger asociated with the Keypad matrix.
> +
> +	KEYPAD_INTERRUPT_NO_TRIGGER	=	0
> +	KEYPAD_INTERRUPT_RISING_EDGE	=	1
> +	KEYPAD_INTERRUPT_FALLING_EDGE	=	2
> +	KEYPAD_INTERRUPT_BOTH_EDGES	=	3

Can we get this data from the interrupt spec?

> +
> +- col-debounce-filter-period: The debounce period for the Column filter.
> +
> +	KEYPAD_DEBOUNCE_1_ms	=	0
> +	KEYPAD_DEBOUNCE_2_ms	=	1
> +	KEYPAD_DEBOUNCE_4_ms	=	2
> +	KEYPAD_DEBOUNCE_8_ms	=	3

> +	KEYPAD_DEBOUNCE_16_ms	=	4
> +	KEYPAD_DEBOUNCE_32_ms	=	5
> +	KEYPAD_DEBOUNCE_64_ms	=	6
> +	KEYPAD_DEBOUNCE_128_ms	=	7
> +
> +- status-debounce-filter-period: The debounce period for the Status filter.
> +
> +	KEYPAD_DEBOUNCE_1_ms	=	0
> +	KEYPAD_DEBOUNCE_2_ms	=	1
> +	KEYPAD_DEBOUNCE_4_ms	=	2
> +	KEYPAD_DEBOUNCE_8_ms	=	3
> +	KEYPAD_DEBOUNCE_16_ms	=	4
> +	KEYPAD_DEBOUNCE_32_ms	=	5
> +	KEYPAD_DEBOUNCE_64_ms	=	6
> +	KEYPAD_DEBOUNCE_128_ms	=	7

I could swear device-specific properties should be in form of
<vendor-prefix>,<property-name> to ensure it won't clash with changes on
subsystem level later on. Device-tree folks, what say you?

> +
> +- row-output-enabled: An optional property indicating whether the row or
> +  column is being used as output. If specified the row is being used
> +  as the output. Else defaults to column.
> +
> +- pull-up-enabled: An optional property indicating the Keypad scan mode.
> +  If specified implies the keypad scan pull-up has been enabled.
> +
> +- Keys represented as child nodes: Each key connected to the keypad
> +  controller is represented as a child node to the keypad controller
> +  device node and should include the following properties.
> +  - row: the row number to which the key is connected.
> +  - column: the column number to which the key is connected.
> +  - code: the key-code to be reported when the key is pressed
> +    and released.

That does not seem to be right, linux,keymap is a list, not a subtree.
I'd simply refer to
Documentation/devicetree/bindings/input/matrix-keymap.txt for details.

> +
> +Example:
> +#include "dt-bindings/input/input.h"
> +
> +/ {
> +	keypad: keypad@180ac000 {
> +		/* Required SoC specific properties */
> +		compatible = "brcm,bcm-keypad";
> +
> +		/* Required Board specific properties */
> +		keypad,num-rows = <5>;
> +		keypad,num-columns = <5>;
> +		status = "okay";
> +
> +		linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_F) /* key_forward */
> +		MATRIX_KEY(0x00, 0x03, KEY_HOME) /* key_home */
> +		MATRIX_KEY(0x00, 0x04, KEY_M) /* key_message */
> +		MATRIX_KEY(0x01, 0x00, KEY_A) /* key_contacts */
> +		MATRIX_KEY(0x01, 0x01, KEY_1) /* key_1 */
> +		MATRIX_KEY(0x01, 0x02, KEY_2) /* key_2 */
> +		MATRIX_KEY(0x01, 0x03, KEY_3) /* key_3 */
> +		MATRIX_KEY(0x01, 0x04, KEY_S) /* key_speaker */
> +		MATRIX_KEY(0x02, 0x00, KEY_P) /* key_phone */
> +		MATRIX_KEY(0x02, 0x01, KEY_4) /* key_4 */
> +		MATRIX_KEY(0x02, 0x02, KEY_5) /* key_5 */
> +		MATRIX_KEY(0x02, 0x03, KEY_6) /* key_6 */
> +		MATRIX_KEY(0x02, 0x04, KEY_VOLUMEUP) /* key_vol_up */
> +		MATRIX_KEY(0x03, 0x00, KEY_C) /* key_call_log */
> +		MATRIX_KEY(0x03, 0x01, KEY_7) /* key_7 */
> +		MATRIX_KEY(0x03, 0x02, KEY_8) /* key_8 */
> +		MATRIX_KEY(0x03, 0x03, KEY_9) /* key_9 */
> +		MATRIX_KEY(0x03, 0x04, KEY_VOLUMEDOWN) /* key_vol_down */
> +		MATRIX_KEY(0x04, 0x00, KEY_H) /* key_headset */
> +		MATRIX_KEY(0x04, 0x01, KEY_KPASTERISK) /* key_* */
> +		MATRIX_KEY(0x04, 0x02, KEY_0) /* key_0 */
> +		MATRIX_KEY(0x04, 0x03, KEY_GRAVE) /* key_# */
> +		MATRIX_KEY(0x04, 0x04, KEY_MUTE) /* key_mute */
> +		>;
> +
> +		/* Optional board specific properties */
> +		key-interrupt-trigger-type = <3>;
> +		col-debounce-filter-period = <5>;
> +		row-output-enabled;
> +		pull-up-enabled;
> +
> +	};
> +};
> -- 
> 2.2.2
> 

Thanks.

-- 
Dmitry

Re: [PATCH 2/2] Input: bcm-keypad: Add Broadcom keypad controller

[Dmitry Torokhov]

Hi Scott,

On Mon, Feb 09, 2015 at 04:07:41PM -0800, Scott Branden wrote:
> Add driver for Broadcom's keypad controller.
> 
> Broadcom Keypad controller is used to interface a SoC with a matrix-type
> keypad device. The keypad controller supports multiple row and column lines.
> A key can be placed at each intersection of a unique row and a unique column.
> The keypad controller can sense a key-press and key-release and report the
> event using a interrupt to the cpu.
> 
> Reviewed-by: Ray Jui <rjui@broadcom.com>
> Signed-off-by: Scott Branden <sbranden@broadcom.com>
> ---
>  drivers/input/keyboard/Kconfig      |  10 +
>  drivers/input/keyboard/Makefile     |   1 +
>  drivers/input/keyboard/bcm-keypad.c | 489 ++++++++++++++++++++++++++++++++++++
>  3 files changed, 500 insertions(+)
>  create mode 100644 drivers/input/keyboard/bcm-keypad.c
> 
> diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
> index a5d9b3f..3a0c0f2 100644
> --- a/drivers/input/keyboard/Kconfig
> +++ b/drivers/input/keyboard/Kconfig
> @@ -676,4 +676,14 @@ config KEYBOARD_CAP11XX
>  	  To compile this driver as a module, choose M here: the
>  	  module will be called cap11xx.
>  
> +config KEYBOARD_BCM
> +	tristate "Broadcom keypad driver"
> +	select INPUT_MATRIXKMAP
> +	default ARCH_BCM_CYGNUS
> +	help
> +	  Say Y here if you want to use Broadcom keypad.
> +
> +	  To compile this driver as a module, choose M here: the
> +	  module will be called bcm-keypad.
> +
>  endif
> diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
> index febafa5..3cff8f6 100644
> --- a/drivers/input/keyboard/Makefile
> +++ b/drivers/input/keyboard/Makefile
> @@ -10,6 +10,7 @@ obj-$(CONFIG_KEYBOARD_ADP5589)		+= adp5589-keys.o
>  obj-$(CONFIG_KEYBOARD_AMIGA)		+= amikbd.o
>  obj-$(CONFIG_KEYBOARD_ATARI)		+= atakbd.o
>  obj-$(CONFIG_KEYBOARD_ATKBD)		+= atkbd.o
> +obj-$(CONFIG_KEYBOARD_BCM)		+= bcm-keypad.o
>  obj-$(CONFIG_KEYBOARD_BFIN)		+= bf54x-keys.o
>  obj-$(CONFIG_KEYBOARD_CAP11XX)		+= cap11xx.o
>  obj-$(CONFIG_KEYBOARD_CLPS711X)		+= clps711x-keypad.o
> diff --git a/drivers/input/keyboard/bcm-keypad.c b/drivers/input/keyboard/bcm-keypad.c
> new file mode 100644
> index 0000000..b2c4bb7
> --- /dev/null
> +++ b/drivers/input/keyboard/bcm-keypad.c
> @@ -0,0 +1,489 @@
> +/*
> + * Copyright (C) 2014 Broadcom Corporation
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/mm.h>
> +#include <linux/module.h>
> +#include <linux/input.h>
> +#include <linux/interrupt.h>
> +#include <linux/bitops.h>
> +#include <linux/platform_device.h>
> +#include <linux/delay.h>
> +#include <linux/sizes.h>
> +#include <linux/stddef.h>
> +#include <linux/of.h>
> +#include <linux/of_irq.h>
> +#include <linux/slab.h>
> +#include <linux/clk.h>
> +#include <linux/types.h>
> +#include <linux/string.h>
> +#include <asm/memory.h>
> +#include <linux/io.h>
> +#include <linux/input/matrix_keypad.h>
> +
> +#define DEFAULT_CLK_HZ                  31250
> +/* Repeat period (ms) */
> +#define KEY_REPEAT_PERIOD               100
> +/* First time press dly (ms) */
> +#define KEY_REPEAT_DELAY                400
> +#define MAX_ROWS                        8
> +#define MAX_COLS                        8
> +
> +/* Register/field definitions */
> +#define KPCR_OFFSET                          0x00000080
> +#define KPCR_MODE                       0x00000002
> +#define KPCR_MODE_SHIFT                 1
> +#define KPCR_MODE_MASK                  1
> +#define KPCR_ENABLE                     0x00000001
> +#define KPCR_STATUSFILTERENABLE         0x00008000
> +#define KPCR_STATUSFILTERTYPE_SHIFT          12
> +#define KPCR_COLFILTERENABLE            0x00000800
> +#define KPCR_COLFILTERTYPE_SHIFT             8
> +#define KPCR_ROWWIDTH_SHIFT                  20
> +#define KPCR_COLUMNWIDTH_SHIFT               16
> +
> +#define KPIOR_OFFSET                         0x00000084
> +#define KPIOR_ROWOCONTRL_SHIFT               24
> +#define KPIOR_ROWOCONTRL_MASK                0xFF000000
> +#define KPIOR_COLUMNOCONTRL_SHIFT            16
> +#define KPIOR_COLUMNOCONTRL_MASK             0x00FF0000
> +#define KPIOR_COLUMN_IO_DATA_SHIFT           0
> +
> +#define KPEMR0_OFFSET                        0x00000090
> +#define KPEMR1_OFFSET                        0x00000094
> +#define KPEMR2_OFFSET                        0x00000098
> +#define KPEMR3_OFFSET                        0x0000009C
> +#define KPEMR_EDGETYPE_MAX 3
> +
> +#define KPSSR0_OFFSET                        0x000000A0
> +#define KPSSR1_OFFSET                        0x000000A4
> +#define KPIMR0_OFFSET                        0x000000B0
> +#define KPIMR1_OFFSET                        0x000000B4
> +#define KPICR0_OFFSET                        0x000000B8
> +#define KPICR1_OFFSET                        0x000000BC
> +#define KPISR0_OFFSET                        0x000000C0
> +#define KPISR1_OFFSET                        0x000000C4
> +
> +#define KPCR_STATUSFILTERTYPE_MAX 7
> +#define KPCR_COLFILTERTYPE_MAX 7
> +
> +/* Macros to determine the row/column from a bit that is set in SSR0/1. */
> +#define BIT_TO_ROW_SSR0(bit_nr)  (bit_nr >> 3)
> +#define BIT_TO_ROW_SSR1(bit_nr)  ((bit_nr >> 3) + 4)
> +#define BIT_TO_COL(bit_nr)       (bit_nr % 8)
> +
> +/* Structure representing various run-time entities */
> +struct bcm_kp {
> +	void __iomem *base;
> +	int irq;
> +	struct clk *clk;
> +	struct input_dev *input_dev;
> +	unsigned long last_state[2];
> +	unsigned int n_rows;
> +	unsigned int n_cols;
> +	u32 kpcr;
> +	u32 kpior;
> +	u32 kpemr;
> +	u32 imr0_val;
> +	u32 imr1_val;
> +};
> +
> +/*
> + * Returns the keycode from the input device keymap given the row and
> + * column.
> + */
> +static inline int bcm_kp_get_keycode(struct bcm_kp *kp, int row, int col)
> +{
> +	unsigned int row_shift = get_count_order(kp->n_cols);
> +	unsigned short *keymap = kp->input_dev->keycode;
> +
> +	return keymap[MATRIX_SCAN_CODE(row, col, row_shift)];
> +}
> +
> +static irqreturn_t bcm_kp_isr_thread(int irq, void *dev_id)
> +{
> +	struct bcm_kp *kp = dev_id;
> +	unsigned long state, change;
> +	int bit_nr;
> +	int pull_mode = (kp->kpcr >> KPCR_MODE_SHIFT) & KPCR_MODE_MASK;
> +	int key_press;
> +	int row, col;
> +	unsigned int keycode;
> +
> +	/* Clear interrupts */
> +	writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET);
> +	writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET);
> +
> +	state = readl(kp->base + KPSSR0_OFFSET);
> +	change = kp->last_state[0] ^ state;
> +	kp->last_state[0] = state;
> +
> +	for_each_set_bit(bit_nr, &change, BITS_PER_LONG) {
> +		key_press = state & BIT(bit_nr);
> +		/* The meaning of SSR register depends on pull mode. */
> +		key_press = pull_mode ? !key_press : key_press;
> +		row = BIT_TO_ROW_SSR0(bit_nr);
> +		col = BIT_TO_COL(bit_nr);
> +		keycode = bcm_kp_get_keycode(kp, row, col);
> +		input_report_key(kp->input_dev, keycode, key_press);
> +	}
> +
> +	state = readl(kp->base + KPSSR1_OFFSET);
> +	change = kp->last_state[1] ^ state;
> +	kp->last_state[1] = state;
> +
> +	for_each_set_bit(bit_nr, &change, BITS_PER_LONG) {
> +		key_press = state & BIT(bit_nr);
> +		/* The meaning of SSR register depends on pull mode. */
> +		key_press = pull_mode ? !key_press : key_press;
> +		row = BIT_TO_ROW_SSR1(bit_nr);
> +		col = BIT_TO_COL(bit_nr);
> +		keycode = bcm_kp_get_keycode(kp, row, col);
> +		input_report_key(kp->input_dev, keycode, key_press);
> +	}

Please split it into a separate function that processes one bank and
call it twice instead of doing cut-and-paste of almost the same code. Or
even better combine it all into one block (i.e have changes[2], use
bitmap_xor to figure difference, etc...).

> +
> +	input_sync(kp->input_dev);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static int bcm_kp_start(struct bcm_kp *kp)
> +{
> +	int error;
> +
> +	error = clk_prepare_enable(kp->clk);
> +	if (error)
> +		return error;
> +
> +	writel(kp->kpior, kp->base + KPIOR_OFFSET);
> +
> +	writel(kp->imr0_val, kp->base + KPIMR0_OFFSET);
> +	writel(kp->imr1_val, kp->base + KPIMR1_OFFSET);
> +
> +	writel(kp->kpemr, kp->base + KPEMR0_OFFSET);
> +	writel(kp->kpemr, kp->base + KPEMR1_OFFSET);
> +	writel(kp->kpemr, kp->base + KPEMR2_OFFSET);
> +	writel(kp->kpemr, kp->base + KPEMR3_OFFSET);
> +
> +	writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET);
> +	writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET);
> +
> +	kp->last_state[0] = readl(kp->base + KPSSR0_OFFSET);
> +	kp->last_state[0] = readl(kp->base + KPSSR1_OFFSET);
> +
> +	writel(kp->kpcr | KPCR_ENABLE, kp->base + KPCR_OFFSET);
> +
> +	return 0;
> +}
> +
> +static void bcm_kp_stop(const struct bcm_kp *kp)
> +{
> +	u32 val;
> +
> +	val = readl(kp->base + KPCR_OFFSET);
> +	val &= ~KPCR_ENABLE;
> +	writel(0, kp->base + KPCR_OFFSET);
> +	writel(0, kp->base + KPIMR0_OFFSET);
> +	writel(0, kp->base + KPIMR1_OFFSET);
> +	writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET);
> +	writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET);
> +
> +	clk_disable_unprepare(kp->clk);
> +}
> +
> +static int bcm_kp_open(struct input_dev *dev)
> +{
> +	struct bcm_kp *kp = input_get_drvdata(dev);
> +
> +	return bcm_kp_start(kp);
> +}
> +
> +static void bcm_kp_close(struct input_dev *dev)
> +{
> +	struct bcm_kp *kp = input_get_drvdata(dev);
> +
> +	bcm_kp_stop(kp);
> +}
> +
> +static int bcm_kp_matrix_key_parse_dt(struct bcm_kp *kp)
> +{
> +	struct device *dev = kp->input_dev->dev.parent;
> +	struct device_node *np = dev->of_node;
> +	int error;
> +	unsigned int dt_val;
> +	unsigned int i;
> +
> +	/* Initialize the KPCR Keypad Configuration Register */
> +	kp->kpcr = KPCR_STATUSFILTERENABLE | KPCR_COLFILTERENABLE;
> +
> +	error = matrix_keypad_parse_of_params(dev, &kp->n_rows, &kp->n_cols);
> +	if (error) {
> +		dev_err(dev, "failed to parse kp params\n");
> +		return error;
> +	}
> +	/* Set row width for the ASIC block. */
> +	kp->kpcr |= (kp->n_rows - 1) << KPCR_ROWWIDTH_SHIFT;
> +
> +	/* Set column width for the ASIC block. */
> +	kp->kpcr |= (kp->n_cols - 1) << KPCR_COLUMNWIDTH_SHIFT;
> +
> +	/* Configure the IMR registers */
> +	{
> +		unsigned int num_rows, col_mask, rows_set;
> +
> +		/* IMR registers contain interrupt enable bits for 8x8 matrix
> +		 * IMR0 register format: <row3> <row2> <row1> <row0>
> +		 * IMR1 register format: <row7> <row6> <row5> <row4>
> +		 */
> +
> +		col_mask = (1 << (kp->n_cols)) - 1;
> +		num_rows = kp->n_rows;
> +
> +		/* Set column bits in rows 0 to 3 in IMR0 */
> +		kp->imr0_val = col_mask;
> +
> +		rows_set = 1;
> +		while ((--num_rows) && (rows_set++ < 4))
> +			kp->imr0_val |= (kp->imr0_val << MAX_COLS);
> +
> +		/* Set column bits in rows 4 to 7 in IMR1 */
> +		kp->imr1_val = 0;
> +		if (num_rows) {
> +			kp->imr1_val = col_mask;
> +			while (--num_rows)
> +				kp->imr1_val |= (kp->imr1_val << MAX_COLS);
> +		}
> +	}
> +
> +	/*
> +	 * Obtain the interrupt trigger type specified and verify against the
> +	 * possible values specified in the DT binding.
> +	 */
> +	of_property_read_u32(np, "key-interrupt-trigger-type",
> +		&dt_val);
> +	if ((dt_val == 0) || (dt_val > KPEMR_EDGETYPE_MAX)) {
> +		dev_err(dev, "Invalid interrupt trigger type %d\n", dt_val);
> +		return -EINVAL;
> +	}
> +	/* Initialize the KPEMR Keypress Edge Mode Registers */
> +	kp->kpemr = 0;
> +	for (i = 0; i <= 30; i = i + 2)
> +		kp->kpemr |= (dt_val << i);
> +
> +	/*
> +	 * Obtain the Status filter debounce value and verify against the
> +	 * possible values specified in the DT binding.
> +	 */
> +	of_property_read_u32(np, "status-debounce-filter-period",
> +		&dt_val);
> +	if (dt_val > KPCR_STATUSFILTERTYPE_MAX) {
> +		dev_err(dev, "Invalid Status filter debounce value %d\n",
> +			dt_val);
> +		return -EINVAL;
> +	}
> +	kp->kpcr |= dt_val << KPCR_STATUSFILTERTYPE_SHIFT;
> +
> +
> +	/*
> +	 * Obtain the Column filter debounce value and verify against the
> +	 * possible values specified in the DT binding.
> +	 */
> +	of_property_read_u32(np, "col-debounce-filter-period",
> +		&dt_val);
> +
> +	if (dt_val > KPCR_COLFILTERTYPE_MAX) {
> +		dev_err(dev, "Invalid Column filter debounce value %d\n",
> +			dt_val);
> +		return -EINVAL;
> +	}
> +	kp->kpcr |= dt_val << KPCR_COLFILTERTYPE_SHIFT;
> +
> +	/*
> +	 * Determine between the row and column,
> +	 * which should be configured as output.
> +	 */
> +	if (of_property_read_bool(np, "row-output-enabled")) {
> +		/*
> +		* Set RowOContrl or ColumnOContrl in KPIOR
> +		* to the number of pins to drive as outputs
> +		*/
> +		kp->kpior = (((1 << kp->n_rows) - 1) <<
> +				KPIOR_ROWOCONTRL_SHIFT);
> +	} else {
> +		kp->kpior = (((1 << kp->n_cols) - 1) <<
> +				KPIOR_COLUMNOCONTRL_SHIFT);
> +	}
> +
> +	/*
> +	 * Determine if the scan pull up needs to be enabled
> +	 */
> +	if (of_property_read_bool(np, "pull-up-enabled"))
> +		kp->kpcr |= KPCR_MODE;
> +
> +	dev_dbg(dev, "n_rows=%d n_col=%d kpcr=%x kpior=%x kpemr=%x\n",
> +		kp->n_rows, kp->n_cols,
> +		kp->kpcr, kp->kpior, kp->kpemr);
> +
> +	return 0;
> +}
> +
> +
> +static int bcm_kp_probe(struct platform_device *pdev)
> +{
> +	struct bcm_kp *kp;
> +	struct input_dev *input_dev;
> +	struct resource *res;
> +	int error;
> +
> +	kp = devm_kzalloc(&pdev->dev, sizeof(*kp),
> +				   GFP_KERNEL);
> +	if (!kp)
> +		return -ENOMEM;
> +
> +	input_dev = devm_input_allocate_device(&pdev->dev);
> +	if (!input_dev) {
> +		dev_err(&pdev->dev, "failed to allocate the input device\n");
> +		return -ENOMEM;
> +	}
> +	__set_bit(EV_KEY, input_dev->evbit);
> +	__set_bit(EV_REP, input_dev->evbit);
> +	input_dev->rep[REP_PERIOD] = KEY_REPEAT_PERIOD;
> +	input_dev->rep[REP_DELAY] = KEY_REPEAT_DELAY;

That does not do what you think: if you set up custom delay and period
you are supposed to supply your own timer as well. Either adjust values
after registering input device, or leave defaults.

Also it might be a good idea to have "linux,autorepeat" DT property to
control it.

> +	input_dev->name = pdev->name;
> +	input_dev->phys = "keypad/input0";
> +	input_dev->dev.parent = &pdev->dev;
> +	input_dev->open = bcm_kp_open;
> +	input_dev->close = bcm_kp_close;
> +
> +	input_dev->id.bustype = BUS_HOST;
> +	input_dev->id.vendor = 0x0001;
> +	input_dev->id.product = 0x0001;
> +	input_dev->id.version = 0x0100;
> +
> +	input_set_drvdata(input_dev, kp);
> +
> +	kp->input_dev = input_dev;
> +
> +	platform_set_drvdata(pdev, kp);
> +
> +	error = bcm_kp_matrix_key_parse_dt(kp);
> +	if (error)
> +		return error;
> +
> +	error = matrix_keypad_build_keymap(NULL, NULL,
> +					   kp->n_rows,
> +					   kp->n_cols,
> +					   NULL, input_dev);
> +	if (error) {
> +		dev_err(&pdev->dev, "failed to build keymap\n");
> +		return error;
> +	}
> +
> +	/* Get the KEYPAD base address */
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!res) {
> +		dev_err(&pdev->dev, "Missing keypad base address resource\n");
> +		return -ENODEV;
> +	}
> +
> +	kp->base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(kp->base))
> +		return PTR_ERR(kp->base);
> +
> +	/* Enable clock */
> +
> +	kp->clk = devm_clk_get(&pdev->dev, "peri_clk");
> +	if (IS_ERR(kp->clk))
> +		dev_info(&pdev->dev,
> +			"No clock specified. Assuming it's enabled\n");
> +	else {
> +		unsigned int desired_rate;
> +		long actual_rate;
> +
> +		error = of_property_read_u32(pdev->dev.of_node,
> +				"clock-frequency", &desired_rate);
> +		if (error < 0)
> +			desired_rate = DEFAULT_CLK_HZ;
> +
> +		actual_rate = clk_round_rate(kp->clk, desired_rate);
> +		if (actual_rate <= 0)
> +			return -EINVAL;
> +
> +		error = clk_set_rate(kp->clk, actual_rate);
> +		if (error)
> +			return -EINVAL;
> +
> +		error = clk_prepare_enable(kp->clk);
> +		if (error)
> +			return -EINVAL;
> +	}
> +
> +	/* Put the kp into a known sane state */
> +	bcm_kp_stop(kp);
> +
> +	kp->irq = platform_get_irq(pdev, 0);
> +	if (kp->irq < 0) {
> +		dev_err(&pdev->dev, "no IRQ specified\n");
> +		return -EINVAL;
> +	}
> +
> +	error = devm_request_threaded_irq(&pdev->dev, kp->irq, NULL,
> +		bcm_kp_isr_thread,
> +		IRQF_ONESHOT, pdev->name, kp);
> +	if (error) {
> +		dev_err(&pdev->dev, "failed to request IRQ\n");
> +		return error;
> +	}
> +
> +	error = input_register_device(input_dev);
> +	if (error) {
> +		dev_err(&pdev->dev, "failed to register input device\n");
> +		return error;
> +	}
> +
> +	return 0;
> +}
> +
> +/* Called to perform module cleanup when the module is unloaded. */
> +static int bcm_kp_remove(struct platform_device *pdev)
> +{
> +	struct bcm_kp *kp = platform_get_drvdata(pdev);
> +
> +	pr_info("bcm_kp_remove\n");
> +
> +	/* Unregister everything */
> +	input_unregister_device(kp->input_dev);
> +	clk_disable_unprepare(kp->clk);

You already calling clk_disable_unprepare() as part of bcm_kp_close()
(in stop()), so you do not need it here. input_unregister_device() will
also be called automatically since you are using managed input device,
so please remove bcm_kp_remove altogether.

> +
> +	return 0;
> +}
> +
> +static const struct of_device_id bcm_kp_of_match[] = {
> +	{ .compatible = "brcm,bcm-keypad" },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, bcm_kp_of_match);
> +
> +static struct platform_driver bcm_kp_device_driver = {
> +	.probe		= bcm_kp_probe,
> +	.remove = bcm_kp_remove,
> +	.driver		= {
> +		.name	= "bcm-keypad",
> +		.of_match_table = of_match_ptr(bcm_kp_of_match),
> +	}
> +};
> +
> +module_platform_driver(bcm_kp_device_driver);
> +
> +MODULE_AUTHOR("Broadcom Corporation");
> +MODULE_DESCRIPTION("BCM Keypad Driver");
> +MODULE_LICENSE("GPL");
> -- 
> 2.2.2
> 

Thanks.

-- 
Dmitry

Re: [PATCH 1/2] hwrng: iproc-rng200 - Add Broadcom IPROC RNG driver

[Scott Branden]

Hi Joe,

I really don't see the missing terminating newlines in the patch or 
source code.  The lines look the same as every other line???

Regards,
  Scott

On 15-02-09 04:27 PM, Joe Perches wrote:
> On Mon, 2015-02-09 at 16:07 -0800, Scott Branden wrote:
>> This adds a driver for random number generator present on Broadcom
>> IPROC devices.
>
> trivia:
>
>> diff --git a/drivers/char/hw_random/iproc-rng200.c b/drivers/char/hw_random/iproc-rng200.c
> []
>> +static int iproc_rng200_probe(struct platform_device *pdev)
>> +{
> []
>> +	if (!res) {
>> +		dev_err(dev, "failed to get rng resources");
>
> Missing terminating newline:
>
> 		dev_err(dev, "failed to get rng resources\n");
>
>> +	rng_base = devm_ioremap_resource(dev, res);
>> +	if (!rng_base) {
>> +		dev_err(dev, "failed to remap rng regs");
>
> here too.
>
>

Re: [PATCH 1/2] Input: bcm-keypad: add device tree bindings

[Scott Branden]

Hi Dmitry,

Comments inline.  I still have an issue with vendor prefix as there are 
not documented guidelines I can find in this area?


On 15-02-09 04:51 PM, Dmitry Torokhov wrote:
> Hi Scott,
>
> On Mon, Feb 09, 2015 at 04:07:40PM -0800, Scott Branden wrote:
>> Documents the Broadcom keypad controller device tree bindings.
>>
>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>> ---
>>   .../devicetree/bindings/input/brcm,bcm-keypad.txt  | 118 +++++++++++++++++++++
>>   1 file changed, 118 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
>>
>> diff --git a/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt b/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
>> new file mode 100644
>> index 0000000..645829d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
>> @@ -0,0 +1,118 @@
>> +* Broadcom Keypad Controller device tree bindings
>> +
>> +Broadcom Keypad controller is used to interface a SoC with a matrix-type
>> +keypad device. The keypad controller supports multiple row and column lines.
>> +A key can be placed at each intersection of a unique row and a unique column.
>> +The keypad controller can sense a key-press and key-release and report the
>> +event using a interrupt to the cpu.
>> +
>> +This binding is based on the matrix-keymap binding with the following
>> +changes:
>> +
>> +keypad,num-rows and keypad,num-columns are required.
>> +
>> +Required SoC Specific Properties:
>> +- compatible: should be "brcm,bcm-keypad"
>> +
>> +- reg: physical base address of the controller and length of memory mapped
>> +  region.
>> +
>> +- interrupts: The interrupt number to the cpu.
>> +
>> +Board Specific Properties:
>> +- keypad,num-rows: Number of row lines connected to the keypad
>> +  controller.
>> +
>> +- keypad,num-columns: Number of column lines connected to the
>> +  keypad controller.
>> +
>> +- key-interrupt-trigger-type: The type of interrupt trigger asociated with the Keypad matrix.
>> +
>> +	KEYPAD_INTERRUPT_NO_TRIGGER	=	0
>> +	KEYPAD_INTERRUPT_RISING_EDGE	=	1
>> +	KEYPAD_INTERRUPT_FALLING_EDGE	=	2
>> +	KEYPAD_INTERRUPT_BOTH_EDGES	=	3
>
> Can we get this data from the interrupt spec?
I don't understand your question. Could you elaborate?
But, looking at this closer this determines when the hardware should 
generate interrupts.  I think we would always need to set it to both 
edges and this binding option can probably we removed?
>
>> +
>> +- col-debounce-filter-period: The debounce period for the Column filter.
>> +
>> +	KEYPAD_DEBOUNCE_1_ms	=	0
>> +	KEYPAD_DEBOUNCE_2_ms	=	1
>> +	KEYPAD_DEBOUNCE_4_ms	=	2
>> +	KEYPAD_DEBOUNCE_8_ms	=	3
>
>> +	KEYPAD_DEBOUNCE_16_ms	=	4
>> +	KEYPAD_DEBOUNCE_32_ms	=	5
>> +	KEYPAD_DEBOUNCE_64_ms	=	6
>> +	KEYPAD_DEBOUNCE_128_ms	=	7
>> +
>> +- status-debounce-filter-period: The debounce period for the Status filter.
>> +
>> +	KEYPAD_DEBOUNCE_1_ms	=	0
>> +	KEYPAD_DEBOUNCE_2_ms	=	1
>> +	KEYPAD_DEBOUNCE_4_ms	=	2
>> +	KEYPAD_DEBOUNCE_8_ms	=	3
>> +	KEYPAD_DEBOUNCE_16_ms	=	4
>> +	KEYPAD_DEBOUNCE_32_ms	=	5
>> +	KEYPAD_DEBOUNCE_64_ms	=	6
>> +	KEYPAD_DEBOUNCE_128_ms	=	7
>
> I could swear device-specific properties should be in form of
> <vendor-prefix>,<property-name> to ensure it won't clash with changes on
> subsystem level later on. Device-tree folks, what say you?
I see examples with and without vendor-prefix.
qcom,pm8xxx-keypad.txt does not have prefixes
st-keyscan.txt does have a prefix

I can't find any documented guidelines for this.
Clash changes should not happen because as new standard properties are 
added the drivers should be adjusted to use the new dt-bindings?
>
>> +
>> +- row-output-enabled: An optional property indicating whether the row or
>> +  column is being used as output. If specified the row is being used
>> +  as the output. Else defaults to column.
>> +
>> +- pull-up-enabled: An optional property indicating the Keypad scan mode.
>> +  If specified implies the keypad scan pull-up has been enabled.
>> +
>> +- Keys represented as child nodes: Each key connected to the keypad
>> +  controller is represented as a child node to the keypad controller
>> +  device node and should include the following properties.
>> +  - row: the row number to which the key is connected.
>> +  - column: the column number to which the key is connected.
>> +  - code: the key-code to be reported when the key is pressed
>> +    and released.
>
> That does not seem to be right, linux,keymap is a list, not a subtree.
> I'd simply refer to
> Documentation/devicetree/bindings/input/matrix-keymap.txt for details.
Yes, we moved to matrix-keymap and forgot to update this documentation. 
  Will correct - thanks.
>
>> +
>> +Example:
>> +#include "dt-bindings/input/input.h"
>> +
>> +/ {
>> +	keypad: keypad@180ac000 {
>> +		/* Required SoC specific properties */
>> +		compatible = "brcm,bcm-keypad";
>> +
>> +		/* Required Board specific properties */
>> +		keypad,num-rows = <5>;
>> +		keypad,num-columns = <5>;
>> +		status = "okay";
>> +
>> +		linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_F) /* key_forward */
>> +		MATRIX_KEY(0x00, 0x03, KEY_HOME) /* key_home */
>> +		MATRIX_KEY(0x00, 0x04, KEY_M) /* key_message */
>> +		MATRIX_KEY(0x01, 0x00, KEY_A) /* key_contacts */
>> +		MATRIX_KEY(0x01, 0x01, KEY_1) /* key_1 */
>> +		MATRIX_KEY(0x01, 0x02, KEY_2) /* key_2 */
>> +		MATRIX_KEY(0x01, 0x03, KEY_3) /* key_3 */
>> +		MATRIX_KEY(0x01, 0x04, KEY_S) /* key_speaker */
>> +		MATRIX_KEY(0x02, 0x00, KEY_P) /* key_phone */
>> +		MATRIX_KEY(0x02, 0x01, KEY_4) /* key_4 */
>> +		MATRIX_KEY(0x02, 0x02, KEY_5) /* key_5 */
>> +		MATRIX_KEY(0x02, 0x03, KEY_6) /* key_6 */
>> +		MATRIX_KEY(0x02, 0x04, KEY_VOLUMEUP) /* key_vol_up */
>> +		MATRIX_KEY(0x03, 0x00, KEY_C) /* key_call_log */
>> +		MATRIX_KEY(0x03, 0x01, KEY_7) /* key_7 */
>> +		MATRIX_KEY(0x03, 0x02, KEY_8) /* key_8 */
>> +		MATRIX_KEY(0x03, 0x03, KEY_9) /* key_9 */
>> +		MATRIX_KEY(0x03, 0x04, KEY_VOLUMEDOWN) /* key_vol_down */
>> +		MATRIX_KEY(0x04, 0x00, KEY_H) /* key_headset */
>> +		MATRIX_KEY(0x04, 0x01, KEY_KPASTERISK) /* key_* */
>> +		MATRIX_KEY(0x04, 0x02, KEY_0) /* key_0 */
>> +		MATRIX_KEY(0x04, 0x03, KEY_GRAVE) /* key_# */
>> +		MATRIX_KEY(0x04, 0x04, KEY_MUTE) /* key_mute */
>> +		>;
>> +
>> +		/* Optional board specific properties */
>> +		key-interrupt-trigger-type = <3>;
>> +		col-debounce-filter-period = <5>;
>> +		row-output-enabled;
>> +		pull-up-enabled;
>> +
>> +	};
>> +};
>> --
>> 2.2.2
>>
>
> Thanks.
>

Re: [PATCH 1/2] hwrng: iproc-rng200 - Add Broadcom IPROC RNG driver

[Scott Branden]

I didn't read this properly.  Will add \n in the dev_err messages.

Thanks,
  Scott

On 15-02-14 08:36 AM, Scott Branden wrote:
> Hi Joe,
>
> I really don't see the missing terminating newlines in the patch or
> source code.  The lines look the same as every other line???
>
> Regards,
>   Scott
>
> On 15-02-09 04:27 PM, Joe Perches wrote:
>> On Mon, 2015-02-09 at 16:07 -0800, Scott Branden wrote:
>>> This adds a driver for random number generator present on Broadcom
>>> IPROC devices.
>>
>> trivia:
>>
>>> diff --git a/drivers/char/hw_random/iproc-rng200.c
>>> b/drivers/char/hw_random/iproc-rng200.c
>> []
>>> +static int iproc_rng200_probe(struct platform_device *pdev)
>>> +{
>> []
>>> +    if (!res) {
>>> +        dev_err(dev, "failed to get rng resources");
>>
>> Missing terminating newline:
>>
>>         dev_err(dev, "failed to get rng resources\n");
>>
>>> +    rng_base = devm_ioremap_resource(dev, res);
>>> +    if (!rng_base) {
>>> +        dev_err(dev, "failed to remap rng regs");
>>
>> here too.
>>
>>
>

Re: [PATCH 2/2] Input: bcm-keypad: Add Broadcom keypad controller

[Scott Branden]

Hi Dmitry,

Good review.  Thanks.  Commented inline.

On 15-02-09 05:02 PM, Dmitry Torokhov wrote:
> Hi Scott,
>
> On Mon, Feb 09, 2015 at 04:07:41PM -0800, Scott Branden wrote:
>> Add driver for Broadcom's keypad controller.
>>
>> Broadcom Keypad controller is used to interface a SoC with a matrix-type
>> keypad device. The keypad controller supports multiple row and column lines.
>> A key can be placed at each intersection of a unique row and a unique column.
>> The keypad controller can sense a key-press and key-release and report the
>> event using a interrupt to the cpu.
>>
>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>> ---
>>   drivers/input/keyboard/Kconfig      |  10 +
>>   drivers/input/keyboard/Makefile     |   1 +
>>   drivers/input/keyboard/bcm-keypad.c | 489 ++++++++++++++++++++++++++++++++++++
>>   3 files changed, 500 insertions(+)
>>   create mode 100644 drivers/input/keyboard/bcm-keypad.c
>>
>> diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
>> index a5d9b3f..3a0c0f2 100644
>> --- a/drivers/input/keyboard/Kconfig
>> +++ b/drivers/input/keyboard/Kconfig
>> @@ -676,4 +676,14 @@ config KEYBOARD_CAP11XX
>>   	  To compile this driver as a module, choose M here: the
>>   	  module will be called cap11xx.
>>
>> +config KEYBOARD_BCM
>> +	tristate "Broadcom keypad driver"
>> +	select INPUT_MATRIXKMAP
>> +	default ARCH_BCM_CYGNUS
>> +	help
>> +	  Say Y here if you want to use Broadcom keypad.
>> +
>> +	  To compile this driver as a module, choose M here: the
>> +	  module will be called bcm-keypad.
>> +
>>   endif
>> diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
>> index febafa5..3cff8f6 100644
>> --- a/drivers/input/keyboard/Makefile
>> +++ b/drivers/input/keyboard/Makefile
>> @@ -10,6 +10,7 @@ obj-$(CONFIG_KEYBOARD_ADP5589)		+= adp5589-keys.o
>>   obj-$(CONFIG_KEYBOARD_AMIGA)		+= amikbd.o
>>   obj-$(CONFIG_KEYBOARD_ATARI)		+= atakbd.o
>>   obj-$(CONFIG_KEYBOARD_ATKBD)		+= atkbd.o
>> +obj-$(CONFIG_KEYBOARD_BCM)		+= bcm-keypad.o
>>   obj-$(CONFIG_KEYBOARD_BFIN)		+= bf54x-keys.o
>>   obj-$(CONFIG_KEYBOARD_CAP11XX)		+= cap11xx.o
>>   obj-$(CONFIG_KEYBOARD_CLPS711X)		+= clps711x-keypad.o
>> diff --git a/drivers/input/keyboard/bcm-keypad.c b/drivers/input/keyboard/bcm-keypad.c
>> new file mode 100644
>> index 0000000..b2c4bb7
>> --- /dev/null
>> +++ b/drivers/input/keyboard/bcm-keypad.c
>> @@ -0,0 +1,489 @@
>> +/*
>> + * Copyright (C) 2014 Broadcom Corporation
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation version 2.
>> + *
>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> + * kind, whether express or implied; without even the implied warranty
>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/mm.h>
>> +#include <linux/module.h>
>> +#include <linux/input.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/bitops.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/delay.h>
>> +#include <linux/sizes.h>
>> +#include <linux/stddef.h>
>> +#include <linux/of.h>
>> +#include <linux/of_irq.h>
>> +#include <linux/slab.h>
>> +#include <linux/clk.h>
>> +#include <linux/types.h>
>> +#include <linux/string.h>
>> +#include <asm/memory.h>
>> +#include <linux/io.h>
>> +#include <linux/input/matrix_keypad.h>
>> +
>> +#define DEFAULT_CLK_HZ                  31250
>> +/* Repeat period (ms) */
>> +#define KEY_REPEAT_PERIOD               100
>> +/* First time press dly (ms) */
>> +#define KEY_REPEAT_DELAY                400
>> +#define MAX_ROWS                        8
>> +#define MAX_COLS                        8
>> +
>> +/* Register/field definitions */
>> +#define KPCR_OFFSET                          0x00000080
>> +#define KPCR_MODE                       0x00000002
>> +#define KPCR_MODE_SHIFT                 1
>> +#define KPCR_MODE_MASK                  1
>> +#define KPCR_ENABLE                     0x00000001
>> +#define KPCR_STATUSFILTERENABLE         0x00008000
>> +#define KPCR_STATUSFILTERTYPE_SHIFT          12
>> +#define KPCR_COLFILTERENABLE            0x00000800
>> +#define KPCR_COLFILTERTYPE_SHIFT             8
>> +#define KPCR_ROWWIDTH_SHIFT                  20
>> +#define KPCR_COLUMNWIDTH_SHIFT               16
>> +
>> +#define KPIOR_OFFSET                         0x00000084
>> +#define KPIOR_ROWOCONTRL_SHIFT               24
>> +#define KPIOR_ROWOCONTRL_MASK                0xFF000000
>> +#define KPIOR_COLUMNOCONTRL_SHIFT            16
>> +#define KPIOR_COLUMNOCONTRL_MASK             0x00FF0000
>> +#define KPIOR_COLUMN_IO_DATA_SHIFT           0
>> +
>> +#define KPEMR0_OFFSET                        0x00000090
>> +#define KPEMR1_OFFSET                        0x00000094
>> +#define KPEMR2_OFFSET                        0x00000098
>> +#define KPEMR3_OFFSET                        0x0000009C
>> +#define KPEMR_EDGETYPE_MAX 3
>> +
>> +#define KPSSR0_OFFSET                        0x000000A0
>> +#define KPSSR1_OFFSET                        0x000000A4
>> +#define KPIMR0_OFFSET                        0x000000B0
>> +#define KPIMR1_OFFSET                        0x000000B4
>> +#define KPICR0_OFFSET                        0x000000B8
>> +#define KPICR1_OFFSET                        0x000000BC
>> +#define KPISR0_OFFSET                        0x000000C0
>> +#define KPISR1_OFFSET                        0x000000C4
>> +
>> +#define KPCR_STATUSFILTERTYPE_MAX 7
>> +#define KPCR_COLFILTERTYPE_MAX 7
>> +
>> +/* Macros to determine the row/column from a bit that is set in SSR0/1. */
>> +#define BIT_TO_ROW_SSR0(bit_nr)  (bit_nr >> 3)
>> +#define BIT_TO_ROW_SSR1(bit_nr)  ((bit_nr >> 3) + 4)
>> +#define BIT_TO_COL(bit_nr)       (bit_nr % 8)
>> +
>> +/* Structure representing various run-time entities */
>> +struct bcm_kp {
>> +	void __iomem *base;
>> +	int irq;
>> +	struct clk *clk;
>> +	struct input_dev *input_dev;
>> +	unsigned long last_state[2];
>> +	unsigned int n_rows;
>> +	unsigned int n_cols;
>> +	u32 kpcr;
>> +	u32 kpior;
>> +	u32 kpemr;
>> +	u32 imr0_val;
>> +	u32 imr1_val;
>> +};
>> +
>> +/*
>> + * Returns the keycode from the input device keymap given the row and
>> + * column.
>> + */
>> +static inline int bcm_kp_get_keycode(struct bcm_kp *kp, int row, int col)
>> +{
>> +	unsigned int row_shift = get_count_order(kp->n_cols);
>> +	unsigned short *keymap = kp->input_dev->keycode;
>> +
>> +	return keymap[MATRIX_SCAN_CODE(row, col, row_shift)];
>> +}
>> +
>> +static irqreturn_t bcm_kp_isr_thread(int irq, void *dev_id)
>> +{
>> +	struct bcm_kp *kp = dev_id;
>> +	unsigned long state, change;
>> +	int bit_nr;
>> +	int pull_mode = (kp->kpcr >> KPCR_MODE_SHIFT) & KPCR_MODE_MASK;
>> +	int key_press;
>> +	int row, col;
>> +	unsigned int keycode;
>> +
>> +	/* Clear interrupts */
>> +	writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET);
>> +	writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET);
>> +
>> +	state = readl(kp->base + KPSSR0_OFFSET);
>> +	change = kp->last_state[0] ^ state;
>> +	kp->last_state[0] = state;
>> +
>> +	for_each_set_bit(bit_nr, &change, BITS_PER_LONG) {
>> +		key_press = state & BIT(bit_nr);
>> +		/* The meaning of SSR register depends on pull mode. */
>> +		key_press = pull_mode ? !key_press : key_press;
>> +		row = BIT_TO_ROW_SSR0(bit_nr);
>> +		col = BIT_TO_COL(bit_nr);
>> +		keycode = bcm_kp_get_keycode(kp, row, col);
>> +		input_report_key(kp->input_dev, keycode, key_press);
>> +	}
>> +
>> +	state = readl(kp->base + KPSSR1_OFFSET);
>> +	change = kp->last_state[1] ^ state;
>> +	kp->last_state[1] = state;
>> +
>> +	for_each_set_bit(bit_nr, &change, BITS_PER_LONG) {
>> +		key_press = state & BIT(bit_nr);
>> +		/* The meaning of SSR register depends on pull mode. */
>> +		key_press = pull_mode ? !key_press : key_press;
>> +		row = BIT_TO_ROW_SSR1(bit_nr);
>> +		col = BIT_TO_COL(bit_nr);
>> +		keycode = bcm_kp_get_keycode(kp, row, col);
>> +		input_report_key(kp->input_dev, keycode, key_press);
>> +	}
>
> Please split it into a separate function that processes one bank and
> call it twice instead of doing cut-and-paste of almost the same code. Or
> even better combine it all into one block (i.e have changes[2], use
> bitmap_xor to figure difference, etc...).
>
OK.  It was a few lines of code called twice but I'll change it.

>> +
>> +	input_sync(kp->input_dev);
>> +
>> +	return IRQ_HANDLED;
>> +}
>> +
>> +static int bcm_kp_start(struct bcm_kp *kp)
>> +{
>> +	int error;
>> +
>> +	error = clk_prepare_enable(kp->clk);
>> +	if (error)
>> +		return error;
>> +
>> +	writel(kp->kpior, kp->base + KPIOR_OFFSET);
>> +
>> +	writel(kp->imr0_val, kp->base + KPIMR0_OFFSET);
>> +	writel(kp->imr1_val, kp->base + KPIMR1_OFFSET);
>> +
>> +	writel(kp->kpemr, kp->base + KPEMR0_OFFSET);
>> +	writel(kp->kpemr, kp->base + KPEMR1_OFFSET);
>> +	writel(kp->kpemr, kp->base + KPEMR2_OFFSET);
>> +	writel(kp->kpemr, kp->base + KPEMR3_OFFSET);
>> +
>> +	writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET);
>> +	writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET);
>> +
>> +	kp->last_state[0] = readl(kp->base + KPSSR0_OFFSET);
>> +	kp->last_state[0] = readl(kp->base + KPSSR1_OFFSET);
>> +
>> +	writel(kp->kpcr | KPCR_ENABLE, kp->base + KPCR_OFFSET);
>> +
>> +	return 0;
>> +}
>> +
>> +static void bcm_kp_stop(const struct bcm_kp *kp)
>> +{
>> +	u32 val;
>> +
>> +	val = readl(kp->base + KPCR_OFFSET);
>> +	val &= ~KPCR_ENABLE;
>> +	writel(0, kp->base + KPCR_OFFSET);
>> +	writel(0, kp->base + KPIMR0_OFFSET);
>> +	writel(0, kp->base + KPIMR1_OFFSET);
>> +	writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET);
>> +	writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET);
>> +
>> +	clk_disable_unprepare(kp->clk);
>> +}
>> +
>> +static int bcm_kp_open(struct input_dev *dev)
>> +{
>> +	struct bcm_kp *kp = input_get_drvdata(dev);
>> +
>> +	return bcm_kp_start(kp);
>> +}
>> +
>> +static void bcm_kp_close(struct input_dev *dev)
>> +{
>> +	struct bcm_kp *kp = input_get_drvdata(dev);
>> +
>> +	bcm_kp_stop(kp);
>> +}
>> +
>> +static int bcm_kp_matrix_key_parse_dt(struct bcm_kp *kp)
>> +{
>> +	struct device *dev = kp->input_dev->dev.parent;
>> +	struct device_node *np = dev->of_node;
>> +	int error;
>> +	unsigned int dt_val;
>> +	unsigned int i;
>> +
>> +	/* Initialize the KPCR Keypad Configuration Register */
>> +	kp->kpcr = KPCR_STATUSFILTERENABLE | KPCR_COLFILTERENABLE;
>> +
>> +	error = matrix_keypad_parse_of_params(dev, &kp->n_rows, &kp->n_cols);
>> +	if (error) {
>> +		dev_err(dev, "failed to parse kp params\n");
>> +		return error;
>> +	}
>> +	/* Set row width for the ASIC block. */
>> +	kp->kpcr |= (kp->n_rows - 1) << KPCR_ROWWIDTH_SHIFT;
>> +
>> +	/* Set column width for the ASIC block. */
>> +	kp->kpcr |= (kp->n_cols - 1) << KPCR_COLUMNWIDTH_SHIFT;
>> +
>> +	/* Configure the IMR registers */
>> +	{
>> +		unsigned int num_rows, col_mask, rows_set;
>> +
>> +		/* IMR registers contain interrupt enable bits for 8x8 matrix
>> +		 * IMR0 register format: <row3> <row2> <row1> <row0>
>> +		 * IMR1 register format: <row7> <row6> <row5> <row4>
>> +		 */
>> +
>> +		col_mask = (1 << (kp->n_cols)) - 1;
>> +		num_rows = kp->n_rows;
>> +
>> +		/* Set column bits in rows 0 to 3 in IMR0 */
>> +		kp->imr0_val = col_mask;
>> +
>> +		rows_set = 1;
>> +		while ((--num_rows) && (rows_set++ < 4))
>> +			kp->imr0_val |= (kp->imr0_val << MAX_COLS);
>> +
>> +		/* Set column bits in rows 4 to 7 in IMR1 */
>> +		kp->imr1_val = 0;
>> +		if (num_rows) {
>> +			kp->imr1_val = col_mask;
>> +			while (--num_rows)
>> +				kp->imr1_val |= (kp->imr1_val << MAX_COLS);
>> +		}
>> +	}
>> +
>> +	/*
>> +	 * Obtain the interrupt trigger type specified and verify against the
>> +	 * possible values specified in the DT binding.
>> +	 */
>> +	of_property_read_u32(np, "key-interrupt-trigger-type",
>> +		&dt_val);
>> +	if ((dt_val == 0) || (dt_val > KPEMR_EDGETYPE_MAX)) {
>> +		dev_err(dev, "Invalid interrupt trigger type %d\n", dt_val);
>> +		return -EINVAL;
>> +	}
>> +	/* Initialize the KPEMR Keypress Edge Mode Registers */
>> +	kp->kpemr = 0;
>> +	for (i = 0; i <= 30; i = i + 2)
>> +		kp->kpemr |= (dt_val << i);
>> +
>> +	/*
>> +	 * Obtain the Status filter debounce value and verify against the
>> +	 * possible values specified in the DT binding.
>> +	 */
>> +	of_property_read_u32(np, "status-debounce-filter-period",
>> +		&dt_val);
>> +	if (dt_val > KPCR_STATUSFILTERTYPE_MAX) {
>> +		dev_err(dev, "Invalid Status filter debounce value %d\n",
>> +			dt_val);
>> +		return -EINVAL;
>> +	}
>> +	kp->kpcr |= dt_val << KPCR_STATUSFILTERTYPE_SHIFT;
>> +
>> +
>> +	/*
>> +	 * Obtain the Column filter debounce value and verify against the
>> +	 * possible values specified in the DT binding.
>> +	 */
>> +	of_property_read_u32(np, "col-debounce-filter-period",
>> +		&dt_val);
>> +
>> +	if (dt_val > KPCR_COLFILTERTYPE_MAX) {
>> +		dev_err(dev, "Invalid Column filter debounce value %d\n",
>> +			dt_val);
>> +		return -EINVAL;
>> +	}
>> +	kp->kpcr |= dt_val << KPCR_COLFILTERTYPE_SHIFT;
>> +
>> +	/*
>> +	 * Determine between the row and column,
>> +	 * which should be configured as output.
>> +	 */
>> +	if (of_property_read_bool(np, "row-output-enabled")) {
>> +		/*
>> +		* Set RowOContrl or ColumnOContrl in KPIOR
>> +		* to the number of pins to drive as outputs
>> +		*/
>> +		kp->kpior = (((1 << kp->n_rows) - 1) <<
>> +				KPIOR_ROWOCONTRL_SHIFT);
>> +	} else {
>> +		kp->kpior = (((1 << kp->n_cols) - 1) <<
>> +				KPIOR_COLUMNOCONTRL_SHIFT);
>> +	}
>> +
>> +	/*
>> +	 * Determine if the scan pull up needs to be enabled
>> +	 */
>> +	if (of_property_read_bool(np, "pull-up-enabled"))
>> +		kp->kpcr |= KPCR_MODE;
>> +
>> +	dev_dbg(dev, "n_rows=%d n_col=%d kpcr=%x kpior=%x kpemr=%x\n",
>> +		kp->n_rows, kp->n_cols,
>> +		kp->kpcr, kp->kpior, kp->kpemr);
>> +
>> +	return 0;
>> +}
>> +
>> +
>> +static int bcm_kp_probe(struct platform_device *pdev)
>> +{
>> +	struct bcm_kp *kp;
>> +	struct input_dev *input_dev;
>> +	struct resource *res;
>> +	int error;
>> +
>> +	kp = devm_kzalloc(&pdev->dev, sizeof(*kp),
>> +				   GFP_KERNEL);
>> +	if (!kp)
>> +		return -ENOMEM;
>> +
>> +	input_dev = devm_input_allocate_device(&pdev->dev);
>> +	if (!input_dev) {
>> +		dev_err(&pdev->dev, "failed to allocate the input device\n");
>> +		return -ENOMEM;
>> +	}
>> +	__set_bit(EV_KEY, input_dev->evbit);
>> +	__set_bit(EV_REP, input_dev->evbit);
>> +	input_dev->rep[REP_PERIOD] = KEY_REPEAT_PERIOD;
>> +	input_dev->rep[REP_DELAY] = KEY_REPEAT_DELAY;
>
> That does not do what you think: if you set up custom delay and period
> you are supposed to supply your own timer as well. Either adjust values
> after registering input device, or leave defaults.
>
> Also it might be a good idea to have "linux,autorepeat" DT property to
> control it.
>
I'll look into this in more detail to understand.

>> +	input_dev->name = pdev->name;
>> +	input_dev->phys = "keypad/input0";
>> +	input_dev->dev.parent = &pdev->dev;
>> +	input_dev->open = bcm_kp_open;
>> +	input_dev->close = bcm_kp_close;
>> +
>> +	input_dev->id.bustype = BUS_HOST;
>> +	input_dev->id.vendor = 0x0001;
>> +	input_dev->id.product = 0x0001;
>> +	input_dev->id.version = 0x0100;
>> +
>> +	input_set_drvdata(input_dev, kp);
>> +
>> +	kp->input_dev = input_dev;
>> +
>> +	platform_set_drvdata(pdev, kp);
>> +
>> +	error = bcm_kp_matrix_key_parse_dt(kp);
>> +	if (error)
>> +		return error;
>> +
>> +	error = matrix_keypad_build_keymap(NULL, NULL,
>> +					   kp->n_rows,
>> +					   kp->n_cols,
>> +					   NULL, input_dev);
>> +	if (error) {
>> +		dev_err(&pdev->dev, "failed to build keymap\n");
>> +		return error;
>> +	}
>> +
>> +	/* Get the KEYPAD base address */
>> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +	if (!res) {
>> +		dev_err(&pdev->dev, "Missing keypad base address resource\n");
>> +		return -ENODEV;
>> +	}
>> +
>> +	kp->base = devm_ioremap_resource(&pdev->dev, res);
>> +	if (IS_ERR(kp->base))
>> +		return PTR_ERR(kp->base);
>> +
>> +	/* Enable clock */
>> +
>> +	kp->clk = devm_clk_get(&pdev->dev, "peri_clk");
>> +	if (IS_ERR(kp->clk))
>> +		dev_info(&pdev->dev,
>> +			"No clock specified. Assuming it's enabled\n");
>> +	else {
>> +		unsigned int desired_rate;
>> +		long actual_rate;
>> +
>> +		error = of_property_read_u32(pdev->dev.of_node,
>> +				"clock-frequency", &desired_rate);
>> +		if (error < 0)
>> +			desired_rate = DEFAULT_CLK_HZ;
>> +
>> +		actual_rate = clk_round_rate(kp->clk, desired_rate);
>> +		if (actual_rate <= 0)
>> +			return -EINVAL;
>> +
>> +		error = clk_set_rate(kp->clk, actual_rate);
>> +		if (error)
>> +			return -EINVAL;
>> +
>> +		error = clk_prepare_enable(kp->clk);
>> +		if (error)
>> +			return -EINVAL;
>> +	}
>> +
>> +	/* Put the kp into a known sane state */
>> +	bcm_kp_stop(kp);
>> +
>> +	kp->irq = platform_get_irq(pdev, 0);
>> +	if (kp->irq < 0) {
>> +		dev_err(&pdev->dev, "no IRQ specified\n");
>> +		return -EINVAL;
>> +	}
>> +
>> +	error = devm_request_threaded_irq(&pdev->dev, kp->irq, NULL,
>> +		bcm_kp_isr_thread,
>> +		IRQF_ONESHOT, pdev->name, kp);
>> +	if (error) {
>> +		dev_err(&pdev->dev, "failed to request IRQ\n");
>> +		return error;
>> +	}
>> +
>> +	error = input_register_device(input_dev);
>> +	if (error) {
>> +		dev_err(&pdev->dev, "failed to register input device\n");
>> +		return error;
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +/* Called to perform module cleanup when the module is unloaded. */
>> +static int bcm_kp_remove(struct platform_device *pdev)
>> +{
>> +	struct bcm_kp *kp = platform_get_drvdata(pdev);
>> +
>> +	pr_info("bcm_kp_remove\n");
>> +
>> +	/* Unregister everything */
>> +	input_unregister_device(kp->input_dev);
>> +	clk_disable_unprepare(kp->clk);
>
> You already calling clk_disable_unprepare() as part of bcm_kp_close()
> (in stop()), so you do not need it here. input_unregister_device() will
> also be called automatically since you are using managed input device,
> so please remove bcm_kp_remove altogether.
>
OK, will remove.  That's an easy thing to do.

>> +
>> +	return 0;
>> +}
>> +
>> +static const struct of_device_id bcm_kp_of_match[] = {
>> +	{ .compatible = "brcm,bcm-keypad" },
>> +	{ },
>> +};
>> +MODULE_DEVICE_TABLE(of, bcm_kp_of_match);
>> +
>> +static struct platform_driver bcm_kp_device_driver = {
>> +	.probe		= bcm_kp_probe,
>> +	.remove = bcm_kp_remove,
>> +	.driver		= {
>> +		.name	= "bcm-keypad",
>> +		.of_match_table = of_match_ptr(bcm_kp_of_match),
>> +	}
>> +};
>> +
>> +module_platform_driver(bcm_kp_device_driver);
>> +
>> +MODULE_AUTHOR("Broadcom Corporation");
>> +MODULE_DESCRIPTION("BCM Keypad Driver");
>> +MODULE_LICENSE("GPL");
>> --
>> 2.2.2
>>
>
> Thanks.
>

Re: [PATCH 1/2] Input: bcm-keypad: add device tree bindings

[Dmitry Torokhov]

Hi Scott,

On Sat, Feb 14, 2015 at 08:49:15AM -0800, Scott Branden wrote:
> Hi Dmitry,
> 
> Comments inline.  I still have an issue with vendor prefix as there
> are not documented guidelines I can find in this area?

I looked and I could not locate it written down either. I think Grant is
in Santa Rosa this week, I'll ask him to clarify.

> 
> 
> On 15-02-09 04:51 PM, Dmitry Torokhov wrote:
> >Hi Scott,
> >
> >On Mon, Feb 09, 2015 at 04:07:40PM -0800, Scott Branden wrote:
> >>Documents the Broadcom keypad controller device tree bindings.
> >>
> >>Reviewed-by: Ray Jui <rjui@broadcom.com>
> >>Signed-off-by: Scott Branden <sbranden@broadcom.com>
> >>---
> >>  .../devicetree/bindings/input/brcm,bcm-keypad.txt  | 118 +++++++++++++++++++++
> >>  1 file changed, 118 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
> >>
> >>diff --git a/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt b/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
> >>new file mode 100644
> >>index 0000000..645829d
> >>--- /dev/null
> >>+++ b/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
> >>@@ -0,0 +1,118 @@
> >>+* Broadcom Keypad Controller device tree bindings
> >>+
> >>+Broadcom Keypad controller is used to interface a SoC with a matrix-type
> >>+keypad device. The keypad controller supports multiple row and column lines.
> >>+A key can be placed at each intersection of a unique row and a unique column.
> >>+The keypad controller can sense a key-press and key-release and report the
> >>+event using a interrupt to the cpu.
> >>+
> >>+This binding is based on the matrix-keymap binding with the following
> >>+changes:
> >>+
> >>+keypad,num-rows and keypad,num-columns are required.
> >>+
> >>+Required SoC Specific Properties:
> >>+- compatible: should be "brcm,bcm-keypad"
> >>+
> >>+- reg: physical base address of the controller and length of memory mapped
> >>+  region.
> >>+
> >>+- interrupts: The interrupt number to the cpu.
> >>+
> >>+Board Specific Properties:
> >>+- keypad,num-rows: Number of row lines connected to the keypad
> >>+  controller.
> >>+
> >>+- keypad,num-columns: Number of column lines connected to the
> >>+  keypad controller.
> >>+
> >>+- key-interrupt-trigger-type: The type of interrupt trigger asociated with the Keypad matrix.
> >>+
> >>+	KEYPAD_INTERRUPT_NO_TRIGGER	=	0
> >>+	KEYPAD_INTERRUPT_RISING_EDGE	=	1
> >>+	KEYPAD_INTERRUPT_FALLING_EDGE	=	2
> >>+	KEYPAD_INTERRUPT_BOTH_EDGES	=	3
> >
> >Can we get this data from the interrupt spec?
> I don't understand your question. Could you elaborate?
> But, looking at this closer this determines when the hardware should
> generate interrupts.  I think we would always need to set it to both
> edges and this binding option can probably we removed?

What I meant that interrupt binding allows specifying the trigger and
you have separate binding for trigger here. It would be nice to have
just one (the standard interrupt binding).

> >
> >>+
> >>+- col-debounce-filter-period: The debounce period for the Column filter.
> >>+
> >>+	KEYPAD_DEBOUNCE_1_ms	=	0
> >>+	KEYPAD_DEBOUNCE_2_ms	=	1
> >>+	KEYPAD_DEBOUNCE_4_ms	=	2
> >>+	KEYPAD_DEBOUNCE_8_ms	=	3
> >
> >>+	KEYPAD_DEBOUNCE_16_ms	=	4
> >>+	KEYPAD_DEBOUNCE_32_ms	=	5
> >>+	KEYPAD_DEBOUNCE_64_ms	=	6
> >>+	KEYPAD_DEBOUNCE_128_ms	=	7
> >>+
> >>+- status-debounce-filter-period: The debounce period for the Status filter.
> >>+
> >>+	KEYPAD_DEBOUNCE_1_ms	=	0
> >>+	KEYPAD_DEBOUNCE_2_ms	=	1
> >>+	KEYPAD_DEBOUNCE_4_ms	=	2
> >>+	KEYPAD_DEBOUNCE_8_ms	=	3
> >>+	KEYPAD_DEBOUNCE_16_ms	=	4
> >>+	KEYPAD_DEBOUNCE_32_ms	=	5
> >>+	KEYPAD_DEBOUNCE_64_ms	=	6
> >>+	KEYPAD_DEBOUNCE_128_ms	=	7
> >
> >I could swear device-specific properties should be in form of
> ><vendor-prefix>,<property-name> to ensure it won't clash with changes on
> >subsystem level later on. Device-tree folks, what say you?
> I see examples with and without vendor-prefix.
> qcom,pm8xxx-keypad.txt does not have prefixes
> st-keyscan.txt does have a prefix
> 
> I can't find any documented guidelines for this.

As I mentioned I'll try to get clarification on this.

> Clash changes should not happen because as new standard properties
> are added the drivers should be adjusted to use the new dt-bindings?

This is a misconception: device tree bindings are supposed to form ABI
(and the goal to eventually separate them from the kernel) and so we
need to support old bindings in new kernels.

Thanks.

-- 
Dmitry

Re: [PATCH 1/2] Input: bcm-keypad: add device tree bindings

[Dmitry Torokhov]

Hi Scott,

On Sun, Feb 15, 2015 at 09:17:51PM -0800, Dmitry Torokhov wrote:
> On Sat, Feb 14, 2015 at 08:49:15AM -0800, Scott Branden wrote:
> > On 15-02-09 04:51 PM, Dmitry Torokhov wrote:
> > >On Mon, Feb 09, 2015 at 04:07:40PM -0800, Scott Branden wrote:
> > >>+
> > >>+- col-debounce-filter-period: The debounce period for the Column filter.
> > >>+
> > >>+	KEYPAD_DEBOUNCE_1_ms	=	0
> > >>+	KEYPAD_DEBOUNCE_2_ms	=	1
> > >>+	KEYPAD_DEBOUNCE_4_ms	=	2
> > >>+	KEYPAD_DEBOUNCE_8_ms	=	3
> > >
> > >>+	KEYPAD_DEBOUNCE_16_ms	=	4
> > >>+	KEYPAD_DEBOUNCE_32_ms	=	5
> > >>+	KEYPAD_DEBOUNCE_64_ms	=	6
> > >>+	KEYPAD_DEBOUNCE_128_ms	=	7
> > >>+
> > >>+- status-debounce-filter-period: The debounce period for the Status filter.
> > >>+
> > >>+	KEYPAD_DEBOUNCE_1_ms	=	0
> > >>+	KEYPAD_DEBOUNCE_2_ms	=	1
> > >>+	KEYPAD_DEBOUNCE_4_ms	=	2
> > >>+	KEYPAD_DEBOUNCE_8_ms	=	3
> > >>+	KEYPAD_DEBOUNCE_16_ms	=	4
> > >>+	KEYPAD_DEBOUNCE_32_ms	=	5
> > >>+	KEYPAD_DEBOUNCE_64_ms	=	6
> > >>+	KEYPAD_DEBOUNCE_128_ms	=	7
> > >
> > >I could swear device-specific properties should be in form of
> > ><vendor-prefix>,<property-name> to ensure it won't clash with changes on
> > >subsystem level later on. Device-tree folks, what say you?
> > I see examples with and without vendor-prefix.
> > qcom,pm8xxx-keypad.txt does not have prefixes
> > st-keyscan.txt does have a prefix
> > 
> > I can't find any documented guidelines for this.
> 
> As I mentioned I'll try to get clarification on this.

I have chatted with a couple of people on this and it is acceptable to
omit vendor prefix in bindings when we are using a specific driver like
we have here (i.e. when driver's compatible string already includes
vendor prefix). Vendor prefixes on properties are required when we
augment a generic driver's binding.

So the above 2 entries are fine as is.

Thanks.

-- 
Dmitry

[PATCH v2 0/2] Add support for Broadcom RNG200

[Scott Branden]

This series of patchsets contains the Broadcom Random Number Generator
driver and device tree binding documentation.

Changes from v1:
 added \n to 2 dev_err messages

Scott Branden (2):
  hwrng: iproc-rng200 - Add device tree bindings
  hwrng: iproc-rng200 - Add Broadcom IPROC RNG driver

 .../bindings/hwrng/brcm,iproc-rng200.txt           |  12 ++
 drivers/char/hw_random/Kconfig                     |  13 ++
 drivers/char/hw_random/Makefile                    |   1 +
 drivers/char/hw_random/iproc-rng200.c              | 239 +++++++++++++++++++++
 4 files changed, 265 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwrng/brcm,iproc-rng200.txt
 create mode 100644 drivers/char/hw_random/iproc-rng200.c

-- 
2.3.0

[PATCH v2 1/2] hwrng: iproc-rng200 - Add device tree bindings

[Scott Branden]

Documents the IPROC random number generator device tree bindings
used in some Broadcom chipsets.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 .../devicetree/bindings/hwrng/brcm,iproc-rng200.txt          | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwrng/brcm,iproc-rng200.txt

diff --git a/Documentation/devicetree/bindings/hwrng/brcm,iproc-rng200.txt b/Documentation/devicetree/bindings/hwrng/brcm,iproc-rng200.txt
new file mode 100644
index 0000000..e25a456
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwrng/brcm,iproc-rng200.txt
@@ -0,0 +1,12 @@
+HWRNG support for the iproc-rng200 driver
+
+Required properties:
+- compatible : "brcm,iproc-rng200"
+- reg : base address and size of control register block
+
+Example:
+
+rng {
+        compatible = "brcm,iproc-rng200";
+        reg = <0x18032000 0x28>;
+};
-- 
2.3.0

[PATCH v2 2/2] hwrng: iproc-rng200 - Add Broadcom IPROC RNG driver

[Scott Branden]

This adds a driver for random number generator present on Broadcom
IPROC devices.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/char/hw_random/Kconfig        |  13 ++
 drivers/char/hw_random/Makefile       |   1 +
 drivers/char/hw_random/iproc-rng200.c | 239 ++++++++++++++++++++++++++++++++++
 3 files changed, 253 insertions(+)
 create mode 100644 drivers/char/hw_random/iproc-rng200.c

diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index de57b38..f48cf11 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -101,6 +101,19 @@ config HW_RANDOM_BCM2835
 
 	  If unsure, say Y.
 
+config HW_RANDOM_IPROC_RNG200
+	tristate "Broadcom iProc RNG200 support"
+	depends on ARCH_BCM_IPROC
+	default HW_RANDOM
+	---help---
+	  This driver provides kernel-side support for the RNG200
+	  hardware found on the Broadcom iProc SoCs.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called iproc-rng200
+
+	  If unsure, say Y.
+
 config HW_RANDOM_GEODE
 	tristate "AMD Geode HW Random Number Generator support"
 	depends on X86_32 && PCI
diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
index 0b4cd57..055bb01 100644
--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
@@ -28,5 +28,6 @@ obj-$(CONFIG_HW_RANDOM_POWERNV) += powernv-rng.o
 obj-$(CONFIG_HW_RANDOM_EXYNOS)	+= exynos-rng.o
 obj-$(CONFIG_HW_RANDOM_TPM) += tpm-rng.o
 obj-$(CONFIG_HW_RANDOM_BCM2835) += bcm2835-rng.o
+obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) += iproc-rng200.o
 obj-$(CONFIG_HW_RANDOM_MSM) += msm-rng.o
 obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o
diff --git a/drivers/char/hw_random/iproc-rng200.c b/drivers/char/hw_random/iproc-rng200.c
new file mode 100644
index 0000000..4643aa9
--- /dev/null
+++ b/drivers/char/hw_random/iproc-rng200.c
@@ -0,0 +1,239 @@
+/*
+* Copyright (C) 2014 Broadcom Corporation
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation version 2.
+*
+* This program is distributed "as is" WITHOUT ANY WARRANTY of any
+* kind, whether express or implied; without even the implied warranty
+* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*/
+/*
+ * DESCRIPTION: The Broadcom iProc RNG200 Driver
+ */
+
+#include <linux/hw_random.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+
+
+/* Registers */
+#define RNG_CTRL_OFFSET					0x00
+#define RNG_CTRL_RNG_RBGEN_MASK				0x00001FFF
+#define RNG_CTRL_RNG_RBGEN_ENABLE			0x00000001
+#define RNG_CTRL_RNG_RBGEN_DISABLE			0x00000000
+
+#define RNG_SOFT_RESET_OFFSET				0x04
+#define RNG_SOFT_RESET_RNG_SOFT_RESET_MASK		0x00000001
+#define RNG_SOFT_RESET_RNG_SOFT_RESET_ACTIVE		0x00000001
+#define RNG_SOFT_RESET_RNG_SOFT_RESET_CLEAR		0x00000000
+
+#define RBG_SOFT_RESET_OFFSET				0x08
+#define RBG_SOFT_RESET_RNG_SOFT_RESET_MASK		0x00000001
+#define RBG_SOFT_RESET_RNG_SOFT_RESET_ACTIVE		0x00000001
+#define RBG_SOFT_RESET_RNG_SOFT_RESET_CLEAR		0x00000000
+
+#define RNG_INT_STATUS_OFFSET				0x18
+#define RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK	0x80000000
+#define RNG_INT_STATUS_STARTUP_TRANSITIONS_MET_IRQ_MASK	0x00020000
+#define RNG_INT_STATUS_NIST_FAIL_IRQ_MASK		0x00000020
+#define RNG_INT_STATUS_TOTAL_BITS_COUNT_IRQ_MASK	0x00000001
+
+#define RNG_FIFO_DATA_OFFSET				0x20
+
+#define RNG_FIFO_COUNT_OFFSET				0x24
+#define RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK		0x000000FF
+
+static void iproc_rng200_restart(void __iomem *rng_base)
+{
+	uint32_t val;
+
+	/* Disable RBG */
+	val = ioread32(rng_base + RNG_CTRL_OFFSET);
+	val &= ~RNG_CTRL_RNG_RBGEN_MASK;
+	val |= RNG_CTRL_RNG_RBGEN_DISABLE;
+	iowrite32(val, rng_base + RNG_CTRL_OFFSET);
+
+	/* Clear all interrupt status */
+	iowrite32(0xFFFFFFFFUL, rng_base + RNG_INT_STATUS_OFFSET);
+
+	/* Reset RNG and RBG */
+	val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
+	val &= ~RBG_SOFT_RESET_RNG_SOFT_RESET_MASK;
+	val |= RBG_SOFT_RESET_RNG_SOFT_RESET_ACTIVE;
+	iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
+
+	val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
+	val &= ~RNG_SOFT_RESET_RNG_SOFT_RESET_MASK;
+	val |= RNG_SOFT_RESET_RNG_SOFT_RESET_ACTIVE;
+	iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
+
+	val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
+	val &= ~RNG_SOFT_RESET_RNG_SOFT_RESET_MASK;
+	val |= RNG_SOFT_RESET_RNG_SOFT_RESET_CLEAR;
+	iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
+
+	val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
+	val &= ~RBG_SOFT_RESET_RNG_SOFT_RESET_MASK;
+	val |= RBG_SOFT_RESET_RNG_SOFT_RESET_CLEAR;
+	iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
+
+	/* Enable RBG */
+	val = ioread32(rng_base + RNG_CTRL_OFFSET);
+	val &= ~RNG_CTRL_RNG_RBGEN_MASK;
+	val |= RNG_CTRL_RNG_RBGEN_ENABLE;
+	iowrite32(val, rng_base + RNG_CTRL_OFFSET);
+}
+
+static int iproc_rng200_read(struct hwrng *rng, void *buf, size_t max,
+			       bool wait)
+{
+	uint32_t status = 0;
+	uint32_t num_remaining = max;
+
+	#define MAX_RESETS_PER_READ	1
+	uint32_t num_resets = 0;
+
+	#define MAX_IDLE_TIME	(1 * HZ)
+	unsigned long idle_endtime = jiffies + MAX_IDLE_TIME;
+
+	/* Retrieve HW RNG registers base address. */
+	void __iomem *rng_base = (void __iomem *)rng->priv;
+
+	while ((num_remaining > 0) && time_before(jiffies, idle_endtime)) {
+
+		/* Is RNG sane? If not, reset it. */
+		status = ioread32(rng_base + RNG_INT_STATUS_OFFSET);
+		if ((status & (RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK |
+			RNG_INT_STATUS_NIST_FAIL_IRQ_MASK)) != 0) {
+
+			if (num_resets >= MAX_RESETS_PER_READ)
+				return max - num_remaining;
+
+			iproc_rng200_restart(rng_base);
+			num_resets++;
+		}
+
+		/* Are there any random numbers available? */
+		if ((ioread32(rng_base + RNG_FIFO_COUNT_OFFSET) &
+				RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK) > 0) {
+
+			if (num_remaining >= sizeof(uint32_t)) {
+				/* Buffer has room to store entire word */
+				*(uint32_t *)buf = ioread32(rng_base +
+							RNG_FIFO_DATA_OFFSET);
+				buf += sizeof(uint32_t);
+				num_remaining -= sizeof(uint32_t);
+			} else {
+				/* Buffer can only store partial word */
+				uint32_t rnd_number = ioread32(rng_base +
+							RNG_FIFO_DATA_OFFSET);
+				memcpy(buf, &rnd_number, num_remaining);
+				buf += num_remaining;
+				num_remaining = 0;
+			}
+
+			/* Reset the IDLE timeout */
+			idle_endtime = jiffies + MAX_IDLE_TIME;
+		} else {
+			if (!wait)
+				/* Cannot wait, return immediately */
+				return max - num_remaining;
+
+			/* Can wait, give others chance to run */
+			cpu_relax();
+		}
+	}
+
+	return max - num_remaining;
+}
+
+static struct hwrng iproc_rng200_ops = {
+	.name	= "iproc-rng200",
+	.read	= iproc_rng200_read,
+};
+
+static int iproc_rng200_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	void __iomem *rng_base = 0;
+	uint32_t val = 0;
+	int err = 0;
+
+	/* Map peripheral */
+	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	if (!res) {
+		dev_err(dev, "failed to get rng resources\n");
+		return -ENODEV;
+	}
+
+	rng_base = devm_ioremap_resource(dev, res);
+	if (!rng_base) {
+		dev_err(dev, "failed to remap rng regs\n");
+		return -ENODEV;
+	}
+
+	iproc_rng200_ops.priv = (unsigned long)rng_base;
+
+	/* Setup RNG. */
+	val = ioread32(rng_base + RNG_CTRL_OFFSET);
+	val &= ~RNG_CTRL_RNG_RBGEN_MASK;
+	val |= RNG_CTRL_RNG_RBGEN_ENABLE;
+	iowrite32(val, rng_base + RNG_CTRL_OFFSET);
+
+	/* Register driver */
+	err = hwrng_register(&iproc_rng200_ops);
+	if (err) {
+		dev_err(dev, "hwrng registration failed\n");
+		return err;
+	}
+	dev_info(dev, "hwrng registered\n");
+
+	return 0;
+}
+
+static int iproc_rng200_remove(struct platform_device *pdev)
+{
+	uint32_t val = 0;
+	void __iomem *rng_base = (void __iomem *)iproc_rng200_ops.priv;
+
+	/* Unregister driver */
+	hwrng_unregister(&iproc_rng200_ops);
+
+	/* Disable RNG hardware */
+	val = ioread32(rng_base + RNG_CTRL_OFFSET);
+	val &= ~RNG_CTRL_RNG_RBGEN_MASK;
+	val |= RNG_CTRL_RNG_RBGEN_DISABLE;
+	iowrite32(val, rng_base + RNG_CTRL_OFFSET);
+
+	return 0;
+}
+
+static const struct of_device_id iproc_rng200_of_match[] = {
+	{ .compatible = "brcm,iproc-rng200", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, iproc_rng200_of_match);
+
+static struct platform_driver iproc_rng200_driver = {
+	.driver = {
+		.name = "iproc-rng200",
+		.of_match_table = iproc_rng200_of_match,
+	},
+	.probe		= iproc_rng200_probe,
+	.remove		= iproc_rng200_remove,
+};
+module_platform_driver(iproc_rng200_driver);
+
+MODULE_AUTHOR("Broadcom");
+MODULE_DESCRIPTION("iProc RNG200 Random Number Generator driver");
+MODULE_LICENSE("GPL v2");
-- 
2.3.0

Re: [PATCH v2 2/2] hwrng: iproc-rng200 - Add Broadcom IPROC RNG driver

[Dmitry Torokhov]

Hi Scott,

On Wed, Feb 25, 2015 at 10:16:24AM -0800, Scott Branden wrote:
> This adds a driver for random number generator present on Broadcom
> IPROC devices.
> 
> Reviewed-by: Ray Jui <rjui@broadcom.com>
> Signed-off-by: Scott Branden <sbranden@broadcom.com>
> ---
>  drivers/char/hw_random/Kconfig        |  13 ++
>  drivers/char/hw_random/Makefile       |   1 +
>  drivers/char/hw_random/iproc-rng200.c | 239 ++++++++++++++++++++++++++++++++++
>  3 files changed, 253 insertions(+)
>  create mode 100644 drivers/char/hw_random/iproc-rng200.c
> 
> diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
> index de57b38..f48cf11 100644
> --- a/drivers/char/hw_random/Kconfig
> +++ b/drivers/char/hw_random/Kconfig
> @@ -101,6 +101,19 @@ config HW_RANDOM_BCM2835
>  
>  	  If unsure, say Y.
>  
> +config HW_RANDOM_IPROC_RNG200
> +	tristate "Broadcom iProc RNG200 support"
> +	depends on ARCH_BCM_IPROC
> +	default HW_RANDOM
> +	---help---
> +	  This driver provides kernel-side support for the RNG200
> +	  hardware found on the Broadcom iProc SoCs.
> +
> +	  To compile this driver as a module, choose M here: the
> +	  module will be called iproc-rng200
> +
> +	  If unsure, say Y.
> +
>  config HW_RANDOM_GEODE
>  	tristate "AMD Geode HW Random Number Generator support"
>  	depends on X86_32 && PCI
> diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
> index 0b4cd57..055bb01 100644
> --- a/drivers/char/hw_random/Makefile
> +++ b/drivers/char/hw_random/Makefile
> @@ -28,5 +28,6 @@ obj-$(CONFIG_HW_RANDOM_POWERNV) += powernv-rng.o
>  obj-$(CONFIG_HW_RANDOM_EXYNOS)	+= exynos-rng.o
>  obj-$(CONFIG_HW_RANDOM_TPM) += tpm-rng.o
>  obj-$(CONFIG_HW_RANDOM_BCM2835) += bcm2835-rng.o
> +obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) += iproc-rng200.o
>  obj-$(CONFIG_HW_RANDOM_MSM) += msm-rng.o
>  obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o
> diff --git a/drivers/char/hw_random/iproc-rng200.c b/drivers/char/hw_random/iproc-rng200.c
> new file mode 100644
> index 0000000..4643aa9
> --- /dev/null
> +++ b/drivers/char/hw_random/iproc-rng200.c
> @@ -0,0 +1,239 @@
> +/*
> +* Copyright (C) 2014 Broadcom Corporation
> +*
> +* This program is free software; you can redistribute it and/or
> +* modify it under the terms of the GNU General Public License as
> +* published by the Free Software Foundation version 2.
> +*
> +* This program is distributed "as is" WITHOUT ANY WARRANTY of any
> +* kind, whether express or implied; without even the implied warranty
> +* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +* GNU General Public License for more details.
> +*/
> +/*
> + * DESCRIPTION: The Broadcom iProc RNG200 Driver
> + */
> +
> +#include <linux/hw_random.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/delay.h>
> +
> +
> +/* Registers */
> +#define RNG_CTRL_OFFSET					0x00
> +#define RNG_CTRL_RNG_RBGEN_MASK				0x00001FFF
> +#define RNG_CTRL_RNG_RBGEN_ENABLE			0x00000001
> +#define RNG_CTRL_RNG_RBGEN_DISABLE			0x00000000
> +
> +#define RNG_SOFT_RESET_OFFSET				0x04
> +#define RNG_SOFT_RESET_RNG_SOFT_RESET_MASK		0x00000001
> +#define RNG_SOFT_RESET_RNG_SOFT_RESET_ACTIVE		0x00000001
> +#define RNG_SOFT_RESET_RNG_SOFT_RESET_CLEAR		0x00000000
> +
> +#define RBG_SOFT_RESET_OFFSET				0x08
> +#define RBG_SOFT_RESET_RNG_SOFT_RESET_MASK		0x00000001
> +#define RBG_SOFT_RESET_RNG_SOFT_RESET_ACTIVE		0x00000001
> +#define RBG_SOFT_RESET_RNG_SOFT_RESET_CLEAR		0x00000000
> +
> +#define RNG_INT_STATUS_OFFSET				0x18
> +#define RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK	0x80000000
> +#define RNG_INT_STATUS_STARTUP_TRANSITIONS_MET_IRQ_MASK	0x00020000
> +#define RNG_INT_STATUS_NIST_FAIL_IRQ_MASK		0x00000020
> +#define RNG_INT_STATUS_TOTAL_BITS_COUNT_IRQ_MASK	0x00000001
> +
> +#define RNG_FIFO_DATA_OFFSET				0x20
> +
> +#define RNG_FIFO_COUNT_OFFSET				0x24
> +#define RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK		0x000000FF
> +
> +static void iproc_rng200_restart(void __iomem *rng_base)
> +{
> +	uint32_t val;
> +
> +	/* Disable RBG */
> +	val = ioread32(rng_base + RNG_CTRL_OFFSET);
> +	val &= ~RNG_CTRL_RNG_RBGEN_MASK;
> +	val |= RNG_CTRL_RNG_RBGEN_DISABLE;
> +	iowrite32(val, rng_base + RNG_CTRL_OFFSET);
> +
> +	/* Clear all interrupt status */
> +	iowrite32(0xFFFFFFFFUL, rng_base + RNG_INT_STATUS_OFFSET);
> +
> +	/* Reset RNG and RBG */
> +	val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
> +	val &= ~RBG_SOFT_RESET_RNG_SOFT_RESET_MASK;
> +	val |= RBG_SOFT_RESET_RNG_SOFT_RESET_ACTIVE;
> +	iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
> +
> +	val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
> +	val &= ~RNG_SOFT_RESET_RNG_SOFT_RESET_MASK;
> +	val |= RNG_SOFT_RESET_RNG_SOFT_RESET_ACTIVE;
> +	iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
> +
> +	val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
> +	val &= ~RNG_SOFT_RESET_RNG_SOFT_RESET_MASK;
> +	val |= RNG_SOFT_RESET_RNG_SOFT_RESET_CLEAR;
> +	iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
> +
> +	val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
> +	val &= ~RBG_SOFT_RESET_RNG_SOFT_RESET_MASK;
> +	val |= RBG_SOFT_RESET_RNG_SOFT_RESET_CLEAR;
> +	iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
> +
> +	/* Enable RBG */
> +	val = ioread32(rng_base + RNG_CTRL_OFFSET);
> +	val &= ~RNG_CTRL_RNG_RBGEN_MASK;
> +	val |= RNG_CTRL_RNG_RBGEN_ENABLE;
> +	iowrite32(val, rng_base + RNG_CTRL_OFFSET);
> +}
> +
> +static int iproc_rng200_read(struct hwrng *rng, void *buf, size_t max,
> +			       bool wait)
> +{
> +	uint32_t status = 0;
> +	uint32_t num_remaining = max;
> +
> +	#define MAX_RESETS_PER_READ	1
> +	uint32_t num_resets = 0;
> +
> +	#define MAX_IDLE_TIME	(1 * HZ)
> +	unsigned long idle_endtime = jiffies + MAX_IDLE_TIME;
> +
> +	/* Retrieve HW RNG registers base address. */
> +	void __iomem *rng_base = (void __iomem *)rng->priv;
> +
> +	while ((num_remaining > 0) && time_before(jiffies, idle_endtime)) {
> +
> +		/* Is RNG sane? If not, reset it. */
> +		status = ioread32(rng_base + RNG_INT_STATUS_OFFSET);
> +		if ((status & (RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK |
> +			RNG_INT_STATUS_NIST_FAIL_IRQ_MASK)) != 0) {
> +
> +			if (num_resets >= MAX_RESETS_PER_READ)
> +				return max - num_remaining;
> +
> +			iproc_rng200_restart(rng_base);
> +			num_resets++;
> +		}
> +
> +		/* Are there any random numbers available? */
> +		if ((ioread32(rng_base + RNG_FIFO_COUNT_OFFSET) &
> +				RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK) > 0) {
> +
> +			if (num_remaining >= sizeof(uint32_t)) {
> +				/* Buffer has room to store entire word */
> +				*(uint32_t *)buf = ioread32(rng_base +
> +							RNG_FIFO_DATA_OFFSET);
> +				buf += sizeof(uint32_t);
> +				num_remaining -= sizeof(uint32_t);
> +			} else {
> +				/* Buffer can only store partial word */
> +				uint32_t rnd_number = ioread32(rng_base +
> +							RNG_FIFO_DATA_OFFSET);
> +				memcpy(buf, &rnd_number, num_remaining);
> +				buf += num_remaining;
> +				num_remaining = 0;
> +			}
> +
> +			/* Reset the IDLE timeout */
> +			idle_endtime = jiffies + MAX_IDLE_TIME;
> +		} else {
> +			if (!wait)
> +				/* Cannot wait, return immediately */
> +				return max - num_remaining;
> +
> +			/* Can wait, give others chance to run */
> +			cpu_relax();
> +		}
> +	}
> +
> +	return max - num_remaining;
> +}
> +
> +static struct hwrng iproc_rng200_ops = {
> +	.name	= "iproc-rng200",
> +	.read	= iproc_rng200_read,
> +};

I would prefer if we allocated a driver-private structure that wraps
hwrng instead of using statically allocated singleton as I wonder how it
will behave if I bind/unbind the device several times.

> +
> +static int iproc_rng200_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	void __iomem *rng_base = 0;
> +	uint32_t val = 0;
> +	int err = 0;

There is no need to initialize all variables as it suppressed "used but
uninitialized" warnings from the compiler. Imagine someone adding a new
init operation and when they handle failure they forget to adjust error
code so it stays 0: for upper layers we'd signal success even though
our device/driver are half-bound.

> +
> +	/* Map peripheral */
> +	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +
> +	if (!res) {
> +		dev_err(dev, "failed to get rng resources\n");
> +		return -ENODEV;

If we have platform device but it is missing parts of necessary data it
should be -EINVAL.

> +	}
> +
> +	rng_base = devm_ioremap_resource(dev, res);
> +	if (!rng_base) {

devm_ioremap_resource() returns ERR_PTR-encoded result, you need to
check with IS_ERR().

> +		dev_err(dev, "failed to remap rng regs\n");
> +		return -ENODEV;

		return PTR_ERR(rng_base);

> +	}

There is no clock for RNG?

> +
> +	iproc_rng200_ops.priv = (unsigned long)rng_base;
> +
> +	/* Setup RNG. */
> +	val = ioread32(rng_base + RNG_CTRL_OFFSET);
> +	val &= ~RNG_CTRL_RNG_RBGEN_MASK;
> +	val |= RNG_CTRL_RNG_RBGEN_ENABLE;
> +	iowrite32(val, rng_base + RNG_CTRL_OFFSET);

That should be in [new] iproc_rng200_init().

> +
> +	/* Register driver */
> +	err = hwrng_register(&iproc_rng200_ops);
> +	if (err) {
> +		dev_err(dev, "hwrng registration failed\n");
> +		return err;
> +	}
> +	dev_info(dev, "hwrng registered\n");
> +
> +	return 0;
> +}
> +
> +static int iproc_rng200_remove(struct platform_device *pdev)
> +{
> +	uint32_t val = 0;
> +	void __iomem *rng_base = (void __iomem *)iproc_rng200_ops.priv;
> +
> +	/* Unregister driver */
> +	hwrng_unregister(&iproc_rng200_ops);
> +
> +	/* Disable RNG hardware */
> +	val = ioread32(rng_base + RNG_CTRL_OFFSET);
> +	val &= ~RNG_CTRL_RNG_RBGEN_MASK;
> +	val |= RNG_CTRL_RNG_RBGEN_DISABLE;
> +	iowrite32(val, rng_base + RNG_CTRL_OFFSET);

That should be in [new] iproc_rng200_cleanup().

> +
> +	return 0;
> +}
> +

#ifdef CONFIG_OF

maybe?

> +static const struct of_device_id iproc_rng200_of_match[] = {
> +	{ .compatible = "brcm,iproc-rng200", },
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, iproc_rng200_of_match);
> +
> +static struct platform_driver iproc_rng200_driver = {
> +	.driver = {
> +		.name = "iproc-rng200",
> +		.of_match_table = iproc_rng200_of_match,
> +	},
> +	.probe		= iproc_rng200_probe,
> +	.remove		= iproc_rng200_remove,
> +};
> +module_platform_driver(iproc_rng200_driver);
> +
> +MODULE_AUTHOR("Broadcom");
> +MODULE_DESCRIPTION("iProc RNG200 Random Number Generator driver");
> +MODULE_LICENSE("GPL v2");
> -- 
> 2.3.0
> 

Thanks.

-- 
Dmitry

Re: [PATCH v2 2/2] hwrng: iproc-rng200 - Add Broadcom IPROC RNG driver

[Arnd Bergmann]

On Wednesday 25 February 2015 10:16:24 Scott Branden wrote:
> This adds a driver for random number generator present on Broadcom
> IPROC devices.
> 
> Reviewed-by: Ray Jui <rjui@broadcom.com>
> Signed-off-by: Scott Branden <sbranden@broadcom.com>

The driver looks reasonable overall, I have just one question about
something that sticks out:

> +	while ((num_remaining > 0) && time_before(jiffies, idle_endtime)) {
...
> +
> +		/* Are there any random numbers available? */
> +		if ((ioread32(rng_base + RNG_FIFO_COUNT_OFFSET) &
> +				RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK) > 0) {
...
> +		} else {
> +			if (!wait)
> +				/* Cannot wait, return immediately */
> +				return max - num_remaining;
> +
> +			/* Can wait, give others chance to run */
> +			cpu_relax();
> +		}
> +	}
> +

It looks like you do a busy-loop around cpu_relax here if asked to wait.
Is this intentional? I would normally expect either cond_resched() or
some msleep() instead.

	Arnd

[PATCH v2 0/2] Add support for Broadcom keypad controller

[Scott Branden]

This series of patchsets contains the Broadcom keypad controller driver
and device tree binding documentation.

Changes from v1:
- updated dt documentation to remove to matrix-keymap.txt
- removed bcm_kp_remove as it is not necessary
- removed key-interrupt-trigger-type dt binding
- added bcm_kp_report_keys and call to process key registers

Scott Branden (2):
  Input: bcm-keypad: add device tree bindings
  Input: bcm-keypad: Add Broadcom keypad controller

 .../devicetree/bindings/input/brcm,bcm-keypad.txt  | 108 +++++
 drivers/input/keyboard/Kconfig                     |  10 +
 drivers/input/keyboard/Makefile                    |   1 +
 drivers/input/keyboard/bcm-keypad.c                | 464 +++++++++++++++++++++
 4 files changed, 583 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
 create mode 100644 drivers/input/keyboard/bcm-keypad.c

-- 
2.3.0

[PATCH v2 1/2] Input: bcm-keypad: add device tree bindings

[Scott Branden]

Documents the Broadcom keypad controller device tree bindings.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 .../devicetree/bindings/input/brcm,bcm-keypad.txt  | 108 +++++++++++++++++++++
 1 file changed, 108 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt

diff --git a/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt b/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
new file mode 100644
index 0000000..e16bb2d
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
@@ -0,0 +1,108 @@
+* Broadcom Keypad Controller device tree bindings
+
+Broadcom Keypad controller is used to interface a SoC with a matrix-type
+keypad device. The keypad controller supports multiple row and column lines.
+A key can be placed at each intersection of a unique row and a unique column.
+The keypad controller can sense a key-press and key-release and report the
+event using a interrupt to the cpu.
+
+This binding is based on the matrix-keymap binding with the following
+changes:
+
+keypad,num-rows and keypad,num-columns are required.
+
+Required SoC Specific Properties:
+- compatible: should be "brcm,bcm-keypad"
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- interrupts: The interrupt number to the cpu.
+
+Board Specific Properties:
+- keypad,num-rows: Number of row lines connected to the keypad
+  controller.
+
+- keypad,num-columns: Number of column lines connected to the
+  keypad controller.
+
+- col-debounce-filter-period: The debounce period for the Column filter.
+
+	KEYPAD_DEBOUNCE_1_ms	=	0
+	KEYPAD_DEBOUNCE_2_ms	=	1
+	KEYPAD_DEBOUNCE_4_ms	=	2
+	KEYPAD_DEBOUNCE_8_ms	=	3
+	KEYPAD_DEBOUNCE_16_ms	=	4
+	KEYPAD_DEBOUNCE_32_ms	=	5
+	KEYPAD_DEBOUNCE_64_ms	=	6
+	KEYPAD_DEBOUNCE_128_ms	=	7
+
+- status-debounce-filter-period: The debounce period for the Status filter.
+
+	KEYPAD_DEBOUNCE_1_ms	=	0
+	KEYPAD_DEBOUNCE_2_ms	=	1
+	KEYPAD_DEBOUNCE_4_ms	=	2
+	KEYPAD_DEBOUNCE_8_ms	=	3
+	KEYPAD_DEBOUNCE_16_ms	=	4
+	KEYPAD_DEBOUNCE_32_ms	=	5
+	KEYPAD_DEBOUNCE_64_ms	=	6
+	KEYPAD_DEBOUNCE_128_ms	=	7
+
+- row-output-enabled: An optional property indicating whether the row or
+  column is being used as output. If specified the row is being used
+  as the output. Else defaults to column.
+
+- pull-up-enabled: An optional property indicating the Keypad scan mode.
+  If specified implies the keypad scan pull-up has been enabled.
+
+- linux,keypad-no-autorepeat: An optional property indicating to
+  not enable autorepeat feature.
+
+- linux,keymap: The keymap for keys as described in the binding document
+  devicetree/bindings/input/matrix-keymap.txt.
+
+Example:
+#include "dt-bindings/input/input.h"
+
+/ {
+	keypad: keypad@180ac000 {
+		/* Required SoC specific properties */
+		compatible = "brcm,bcm-keypad";
+
+		/* Required Board specific properties */
+		keypad,num-rows = <5>;
+		keypad,num-columns = <5>;
+		status = "okay";
+
+		linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_F) /* key_forward */
+		MATRIX_KEY(0x00, 0x03, KEY_HOME) /* key_home */
+		MATRIX_KEY(0x00, 0x04, KEY_M) /* key_message */
+		MATRIX_KEY(0x01, 0x00, KEY_A) /* key_contacts */
+		MATRIX_KEY(0x01, 0x01, KEY_1) /* key_1 */
+		MATRIX_KEY(0x01, 0x02, KEY_2) /* key_2 */
+		MATRIX_KEY(0x01, 0x03, KEY_3) /* key_3 */
+		MATRIX_KEY(0x01, 0x04, KEY_S) /* key_speaker */
+		MATRIX_KEY(0x02, 0x00, KEY_P) /* key_phone */
+		MATRIX_KEY(0x02, 0x01, KEY_4) /* key_4 */
+		MATRIX_KEY(0x02, 0x02, KEY_5) /* key_5 */
+		MATRIX_KEY(0x02, 0x03, KEY_6) /* key_6 */
+		MATRIX_KEY(0x02, 0x04, KEY_VOLUMEUP) /* key_vol_up */
+		MATRIX_KEY(0x03, 0x00, KEY_C) /* key_call_log */
+		MATRIX_KEY(0x03, 0x01, KEY_7) /* key_7 */
+		MATRIX_KEY(0x03, 0x02, KEY_8) /* key_8 */
+		MATRIX_KEY(0x03, 0x03, KEY_9) /* key_9 */
+		MATRIX_KEY(0x03, 0x04, KEY_VOLUMEDOWN) /* key_vol_down */
+		MATRIX_KEY(0x04, 0x00, KEY_H) /* key_headset */
+		MATRIX_KEY(0x04, 0x01, KEY_KPASTERISK) /* key_* */
+		MATRIX_KEY(0x04, 0x02, KEY_0) /* key_0 */
+		MATRIX_KEY(0x04, 0x03, KEY_GRAVE) /* key_# */
+		MATRIX_KEY(0x04, 0x04, KEY_MUTE) /* key_mute */
+		>;
+
+		/* Optional board specific properties */
+		col-debounce-filter-period = <5>;
+		row-output-enabled;
+		pull-up-enabled;
+
+	};
+};
-- 
2.3.0

[PATCH v2 2/2] Input: bcm-keypad: Add Broadcom keypad controller

[Scott Branden]

Add driver for Broadcom's keypad controller.

Broadcom Keypad controller is used to interface a SoC with a matrix-type
keypad device. The keypad controller supports multiple row and column lines.
A key can be placed at each intersection of a unique row and a unique column.
The keypad controller can sense a key-press and key-release and report the
event using a interrupt to the cpu.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/input/keyboard/Kconfig      |  10 +
 drivers/input/keyboard/Makefile     |   1 +
 drivers/input/keyboard/bcm-keypad.c | 464 ++++++++++++++++++++++++++++++++++++
 3 files changed, 475 insertions(+)
 create mode 100644 drivers/input/keyboard/bcm-keypad.c

diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index a5d9b3f..3a0c0f2 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -676,4 +676,14 @@ config KEYBOARD_CAP11XX
 	  To compile this driver as a module, choose M here: the
 	  module will be called cap11xx.
 
+config KEYBOARD_BCM
+	tristate "Broadcom keypad driver"
+	select INPUT_MATRIXKMAP
+	default ARCH_BCM_CYGNUS
+	help
+	  Say Y here if you want to use Broadcom keypad.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called bcm-keypad.
+
 endif
diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
index febafa5..3cff8f6 100644
--- a/drivers/input/keyboard/Makefile
+++ b/drivers/input/keyboard/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_KEYBOARD_ADP5589)		+= adp5589-keys.o
 obj-$(CONFIG_KEYBOARD_AMIGA)		+= amikbd.o
 obj-$(CONFIG_KEYBOARD_ATARI)		+= atakbd.o
 obj-$(CONFIG_KEYBOARD_ATKBD)		+= atkbd.o
+obj-$(CONFIG_KEYBOARD_BCM)		+= bcm-keypad.o
 obj-$(CONFIG_KEYBOARD_BFIN)		+= bf54x-keys.o
 obj-$(CONFIG_KEYBOARD_CAP11XX)		+= cap11xx.o
 obj-$(CONFIG_KEYBOARD_CLPS711X)		+= clps711x-keypad.o
diff --git a/drivers/input/keyboard/bcm-keypad.c b/drivers/input/keyboard/bcm-keypad.c
new file mode 100644
index 0000000..f229ac0
--- /dev/null
+++ b/drivers/input/keyboard/bcm-keypad.c
@@ -0,0 +1,464 @@
+/*
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/bitops.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/sizes.h>
+#include <linux/stddef.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <asm/memory.h>
+#include <linux/io.h>
+#include <linux/input/matrix_keypad.h>
+
+#define DEFAULT_CLK_HZ                  31250
+/* Repeat period (ms) */
+#define KEY_REPEAT_PERIOD               100
+/* First time press dly (ms) */
+#define KEY_REPEAT_DELAY                400
+#define MAX_ROWS                        8
+#define MAX_COLS                        8
+
+/* Register/field definitions */
+#define KPCR_OFFSET                          0x00000080
+#define KPCR_MODE                       0x00000002
+#define KPCR_MODE_SHIFT                 1
+#define KPCR_MODE_MASK                  1
+#define KPCR_ENABLE                     0x00000001
+#define KPCR_STATUSFILTERENABLE         0x00008000
+#define KPCR_STATUSFILTERTYPE_SHIFT          12
+#define KPCR_COLFILTERENABLE            0x00000800
+#define KPCR_COLFILTERTYPE_SHIFT             8
+#define KPCR_ROWWIDTH_SHIFT                  20
+#define KPCR_COLUMNWIDTH_SHIFT               16
+
+#define KPIOR_OFFSET                         0x00000084
+#define KPIOR_ROWOCONTRL_SHIFT               24
+#define KPIOR_ROWOCONTRL_MASK                0xFF000000
+#define KPIOR_COLUMNOCONTRL_SHIFT            16
+#define KPIOR_COLUMNOCONTRL_MASK             0x00FF0000
+#define KPIOR_COLUMN_IO_DATA_SHIFT           0
+
+#define KPEMR0_OFFSET                        0x00000090
+#define KPEMR1_OFFSET                        0x00000094
+#define KPEMR2_OFFSET                        0x00000098
+#define KPEMR3_OFFSET                        0x0000009C
+#define KPEMR_EDGETYPE_BOTH 3
+
+#define KPSSR0_OFFSET                        0x000000A0
+#define KPSSR1_OFFSET                        0x000000A4
+#define KPSSRN_OFFSET(reg_n)                 (KPSSR0_OFFSET + (4 * reg_n))
+#define KPIMR0_OFFSET                        0x000000B0
+#define KPIMR1_OFFSET                        0x000000B4
+#define KPICR0_OFFSET                        0x000000B8
+#define KPICR1_OFFSET                        0x000000BC
+#define KPICRN_OFFSET(reg_n)                 (KPICR0_OFFSET + (4 * reg_n))
+#define KPISR0_OFFSET                        0x000000C0
+#define KPISR1_OFFSET                        0x000000C4
+
+#define KPCR_STATUSFILTERTYPE_MAX 7
+#define KPCR_COLFILTERTYPE_MAX 7
+
+/* Macros to determine the row/column from a bit that is set in SSR0/1. */
+#define BIT_TO_ROW_SSRN(bit_nr, reg_n)  ((bit_nr >> 3) + (4 * reg_n))
+#define BIT_TO_COL(bit_nr)       (bit_nr % 8)
+
+/* Structure representing various run-time entities */
+struct bcm_kp {
+	void __iomem *base;
+	int irq;
+	struct clk *clk;
+	struct input_dev *input_dev;
+	unsigned long last_state[2];
+	unsigned int n_rows;
+	unsigned int n_cols;
+	u32 kpcr;
+	u32 kpior;
+	u32 kpemr;
+	u32 imr0_val;
+	u32 imr1_val;
+};
+
+/*
+ * Returns the keycode from the input device keymap given the row and
+ * column.
+ */
+static inline int bcm_kp_get_keycode(struct bcm_kp *kp, int row, int col)
+{
+	unsigned int row_shift = get_count_order(kp->n_cols);
+	unsigned short *keymap = kp->input_dev->keycode;
+
+	return keymap[MATRIX_SCAN_CODE(row, col, row_shift)];
+}
+
+static void bcm_kp_report_keys(struct bcm_kp *kp, int reg_num, int pull_mode)
+{
+	unsigned long state, change;
+	int bit_nr;
+	int key_press;
+	int row, col;
+	unsigned int keycode;
+
+	/* Clear interrupts */
+	writel(0xFFFFFFFF, kp->base + KPICRN_OFFSET(reg_num));
+
+	state = readl(kp->base + KPSSRN_OFFSET(reg_num));
+	change = kp->last_state[reg_num] ^ state;
+	kp->last_state[reg_num] = state;
+
+	for_each_set_bit(bit_nr, &change, BITS_PER_LONG) {
+		key_press = state & BIT(bit_nr);
+		/* The meaning of SSR register depends on pull mode. */
+		key_press = pull_mode ? !key_press : key_press;
+		row = BIT_TO_ROW_SSRN(bit_nr, reg_num);
+		col = BIT_TO_COL(bit_nr);
+		keycode = bcm_kp_get_keycode(kp, row, col);
+		input_report_key(kp->input_dev, keycode, key_press);
+	}
+}
+
+static irqreturn_t bcm_kp_isr_thread(int irq, void *dev_id)
+{
+	struct bcm_kp *kp = dev_id;
+	int pull_mode = (kp->kpcr >> KPCR_MODE_SHIFT) & KPCR_MODE_MASK;
+	int reg_num;
+
+	for (reg_num = 0; reg_num <= 1; reg_num++)
+		bcm_kp_report_keys(kp, reg_num, pull_mode);
+
+	input_sync(kp->input_dev);
+
+	return IRQ_HANDLED;
+}
+
+static int bcm_kp_start(struct bcm_kp *kp)
+{
+	int error;
+
+	error = clk_prepare_enable(kp->clk);
+	if (error)
+		return error;
+
+	writel(kp->kpior, kp->base + KPIOR_OFFSET);
+
+	writel(kp->imr0_val, kp->base + KPIMR0_OFFSET);
+	writel(kp->imr1_val, kp->base + KPIMR1_OFFSET);
+
+	writel(kp->kpemr, kp->base + KPEMR0_OFFSET);
+	writel(kp->kpemr, kp->base + KPEMR1_OFFSET);
+	writel(kp->kpemr, kp->base + KPEMR2_OFFSET);
+	writel(kp->kpemr, kp->base + KPEMR3_OFFSET);
+
+	writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET);
+	writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET);
+
+	kp->last_state[0] = readl(kp->base + KPSSR0_OFFSET);
+	kp->last_state[0] = readl(kp->base + KPSSR1_OFFSET);
+
+	writel(kp->kpcr | KPCR_ENABLE, kp->base + KPCR_OFFSET);
+
+	return 0;
+}
+
+static void bcm_kp_stop(const struct bcm_kp *kp)
+{
+	u32 val;
+
+	val = readl(kp->base + KPCR_OFFSET);
+	val &= ~KPCR_ENABLE;
+	writel(0, kp->base + KPCR_OFFSET);
+	writel(0, kp->base + KPIMR0_OFFSET);
+	writel(0, kp->base + KPIMR1_OFFSET);
+	writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET);
+	writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET);
+
+	clk_disable_unprepare(kp->clk);
+}
+
+static int bcm_kp_open(struct input_dev *dev)
+{
+	struct bcm_kp *kp = input_get_drvdata(dev);
+
+	return bcm_kp_start(kp);
+}
+
+static void bcm_kp_close(struct input_dev *dev)
+{
+	struct bcm_kp *kp = input_get_drvdata(dev);
+
+	bcm_kp_stop(kp);
+}
+
+static int bcm_kp_matrix_key_parse_dt(struct bcm_kp *kp)
+{
+	struct device *dev = kp->input_dev->dev.parent;
+	struct device_node *np = dev->of_node;
+	int error;
+	unsigned int dt_val;
+	unsigned int i;
+
+	/* Initialize the KPCR Keypad Configuration Register */
+	kp->kpcr = KPCR_STATUSFILTERENABLE | KPCR_COLFILTERENABLE;
+
+	error = matrix_keypad_parse_of_params(dev, &kp->n_rows, &kp->n_cols);
+	if (error) {
+		dev_err(dev, "failed to parse kp params\n");
+		return error;
+	}
+	/* Set row width for the ASIC block. */
+	kp->kpcr |= (kp->n_rows - 1) << KPCR_ROWWIDTH_SHIFT;
+
+	/* Set column width for the ASIC block. */
+	kp->kpcr |= (kp->n_cols - 1) << KPCR_COLUMNWIDTH_SHIFT;
+
+	/* Configure the IMR registers */
+	{
+		unsigned int num_rows, col_mask, rows_set;
+
+		/* IMR registers contain interrupt enable bits for 8x8 matrix
+		 * IMR0 register format: <row3> <row2> <row1> <row0>
+		 * IMR1 register format: <row7> <row6> <row5> <row4>
+		 */
+
+		col_mask = (1 << (kp->n_cols)) - 1;
+		num_rows = kp->n_rows;
+
+		/* Set column bits in rows 0 to 3 in IMR0 */
+		kp->imr0_val = col_mask;
+
+		rows_set = 1;
+		while ((--num_rows) && (rows_set++ < 4))
+			kp->imr0_val |= (kp->imr0_val << MAX_COLS);
+
+		/* Set column bits in rows 4 to 7 in IMR1 */
+		kp->imr1_val = 0;
+		if (num_rows) {
+			kp->imr1_val = col_mask;
+			while (--num_rows)
+				kp->imr1_val |= (kp->imr1_val << MAX_COLS);
+		}
+	}
+
+	/* Initialize the KPEMR Keypress Edge Mode Registers */
+	/* Trigger on both edges */
+	kp->kpemr = 0;
+	for (i = 0; i <= 30; i = i + 2)
+		kp->kpemr |= (KPEMR_EDGETYPE_BOTH << i);
+
+	/*
+	 * Obtain the Status filter debounce value and verify against the
+	 * possible values specified in the DT binding.
+	 */
+	of_property_read_u32(np, "status-debounce-filter-period",
+		&dt_val);
+	if (dt_val > KPCR_STATUSFILTERTYPE_MAX) {
+		dev_err(dev, "Invalid Status filter debounce value %d\n",
+			dt_val);
+		return -EINVAL;
+	}
+	kp->kpcr |= dt_val << KPCR_STATUSFILTERTYPE_SHIFT;
+
+
+	/*
+	 * Obtain the Column filter debounce value and verify against the
+	 * possible values specified in the DT binding.
+	 */
+	of_property_read_u32(np, "col-debounce-filter-period",
+		&dt_val);
+
+	if (dt_val > KPCR_COLFILTERTYPE_MAX) {
+		dev_err(dev, "Invalid Column filter debounce value %d\n",
+			dt_val);
+		return -EINVAL;
+	}
+	kp->kpcr |= dt_val << KPCR_COLFILTERTYPE_SHIFT;
+
+	/*
+	 * Determine between the row and column,
+	 * which should be configured as output.
+	 */
+	if (of_property_read_bool(np, "row-output-enabled")) {
+		/*
+		* Set RowOContrl or ColumnOContrl in KPIOR
+		* to the number of pins to drive as outputs
+		*/
+		kp->kpior = (((1 << kp->n_rows) - 1) <<
+				KPIOR_ROWOCONTRL_SHIFT);
+	} else {
+		kp->kpior = (((1 << kp->n_cols) - 1) <<
+				KPIOR_COLUMNOCONTRL_SHIFT);
+	}
+
+	/*
+	 * Determine if the scan pull up needs to be enabled
+	 */
+	if (of_property_read_bool(np, "pull-up-enabled"))
+		kp->kpcr |= KPCR_MODE;
+
+	dev_dbg(dev, "n_rows=%d n_col=%d kpcr=%x kpior=%x kpemr=%x\n",
+		kp->n_rows, kp->n_cols,
+		kp->kpcr, kp->kpior, kp->kpemr);
+
+	return 0;
+}
+
+
+static int bcm_kp_probe(struct platform_device *pdev)
+{
+	struct bcm_kp *kp;
+	struct input_dev *input_dev;
+	struct resource *res;
+	int error;
+	bool repeat;
+
+	kp = devm_kzalloc(&pdev->dev, sizeof(*kp),
+				   GFP_KERNEL);
+	if (!kp)
+		return -ENOMEM;
+
+	input_dev = devm_input_allocate_device(&pdev->dev);
+	if (!input_dev) {
+		dev_err(&pdev->dev, "failed to allocate the input device\n");
+		return -ENOMEM;
+	}
+
+	__set_bit(EV_KEY, input_dev->evbit);
+
+	repeat = !of_property_read_bool(pdev->dev.of_node,
+					"linux,input-no-autorepeat");
+	if (repeat)
+		__set_bit(EV_REP, input_dev->evbit);
+
+	input_dev->name = pdev->name;
+	input_dev->phys = "keypad/input0";
+	input_dev->dev.parent = &pdev->dev;
+	input_dev->open = bcm_kp_open;
+	input_dev->close = bcm_kp_close;
+
+	input_dev->id.bustype = BUS_HOST;
+	input_dev->id.vendor = 0x0001;
+	input_dev->id.product = 0x0001;
+	input_dev->id.version = 0x0100;
+
+	input_set_drvdata(input_dev, kp);
+
+	kp->input_dev = input_dev;
+
+	platform_set_drvdata(pdev, kp);
+
+	error = bcm_kp_matrix_key_parse_dt(kp);
+	if (error)
+		return error;
+
+	error = matrix_keypad_build_keymap(NULL, NULL,
+					   kp->n_rows,
+					   kp->n_cols,
+					   NULL, input_dev);
+	if (error) {
+		dev_err(&pdev->dev, "failed to build keymap\n");
+		return error;
+	}
+
+	/* Get the KEYPAD base address */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "Missing keypad base address resource\n");
+		return -ENODEV;
+	}
+
+	kp->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(kp->base))
+		return PTR_ERR(kp->base);
+
+	/* Enable clock */
+
+	kp->clk = devm_clk_get(&pdev->dev, "peri_clk");
+	if (IS_ERR(kp->clk))
+		dev_info(&pdev->dev,
+			"No clock specified. Assuming it's enabled\n");
+	else {
+		unsigned int desired_rate;
+		long actual_rate;
+
+		error = of_property_read_u32(pdev->dev.of_node,
+				"clock-frequency", &desired_rate);
+		if (error < 0)
+			desired_rate = DEFAULT_CLK_HZ;
+
+		actual_rate = clk_round_rate(kp->clk, desired_rate);
+		if (actual_rate <= 0)
+			return -EINVAL;
+
+		error = clk_set_rate(kp->clk, actual_rate);
+		if (error)
+			return -EINVAL;
+
+		error = clk_prepare_enable(kp->clk);
+		if (error)
+			return -EINVAL;
+	}
+
+	/* Put the kp into a known sane state */
+	bcm_kp_stop(kp);
+
+	kp->irq = platform_get_irq(pdev, 0);
+	if (kp->irq < 0) {
+		dev_err(&pdev->dev, "no IRQ specified\n");
+		return -EINVAL;
+	}
+
+	error = devm_request_threaded_irq(&pdev->dev, kp->irq, NULL,
+		bcm_kp_isr_thread,
+		IRQF_ONESHOT, pdev->name, kp);
+	if (error) {
+		dev_err(&pdev->dev, "failed to request IRQ\n");
+		return error;
+	}
+
+	error = input_register_device(input_dev);
+	if (error) {
+		dev_err(&pdev->dev, "failed to register input device\n");
+		return error;
+	}
+
+	return 0;
+}
+
+static const struct of_device_id bcm_kp_of_match[] = {
+	{ .compatible = "brcm,bcm-keypad" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, bcm_kp_of_match);
+
+static struct platform_driver bcm_kp_device_driver = {
+	.probe		= bcm_kp_probe,
+	.driver		= {
+		.name	= "bcm-keypad",
+		.of_match_table = of_match_ptr(bcm_kp_of_match),
+	}
+};
+
+module_platform_driver(bcm_kp_device_driver);
+
+MODULE_AUTHOR("Broadcom Corporation");
+MODULE_DESCRIPTION("BCM Keypad Driver");
+MODULE_LICENSE("GPL");
-- 
2.3.0

Re: [PATCH 1/2] Input: bcm-keypad: add device tree bindings

[Scott Branden]

Hi Dmitry,

Thanks for the update of no need to change any of dt-binding prefixes. 
I just sent out a v2 patch addressing all of your other comments.

On 15-02-23 09:49 AM, Dmitry Torokhov wrote:
> Hi Scott,
>
> On Sun, Feb 15, 2015 at 09:17:51PM -0800, Dmitry Torokhov wrote:
>> On Sat, Feb 14, 2015 at 08:49:15AM -0800, Scott Branden wrote:
>>> On 15-02-09 04:51 PM, Dmitry Torokhov wrote:
>>>> On Mon, Feb 09, 2015 at 04:07:40PM -0800, Scott Branden wrote:
>>>>> +
>>>>> +- col-debounce-filter-period: The debounce period for the Column filter.
>>>>> +
>>>>> +	KEYPAD_DEBOUNCE_1_ms	=	0
>>>>> +	KEYPAD_DEBOUNCE_2_ms	=	1
>>>>> +	KEYPAD_DEBOUNCE_4_ms	=	2
>>>>> +	KEYPAD_DEBOUNCE_8_ms	=	3
>>>>
>>>>> +	KEYPAD_DEBOUNCE_16_ms	=	4
>>>>> +	KEYPAD_DEBOUNCE_32_ms	=	5
>>>>> +	KEYPAD_DEBOUNCE_64_ms	=	6
>>>>> +	KEYPAD_DEBOUNCE_128_ms	=	7
>>>>> +
>>>>> +- status-debounce-filter-period: The debounce period for the Status filter.
>>>>> +
>>>>> +	KEYPAD_DEBOUNCE_1_ms	=	0
>>>>> +	KEYPAD_DEBOUNCE_2_ms	=	1
>>>>> +	KEYPAD_DEBOUNCE_4_ms	=	2
>>>>> +	KEYPAD_DEBOUNCE_8_ms	=	3
>>>>> +	KEYPAD_DEBOUNCE_16_ms	=	4
>>>>> +	KEYPAD_DEBOUNCE_32_ms	=	5
>>>>> +	KEYPAD_DEBOUNCE_64_ms	=	6
>>>>> +	KEYPAD_DEBOUNCE_128_ms	=	7
>>>>
>>>> I could swear device-specific properties should be in form of
>>>> <vendor-prefix>,<property-name> to ensure it won't clash with changes on
>>>> subsystem level later on. Device-tree folks, what say you?
>>> I see examples with and without vendor-prefix.
>>> qcom,pm8xxx-keypad.txt does not have prefixes
>>> st-keyscan.txt does have a prefix
>>>
>>> I can't find any documented guidelines for this.
>>
>> As I mentioned I'll try to get clarification on this.
>
> I have chatted with a couple of people on this and it is acceptable to
> omit vendor prefix in bindings when we are using a specific driver like
> we have here (i.e. when driver's compatible string already includes
> vendor prefix). Vendor prefixes on properties are required when we
> augment a generic driver's binding.
>
> So the above 2 entries are fine as is.
>
> Thanks.
>

Re: [PATCH 0/4] Add support for IPROC SDHCI controller

[Scott Branden]

Hi Chris,

I have not heard any more feedback on this patchset.  Is it in your 
queue to review or merge into your tree?

Thanks,
  Scott

On 15-02-09 04:06 PM, Scott Branden wrote:
> This series of patchsets contains the IPROC SDHCI driver used
> in a series of Broadcom SoCs
> Quirks are also added to support this controller.
>
> Corneliu Doban (1):
>    mmc: sdhci: do not set AUTO_CMD12 for multi-block CMD53
>
> Scott Branden (3):
>    mmc: sdhci: add quirk for ACMD23 broken
>    mmc: sdhci-iproc: add IPROC SDHCI driver
>    mmc: sdhci-iproc: add device tree bindings
>
>   .../devicetree/bindings/mmc/brcm,sdhci-iproc.txt   |  23 ++
>   drivers/mmc/host/Kconfig                           |  14 ++
>   drivers/mmc/host/Makefile                          |   1 +
>   drivers/mmc/host/sdhci-iproc.c                     | 241 +++++++++++++++++++++
>   drivers/mmc/host/sdhci.c                           |   7 +-
>   include/linux/mmc/sdhci.h                          |   2 +
>   6 files changed, 286 insertions(+), 2 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt
>   create mode 100644 drivers/mmc/host/sdhci-iproc.c
>

Re: [PATCH v2 2/2] hwrng: iproc-rng200 - Add Broadcom IPROC RNG driver

[Scott Branden]

Response inline.

On 15-02-25 11:17 AM, Arnd Bergmann wrote:
> On Wednesday 25 February 2015 10:16:24 Scott Branden wrote:
>> This adds a driver for random number generator present on Broadcom
>> IPROC devices.
>>
>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>
> The driver looks reasonable overall, I have just one question about
> something that sticks out:
>
>> +	while ((num_remaining > 0) && time_before(jiffies, idle_endtime)) {
> ...
>> +
>> +		/* Are there any random numbers available? */
>> +		if ((ioread32(rng_base + RNG_FIFO_COUNT_OFFSET) &
>> +				RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK) > 0) {
> ...
>> +		} else {
>> +			if (!wait)
>> +				/* Cannot wait, return immediately */
>> +				return max - num_remaining;
>> +
>> +			/* Can wait, give others chance to run */
>> +			cpu_relax();
>> +		}
>> +	}
>> +
>
> It looks like you do a busy-loop around cpu_relax here if asked to wait.
> Is this intentional? I would normally expect either cond_resched() or
> some msleep() instead.

This code was following examples of other open source drivers - bcm2835 
and exynos both use cpu_relax.  I'll have to look into this more to 
understand.

>
> 	Arnd
>

Re: [PATCH v2 2/2] hwrng: iproc-rng200 - Add Broadcom IPROC RNG driver

[Arnd Bergmann]

On Thursday 26 February 2015 11:37:20 Scott Branden wrote:
> Response inline.
> 
> On 15-02-25 11:17 AM, Arnd Bergmann wrote:
> > On Wednesday 25 February 2015 10:16:24 Scott Branden wrote:
> >> This adds a driver for random number generator present on Broadcom
> >> IPROC devices.
> >>
> >> Reviewed-by: Ray Jui <rjui@broadcom.com>
> >> Signed-off-by: Scott Branden <sbranden@broadcom.com>
> >
> > The driver looks reasonable overall, I have just one question about
> > something that sticks out:
> >
> >> +    while ((num_remaining > 0) && time_before(jiffies, idle_endtime)) {
> > ...
> >> +
> >> +            /* Are there any random numbers available? */
> >> +            if ((ioread32(rng_base + RNG_FIFO_COUNT_OFFSET) &
> >> +                            RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK) > 0) {
> > ...
> >> +            } else {
> >> +                    if (!wait)
> >> +                            /* Cannot wait, return immediately */
> >> +                            return max - num_remaining;
> >> +
> >> +                    /* Can wait, give others chance to run */
> >> +                    cpu_relax();
> >> +            }
> >> +    }
> >> +
> >
> > It looks like you do a busy-loop around cpu_relax here if asked to wait.
> > Is this intentional? I would normally expect either cond_resched() or
> > some msleep() instead.
> 
> This code was following examples of other open source drivers - bcm2835 
> and exynos both use cpu_relax.  I'll have to look into this more to 
> understand.
> 

The majority of the driver apparently use udelay(10) to wait, which is
not much better but at least consistent. The cpu_relax() call probably
gives better throughput.

I don't understand why none of the drivers actually attempts to
msleep(), but that may be because the delay is much too long.

Can you find out what the expected latency is for new data to
become available on your hardware?

	Arnd

Re: [PATCH v2 2/2] hwrng: iproc-rng200 - Add Broadcom IPROC RNG driver

[Scott Branden]

Hi Arnd,

Latency is 32 us for 32bits of data - commented inline.  What delay call 
do you recommend in this case?

On 15-02-26 12:15 PM, Arnd Bergmann wrote:
> On Thursday 26 February 2015 11:37:20 Scott Branden wrote:
>> Response inline.
>>
>> On 15-02-25 11:17 AM, Arnd Bergmann wrote:
>>> On Wednesday 25 February 2015 10:16:24 Scott Branden wrote:
>>>> This adds a driver for random number generator present on Broadcom
>>>> IPROC devices.
>>>>
>>>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>>>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>>>
>>> The driver looks reasonable overall, I have just one question about
>>> something that sticks out:
>>>
>>>> +    while ((num_remaining > 0) && time_before(jiffies, idle_endtime)) {
>>> ...
>>>> +
>>>> +            /* Are there any random numbers available? */
>>>> +            if ((ioread32(rng_base + RNG_FIFO_COUNT_OFFSET) &
>>>> +                            RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK) > 0) {
>>> ...
>>>> +            } else {
>>>> +                    if (!wait)
>>>> +                            /* Cannot wait, return immediately */
>>>> +                            return max - num_remaining;
>>>> +
>>>> +                    /* Can wait, give others chance to run */
>>>> +                    cpu_relax();
>>>> +            }
>>>> +    }
>>>> +
>>>
>>> It looks like you do a busy-loop around cpu_relax here if asked to wait.
>>> Is this intentional? I would normally expect either cond_resched() or
>>> some msleep() instead.
>>
>> This code was following examples of other open source drivers - bcm2835
>> and exynos both use cpu_relax.  I'll have to look into this more to
>> understand.
>>
>
> The majority of the driver apparently use udelay(10) to wait, which is
> not much better but at least consistent. The cpu_relax() call probably
> gives better throughput.
>
> I don't understand why none of the drivers actually attempts to
> msleep(), but that may be because the delay is much too long.
>
> Can you find out what the expected latency is for new data to
> become available on your hardware?
RNG generates at a nominal 1 Mbps.  So to generate 32 bits of data takes
approximately 32 us.

>
> 	Arnd
>

Re: [PATCH v2 2/2] hwrng: iproc-rng200 - Add Broadcom IPROC RNG driver

[Arnd Bergmann]

On Thursday 26 February 2015 14:26:02 Scott Branden wrote:
> On 15-02-26 12:15 PM, Arnd Bergmann wrote:
> >> On 15-02-25 11:17 AM, Arnd Bergmann wrote:
> >>> On Wednesday 25 February 2015 10:16:24 Scott Branden wrote:
> >> This code was following examples of other open source drivers - bcm2835
> >> and exynos both use cpu_relax.  I'll have to look into this more to
> >> understand.
> >>
> >
> > The majority of the driver apparently use udelay(10) to wait, which is
> > not much better but at least consistent. The cpu_relax() call probably
> > gives better throughput.
> >
> > I don't understand why none of the drivers actually attempts to
> > msleep(), but that may be because the delay is much too long.
> >
> > Can you find out what the expected latency is for new data to
> > become available on your hardware?
> RNG generates at a nominal 1 Mbps.  So to generate 32 bits of data takes
> approximately 32 us.

The udelay(10) that the other drivers have seems about appropriate then,
and we can independently think of a way to refine the interface.
Please add a comment that explains the rate. Also, is there some kind
of FIFO present in the hwrng device? If it can store close to 1ms work
of data (1000 bits), you can just use an msleep(1) to wait for the
pool to recover.

Another option would be to use usleep_range() with the exact amount
of time to wait for, the lower bound being the minimum number of
bytes asked for and the fifo size, the upper bound being the fifo
size.

	Arnd

Re: [PATCH v2 1/2] Input: bcm-keypad: add device tree bindings

[Dmitry Torokhov]

Hi Scott,

On Thu, Feb 26, 2015 at 08:08:48AM -0800, Scott Branden wrote:
> Documents the Broadcom keypad controller device tree bindings.
> 
> Reviewed-by: Ray Jui <rjui@broadcom.com>
> Signed-off-by: Scott Branden <sbranden@broadcom.com>
> ---
>  .../devicetree/bindings/input/brcm,bcm-keypad.txt  | 108 +++++++++++++++++++++
>  1 file changed, 108 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
> 
> diff --git a/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt b/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
> new file mode 100644
> index 0000000..e16bb2d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
> @@ -0,0 +1,108 @@
> +* Broadcom Keypad Controller device tree bindings
> +
> +Broadcom Keypad controller is used to interface a SoC with a matrix-type
> +keypad device. The keypad controller supports multiple row and column lines.
> +A key can be placed at each intersection of a unique row and a unique column.
> +The keypad controller can sense a key-press and key-release and report the
> +event using a interrupt to the cpu.
> +
> +This binding is based on the matrix-keymap binding with the following
> +changes:
> +
> +keypad,num-rows and keypad,num-columns are required.
> +
> +Required SoC Specific Properties:
> +- compatible: should be "brcm,bcm-keypad"
> +
> +- reg: physical base address of the controller and length of memory mapped
> +  region.
> +
> +- interrupts: The interrupt number to the cpu.
> +
> +Board Specific Properties:
> +- keypad,num-rows: Number of row lines connected to the keypad
> +  controller.
> +
> +- keypad,num-columns: Number of column lines connected to the
> +  keypad controller.
> +
> +- col-debounce-filter-period: The debounce period for the Column filter.
> +
> +	KEYPAD_DEBOUNCE_1_ms	=	0
> +	KEYPAD_DEBOUNCE_2_ms	=	1
> +	KEYPAD_DEBOUNCE_4_ms	=	2
> +	KEYPAD_DEBOUNCE_8_ms	=	3
> +	KEYPAD_DEBOUNCE_16_ms	=	4
> +	KEYPAD_DEBOUNCE_32_ms	=	5
> +	KEYPAD_DEBOUNCE_64_ms	=	6
> +	KEYPAD_DEBOUNCE_128_ms	=	7
> +
> +- status-debounce-filter-period: The debounce period for the Status filter.
> +
> +	KEYPAD_DEBOUNCE_1_ms	=	0
> +	KEYPAD_DEBOUNCE_2_ms	=	1
> +	KEYPAD_DEBOUNCE_4_ms	=	2
> +	KEYPAD_DEBOUNCE_8_ms	=	3
> +	KEYPAD_DEBOUNCE_16_ms	=	4
> +	KEYPAD_DEBOUNCE_32_ms	=	5
> +	KEYPAD_DEBOUNCE_64_ms	=	6
> +	KEYPAD_DEBOUNCE_128_ms	=	7
> +
> +- row-output-enabled: An optional property indicating whether the row or
> +  column is being used as output. If specified the row is being used
> +  as the output. Else defaults to column.
> +
> +- pull-up-enabled: An optional property indicating the Keypad scan mode.
> +  If specified implies the keypad scan pull-up has been enabled.
> +
> +- linux,keypad-no-autorepeat: An optional property indicating to
> +  not enable autorepeat feature.

Unfortunately we've accumulated a lot of bindings for turning autorepeat
on or off, I would prefer if we standardize on what gpio-keys is doing
and use "autorepeat" (no "linux,") for new drivers.

Thanks.

-- 
Dmitry

Re: [PATCH v2 2/2] Input: bcm-keypad: Add Broadcom keypad controller

[Dmitry Torokhov]

Hi Scott,

Mostly style nitpicks here...

On Thu, Feb 26, 2015 at 08:08:49AM -0800, Scott Branden wrote:
> Add driver for Broadcom's keypad controller.
> 
> Broadcom Keypad controller is used to interface a SoC with a matrix-type
> keypad device. The keypad controller supports multiple row and column lines.
> A key can be placed at each intersection of a unique row and a unique column.
> The keypad controller can sense a key-press and key-release and report the
> event using a interrupt to the cpu.
> 
> Reviewed-by: Ray Jui <rjui@broadcom.com>
> Signed-off-by: Scott Branden <sbranden@broadcom.com>
> ---
>  drivers/input/keyboard/Kconfig      |  10 +
>  drivers/input/keyboard/Makefile     |   1 +
>  drivers/input/keyboard/bcm-keypad.c | 464 ++++++++++++++++++++++++++++++++++++
>  3 files changed, 475 insertions(+)
>  create mode 100644 drivers/input/keyboard/bcm-keypad.c
> 
> diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
> index a5d9b3f..3a0c0f2 100644
> --- a/drivers/input/keyboard/Kconfig
> +++ b/drivers/input/keyboard/Kconfig
> @@ -676,4 +676,14 @@ config KEYBOARD_CAP11XX
>  	  To compile this driver as a module, choose M here: the
>  	  module will be called cap11xx.
>  
> +config KEYBOARD_BCM
> +	tristate "Broadcom keypad driver"
> +	select INPUT_MATRIXKMAP
> +	default ARCH_BCM_CYGNUS
> +	help
> +	  Say Y here if you want to use Broadcom keypad.
> +
> +	  To compile this driver as a module, choose M here: the
> +	  module will be called bcm-keypad.
> +
>  endif
> diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
> index febafa5..3cff8f6 100644
> --- a/drivers/input/keyboard/Makefile
> +++ b/drivers/input/keyboard/Makefile
> @@ -10,6 +10,7 @@ obj-$(CONFIG_KEYBOARD_ADP5589)		+= adp5589-keys.o
>  obj-$(CONFIG_KEYBOARD_AMIGA)		+= amikbd.o
>  obj-$(CONFIG_KEYBOARD_ATARI)		+= atakbd.o
>  obj-$(CONFIG_KEYBOARD_ATKBD)		+= atkbd.o
> +obj-$(CONFIG_KEYBOARD_BCM)		+= bcm-keypad.o
>  obj-$(CONFIG_KEYBOARD_BFIN)		+= bf54x-keys.o
>  obj-$(CONFIG_KEYBOARD_CAP11XX)		+= cap11xx.o
>  obj-$(CONFIG_KEYBOARD_CLPS711X)		+= clps711x-keypad.o
> diff --git a/drivers/input/keyboard/bcm-keypad.c b/drivers/input/keyboard/bcm-keypad.c
> new file mode 100644
> index 0000000..f229ac0
> --- /dev/null
> +++ b/drivers/input/keyboard/bcm-keypad.c
> @@ -0,0 +1,464 @@
> +/*
> + * Copyright (C) 2014 Broadcom Corporation
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/mm.h>
> +#include <linux/module.h>
> +#include <linux/input.h>
> +#include <linux/interrupt.h>
> +#include <linux/bitops.h>
> +#include <linux/platform_device.h>
> +#include <linux/delay.h>
> +#include <linux/sizes.h>
> +#include <linux/stddef.h>
> +#include <linux/of.h>
> +#include <linux/of_irq.h>
> +#include <linux/slab.h>
> +#include <linux/clk.h>
> +#include <linux/types.h>
> +#include <linux/string.h>
> +#include <asm/memory.h>
> +#include <linux/io.h>
> +#include <linux/input/matrix_keypad.h>
> +
> +#define DEFAULT_CLK_HZ                  31250
> +/* Repeat period (ms) */
> +#define KEY_REPEAT_PERIOD               100
> +/* First time press dly (ms) */
> +#define KEY_REPEAT_DELAY                400
> +#define MAX_ROWS                        8
> +#define MAX_COLS                        8
> +
> +/* Register/field definitions */
> +#define KPCR_OFFSET                          0x00000080
> +#define KPCR_MODE                       0x00000002
> +#define KPCR_MODE_SHIFT                 1
> +#define KPCR_MODE_MASK                  1
> +#define KPCR_ENABLE                     0x00000001
> +#define KPCR_STATUSFILTERENABLE         0x00008000
> +#define KPCR_STATUSFILTERTYPE_SHIFT          12
> +#define KPCR_COLFILTERENABLE            0x00000800
> +#define KPCR_COLFILTERTYPE_SHIFT             8
> +#define KPCR_ROWWIDTH_SHIFT                  20
> +#define KPCR_COLUMNWIDTH_SHIFT               16
> +
> +#define KPIOR_OFFSET                         0x00000084
> +#define KPIOR_ROWOCONTRL_SHIFT               24
> +#define KPIOR_ROWOCONTRL_MASK                0xFF000000
> +#define KPIOR_COLUMNOCONTRL_SHIFT            16
> +#define KPIOR_COLUMNOCONTRL_MASK             0x00FF0000
> +#define KPIOR_COLUMN_IO_DATA_SHIFT           0
> +
> +#define KPEMR0_OFFSET                        0x00000090
> +#define KPEMR1_OFFSET                        0x00000094
> +#define KPEMR2_OFFSET                        0x00000098
> +#define KPEMR3_OFFSET                        0x0000009C
> +#define KPEMR_EDGETYPE_BOTH 3
> +
> +#define KPSSR0_OFFSET                        0x000000A0
> +#define KPSSR1_OFFSET                        0x000000A4
> +#define KPSSRN_OFFSET(reg_n)                 (KPSSR0_OFFSET + (4 * reg_n))
> +#define KPIMR0_OFFSET                        0x000000B0
> +#define KPIMR1_OFFSET                        0x000000B4
> +#define KPICR0_OFFSET                        0x000000B8
> +#define KPICR1_OFFSET                        0x000000BC
> +#define KPICRN_OFFSET(reg_n)                 (KPICR0_OFFSET + (4 * reg_n))
> +#define KPISR0_OFFSET                        0x000000C0
> +#define KPISR1_OFFSET                        0x000000C4
> +
> +#define KPCR_STATUSFILTERTYPE_MAX 7
> +#define KPCR_COLFILTERTYPE_MAX 7
> +
> +/* Macros to determine the row/column from a bit that is set in SSR0/1. */
> +#define BIT_TO_ROW_SSRN(bit_nr, reg_n)  ((bit_nr >> 3) + (4 * reg_n))
> +#define BIT_TO_COL(bit_nr)       (bit_nr % 8)
> +
> +/* Structure representing various run-time entities */
> +struct bcm_kp {
> +	void __iomem *base;
> +	int irq;
> +	struct clk *clk;
> +	struct input_dev *input_dev;
> +	unsigned long last_state[2];
> +	unsigned int n_rows;
> +	unsigned int n_cols;
> +	u32 kpcr;
> +	u32 kpior;
> +	u32 kpemr;
> +	u32 imr0_val;
> +	u32 imr1_val;
> +};
> +
> +/*
> + * Returns the keycode from the input device keymap given the row and
> + * column.
> + */
> +static inline int bcm_kp_get_keycode(struct bcm_kp *kp, int row, int col)
> +{
> +	unsigned int row_shift = get_count_order(kp->n_cols);
> +	unsigned short *keymap = kp->input_dev->keycode;
> +
> +	return keymap[MATRIX_SCAN_CODE(row, col, row_shift)];
> +}
> +
> +static void bcm_kp_report_keys(struct bcm_kp *kp, int reg_num, int pull_mode)
> +{
> +	unsigned long state, change;
> +	int bit_nr;
> +	int key_press;
> +	int row, col;
> +	unsigned int keycode;
> +
> +	/* Clear interrupts */
> +	writel(0xFFFFFFFF, kp->base + KPICRN_OFFSET(reg_num));
> +
> +	state = readl(kp->base + KPSSRN_OFFSET(reg_num));
> +	change = kp->last_state[reg_num] ^ state;
> +	kp->last_state[reg_num] = state;
> +
> +	for_each_set_bit(bit_nr, &change, BITS_PER_LONG) {
> +		key_press = state & BIT(bit_nr);
> +		/* The meaning of SSR register depends on pull mode. */
> +		key_press = pull_mode ? !key_press : key_press;
> +		row = BIT_TO_ROW_SSRN(bit_nr, reg_num);
> +		col = BIT_TO_COL(bit_nr);
> +		keycode = bcm_kp_get_keycode(kp, row, col);
> +		input_report_key(kp->input_dev, keycode, key_press);
> +	}
> +}
> +
> +static irqreturn_t bcm_kp_isr_thread(int irq, void *dev_id)
> +{
> +	struct bcm_kp *kp = dev_id;
> +	int pull_mode = (kp->kpcr >> KPCR_MODE_SHIFT) & KPCR_MODE_MASK;
> +	int reg_num;
> +
> +	for (reg_num = 0; reg_num <= 1; reg_num++)
> +		bcm_kp_report_keys(kp, reg_num, pull_mode);
> +
> +	input_sync(kp->input_dev);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static int bcm_kp_start(struct bcm_kp *kp)
> +{
> +	int error;
> +
> +	error = clk_prepare_enable(kp->clk);
> +	if (error)
> +		return error;
> +
> +	writel(kp->kpior, kp->base + KPIOR_OFFSET);
> +
> +	writel(kp->imr0_val, kp->base + KPIMR0_OFFSET);
> +	writel(kp->imr1_val, kp->base + KPIMR1_OFFSET);
> +
> +	writel(kp->kpemr, kp->base + KPEMR0_OFFSET);
> +	writel(kp->kpemr, kp->base + KPEMR1_OFFSET);
> +	writel(kp->kpemr, kp->base + KPEMR2_OFFSET);
> +	writel(kp->kpemr, kp->base + KPEMR3_OFFSET);
> +
> +	writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET);
> +	writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET);
> +
> +	kp->last_state[0] = readl(kp->base + KPSSR0_OFFSET);
> +	kp->last_state[0] = readl(kp->base + KPSSR1_OFFSET);
> +
> +	writel(kp->kpcr | KPCR_ENABLE, kp->base + KPCR_OFFSET);
> +
> +	return 0;
> +}
> +
> +static void bcm_kp_stop(const struct bcm_kp *kp)
> +{
> +	u32 val;
> +
> +	val = readl(kp->base + KPCR_OFFSET);
> +	val &= ~KPCR_ENABLE;
> +	writel(0, kp->base + KPCR_OFFSET);
> +	writel(0, kp->base + KPIMR0_OFFSET);
> +	writel(0, kp->base + KPIMR1_OFFSET);
> +	writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET);
> +	writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET);
> +
> +	clk_disable_unprepare(kp->clk);
> +}
> +
> +static int bcm_kp_open(struct input_dev *dev)
> +{
> +	struct bcm_kp *kp = input_get_drvdata(dev);
> +
> +	return bcm_kp_start(kp);
> +}
> +
> +static void bcm_kp_close(struct input_dev *dev)
> +{
> +	struct bcm_kp *kp = input_get_drvdata(dev);
> +
> +	bcm_kp_stop(kp);
> +}
> +
> +static int bcm_kp_matrix_key_parse_dt(struct bcm_kp *kp)
> +{
> +	struct device *dev = kp->input_dev->dev.parent;
> +	struct device_node *np = dev->of_node;
> +	int error;
> +	unsigned int dt_val;
> +	unsigned int i;
> +
> +	/* Initialize the KPCR Keypad Configuration Register */
> +	kp->kpcr = KPCR_STATUSFILTERENABLE | KPCR_COLFILTERENABLE;
> +
> +	error = matrix_keypad_parse_of_params(dev, &kp->n_rows, &kp->n_cols);
> +	if (error) {
> +		dev_err(dev, "failed to parse kp params\n");
> +		return error;
> +	}
> +	/* Set row width for the ASIC block. */
> +	kp->kpcr |= (kp->n_rows - 1) << KPCR_ROWWIDTH_SHIFT;
> +
> +	/* Set column width for the ASIC block. */
> +	kp->kpcr |= (kp->n_cols - 1) << KPCR_COLUMNWIDTH_SHIFT;
> +
> +	/* Configure the IMR registers */
> +	{

Woudl prefer not having nested unnamed blocks in functions. If it
deserves a separate block it deserves its own function.

> +		unsigned int num_rows, col_mask, rows_set;
> +
> +		/* IMR registers contain interrupt enable bits for 8x8 matrix
> +		 * IMR0 register format: <row3> <row2> <row1> <row0>
> +		 * IMR1 register format: <row7> <row6> <row5> <row4>
> +		 */

Multi-line comments are in form

		/*
		 * Multi
		 * line
		 * comment
		 */

> +
> +		col_mask = (1 << (kp->n_cols)) - 1;
> +		num_rows = kp->n_rows;
> +
> +		/* Set column bits in rows 0 to 3 in IMR0 */
> +		kp->imr0_val = col_mask;
> +
> +		rows_set = 1;
> +		while ((--num_rows) && (rows_set++ < 4))
> +			kp->imr0_val |= (kp->imr0_val << MAX_COLS);
> +
> +		/* Set column bits in rows 4 to 7 in IMR1 */
> +		kp->imr1_val = 0;
> +		if (num_rows) {
> +			kp->imr1_val = col_mask;
> +			while (--num_rows)
> +				kp->imr1_val |= (kp->imr1_val << MAX_COLS);
> +		}
> +	}
> +
> +	/* Initialize the KPEMR Keypress Edge Mode Registers */
> +	/* Trigger on both edges */
> +	kp->kpemr = 0;
> +	for (i = 0; i <= 30; i = i + 2)
> +		kp->kpemr |= (KPEMR_EDGETYPE_BOTH << i);
> +
> +	/*
> +	 * Obtain the Status filter debounce value and verify against the
> +	 * possible values specified in the DT binding.
> +	 */
> +	of_property_read_u32(np, "status-debounce-filter-period",
> +		&dt_val);
> +	if (dt_val > KPCR_STATUSFILTERTYPE_MAX) {
> +		dev_err(dev, "Invalid Status filter debounce value %d\n",
> +			dt_val);
> +		return -EINVAL;
> +	}
> +	kp->kpcr |= dt_val << KPCR_STATUSFILTERTYPE_SHIFT;
> +
> +
> +	/*
> +	 * Obtain the Column filter debounce value and verify against the
> +	 * possible values specified in the DT binding.
> +	 */
> +	of_property_read_u32(np, "col-debounce-filter-period",
> +		&dt_val);
> +
> +	if (dt_val > KPCR_COLFILTERTYPE_MAX) {
> +		dev_err(dev, "Invalid Column filter debounce value %d\n",
> +			dt_val);
> +		return -EINVAL;
> +	}
> +	kp->kpcr |= dt_val << KPCR_COLFILTERTYPE_SHIFT;
> +
> +	/*
> +	 * Determine between the row and column,
> +	 * which should be configured as output.
> +	 */
> +	if (of_property_read_bool(np, "row-output-enabled")) {
> +		/*
> +		* Set RowOContrl or ColumnOContrl in KPIOR
> +		* to the number of pins to drive as outputs
> +		*/
> +		kp->kpior = (((1 << kp->n_rows) - 1) <<
> +				KPIOR_ROWOCONTRL_SHIFT);
> +	} else {
> +		kp->kpior = (((1 << kp->n_cols) - 1) <<
> +				KPIOR_COLUMNOCONTRL_SHIFT);
> +	}
> +
> +	/*
> +	 * Determine if the scan pull up needs to be enabled
> +	 */
> +	if (of_property_read_bool(np, "pull-up-enabled"))
> +		kp->kpcr |= KPCR_MODE;
> +
> +	dev_dbg(dev, "n_rows=%d n_col=%d kpcr=%x kpior=%x kpemr=%x\n",
> +		kp->n_rows, kp->n_cols,
> +		kp->kpcr, kp->kpior, kp->kpemr);
> +
> +	return 0;
> +}
> +
> +
> +static int bcm_kp_probe(struct platform_device *pdev)
> +{
> +	struct bcm_kp *kp;
> +	struct input_dev *input_dev;
> +	struct resource *res;
> +	int error;
> +	bool repeat;
> +
> +	kp = devm_kzalloc(&pdev->dev, sizeof(*kp),
> +				   GFP_KERNEL);
> +	if (!kp)
> +		return -ENOMEM;
> +
> +	input_dev = devm_input_allocate_device(&pdev->dev);
> +	if (!input_dev) {
> +		dev_err(&pdev->dev, "failed to allocate the input device\n");
> +		return -ENOMEM;
> +	}
> +
> +	__set_bit(EV_KEY, input_dev->evbit);
> +
> +	repeat = !of_property_read_bool(pdev->dev.of_node,
> +					"linux,input-no-autorepeat");
> +	if (repeat)
> +		__set_bit(EV_REP, input_dev->evbit);
> +
> +	input_dev->name = pdev->name;
> +	input_dev->phys = "keypad/input0";
> +	input_dev->dev.parent = &pdev->dev;
> +	input_dev->open = bcm_kp_open;
> +	input_dev->close = bcm_kp_close;
> +
> +	input_dev->id.bustype = BUS_HOST;
> +	input_dev->id.vendor = 0x0001;
> +	input_dev->id.product = 0x0001;
> +	input_dev->id.version = 0x0100;
> +
> +	input_set_drvdata(input_dev, kp);
> +
> +	kp->input_dev = input_dev;
> +
> +	platform_set_drvdata(pdev, kp);
> +
> +	error = bcm_kp_matrix_key_parse_dt(kp);
> +	if (error)
> +		return error;
> +
> +	error = matrix_keypad_build_keymap(NULL, NULL,
> +					   kp->n_rows,
> +					   kp->n_cols,
> +					   NULL, input_dev);
> +	if (error) {
> +		dev_err(&pdev->dev, "failed to build keymap\n");
> +		return error;
> +	}
> +
> +	/* Get the KEYPAD base address */
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!res) {
> +		dev_err(&pdev->dev, "Missing keypad base address resource\n");
> +		return -ENODEV;
> +	}
> +
> +	kp->base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(kp->base))
> +		return PTR_ERR(kp->base);
> +
> +	/* Enable clock */
> +
> +	kp->clk = devm_clk_get(&pdev->dev, "peri_clk");
> +	if (IS_ERR(kp->clk))
> +		dev_info(&pdev->dev,
> +			"No clock specified. Assuming it's enabled\n");

If one branch has curly braces all other have to have them too.

> +	else {
> +		unsigned int desired_rate;
> +		long actual_rate;
> +
> +		error = of_property_read_u32(pdev->dev.of_node,
> +				"clock-frequency", &desired_rate);
> +		if (error < 0)
> +			desired_rate = DEFAULT_CLK_HZ;
> +
> +		actual_rate = clk_round_rate(kp->clk, desired_rate);
> +		if (actual_rate <= 0)
> +			return -EINVAL;
> +
> +		error = clk_set_rate(kp->clk, actual_rate);
> +		if (error)
> +			return -EINVAL;
> +
> +		error = clk_prepare_enable(kp->clk);
> +		if (error)
> +			return -EINVAL;
> +	}
> +
> +	/* Put the kp into a known sane state */
> +	bcm_kp_stop(kp);
> +
> +	kp->irq = platform_get_irq(pdev, 0);
> +	if (kp->irq < 0) {
> +		dev_err(&pdev->dev, "no IRQ specified\n");
> +		return -EINVAL;
> +	}
> +
> +	error = devm_request_threaded_irq(&pdev->dev, kp->irq, NULL,
> +		bcm_kp_isr_thread,
> +		IRQF_ONESHOT, pdev->name, kp);
> +	if (error) {
> +		dev_err(&pdev->dev, "failed to request IRQ\n");
> +		return error;
> +	}
> +
> +	error = input_register_device(input_dev);
> +	if (error) {
> +		dev_err(&pdev->dev, "failed to register input device\n");
> +		return error;
> +	}
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id bcm_kp_of_match[] = {
> +	{ .compatible = "brcm,bcm-keypad" },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, bcm_kp_of_match);
> +
> +static struct platform_driver bcm_kp_device_driver = {
> +	.probe		= bcm_kp_probe,
> +	.driver		= {
> +		.name	= "bcm-keypad",
> +		.of_match_table = of_match_ptr(bcm_kp_of_match),
> +	}
> +};
> +
> +module_platform_driver(bcm_kp_device_driver);
> +
> +MODULE_AUTHOR("Broadcom Corporation");
> +MODULE_DESCRIPTION("BCM Keypad Driver");
> +MODULE_LICENSE("GPL");
> -- 
> 2.3.0
> 

Thanks!

-- 
Dmitry

Re: [PATCH v2 2/2] Input: bcm-keypad: Add Broadcom keypad controller

[Paul Bolle]

On Thu, 2015-02-26 at 08:08 -0800, Scott Branden wrote:
> Add driver for Broadcom's keypad controller.
> 
> Broadcom Keypad controller is used to interface a SoC with a matrix-type
> keypad device. The keypad controller supports multiple row and column lines.
> A key can be placed at each intersection of a unique row and a unique column.
> The keypad controller can sense a key-press and key-release and report the
> event using a interrupt to the cpu.
> 
> Reviewed-by: Ray Jui <rjui@broadcom.com>
> Signed-off-by: Scott Branden <sbranden@broadcom.com>
> ---
>  drivers/input/keyboard/Kconfig      |  10 +
>  drivers/input/keyboard/Makefile     |   1 +
>  drivers/input/keyboard/bcm-keypad.c | 464 ++++++++++++++++++++++++++++++++++++
>  3 files changed, 475 insertions(+)
>  create mode 100644 drivers/input/keyboard/bcm-keypad.c

License nit follows.

> diff --git a/drivers/input/keyboard/bcm-keypad.c b/drivers/input/keyboard/bcm-keypad.c
> new file mode 100644
> index 0000000..f229ac0
> --- /dev/null
> +++ b/drivers/input/keyboard/bcm-keypad.c
> @@ -0,0 +1,464 @@
> +/*
> + * Copyright (C) 2014 Broadcom Corporation
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.

This states that the license is GPL v2 only.

> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
> + * kind, whether express or implied; without even the implied warranty
> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */

[...]

> +MODULE_LICENSE("GPL");

So you probably want
    MODULE_LICENSE("GPL v2");


Paul Bolle

Re: [PATCH v2 2/2] Input: bcm-keypad: Add Broadcom keypad controller

[Scott Branden]

Yes, will correct.  Thanks.

On 15-02-28 06:16 AM, Paul Bolle wrote:
> On Thu, 2015-02-26 at 08:08 -0800, Scott Branden wrote:
>> Add driver for Broadcom's keypad controller.
>>
>> Broadcom Keypad controller is used to interface a SoC with a matrix-type
>> keypad device. The keypad controller supports multiple row and column lines.
>> A key can be placed at each intersection of a unique row and a unique column.
>> The keypad controller can sense a key-press and key-release and report the
>> event using a interrupt to the cpu.
>>
>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>> ---
>>   drivers/input/keyboard/Kconfig      |  10 +
>>   drivers/input/keyboard/Makefile     |   1 +
>>   drivers/input/keyboard/bcm-keypad.c | 464 ++++++++++++++++++++++++++++++++++++
>>   3 files changed, 475 insertions(+)
>>   create mode 100644 drivers/input/keyboard/bcm-keypad.c
>
> License nit follows.
>
>> diff --git a/drivers/input/keyboard/bcm-keypad.c b/drivers/input/keyboard/bcm-keypad.c
>> new file mode 100644
>> index 0000000..f229ac0
>> --- /dev/null
>> +++ b/drivers/input/keyboard/bcm-keypad.c
>> @@ -0,0 +1,464 @@
>> +/*
>> + * Copyright (C) 2014 Broadcom Corporation
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation version 2.
>
> This states that the license is GPL v2 only.
>
>> + *
>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> + * kind, whether express or implied; without even the implied warranty
>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>
> [...]
>
>> +MODULE_LICENSE("GPL");
>
> So you probably want
>      MODULE_LICENSE("GPL v2");
>
>
> Paul Bolle
>

Re: [PATCH v2 1/2] Input: bcm-keypad: add device tree bindings

[Scott Branden]

Hi Dmitry,

On 15-02-27 03:39 PM, Dmitry Torokhov wrote:
> Hi Scott,
>
> On Thu, Feb 26, 2015 at 08:08:48AM -0800, Scott Branden wrote:
>> Documents the Broadcom keypad controller device tree bindings.
>>
>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>> ---
>>   .../devicetree/bindings/input/brcm,bcm-keypad.txt  | 108 +++++++++++++++++++++
>>   1 file changed, 108 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
>>
>> diff --git a/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt b/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
>> new file mode 100644
>> index 0000000..e16bb2d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
>> @@ -0,0 +1,108 @@
>> +* Broadcom Keypad Controller device tree bindings
>> +
>> +Broadcom Keypad controller is used to interface a SoC with a matrix-type
>> +keypad device. The keypad controller supports multiple row and column lines.
>> +A key can be placed at each intersection of a unique row and a unique column.
>> +The keypad controller can sense a key-press and key-release and report the
>> +event using a interrupt to the cpu.
>> +
>> +This binding is based on the matrix-keymap binding with the following
>> +changes:
>> +
>> +keypad,num-rows and keypad,num-columns are required.
>> +
>> +Required SoC Specific Properties:
>> +- compatible: should be "brcm,bcm-keypad"
>> +
>> +- reg: physical base address of the controller and length of memory mapped
>> +  region.
>> +
>> +- interrupts: The interrupt number to the cpu.
>> +
>> +Board Specific Properties:
>> +- keypad,num-rows: Number of row lines connected to the keypad
>> +  controller.
>> +
>> +- keypad,num-columns: Number of column lines connected to the
>> +  keypad controller.
>> +
>> +- col-debounce-filter-period: The debounce period for the Column filter.
>> +
>> +	KEYPAD_DEBOUNCE_1_ms	=	0
>> +	KEYPAD_DEBOUNCE_2_ms	=	1
>> +	KEYPAD_DEBOUNCE_4_ms	=	2
>> +	KEYPAD_DEBOUNCE_8_ms	=	3
>> +	KEYPAD_DEBOUNCE_16_ms	=	4
>> +	KEYPAD_DEBOUNCE_32_ms	=	5
>> +	KEYPAD_DEBOUNCE_64_ms	=	6
>> +	KEYPAD_DEBOUNCE_128_ms	=	7
>> +
>> +- status-debounce-filter-period: The debounce period for the Status filter.
>> +
>> +	KEYPAD_DEBOUNCE_1_ms	=	0
>> +	KEYPAD_DEBOUNCE_2_ms	=	1
>> +	KEYPAD_DEBOUNCE_4_ms	=	2
>> +	KEYPAD_DEBOUNCE_8_ms	=	3
>> +	KEYPAD_DEBOUNCE_16_ms	=	4
>> +	KEYPAD_DEBOUNCE_32_ms	=	5
>> +	KEYPAD_DEBOUNCE_64_ms	=	6
>> +	KEYPAD_DEBOUNCE_128_ms	=	7
>> +
>> +- row-output-enabled: An optional property indicating whether the row or
>> +  column is being used as output. If specified the row is being used
>> +  as the output. Else defaults to column.
>> +
>> +- pull-up-enabled: An optional property indicating the Keypad scan mode.
>> +  If specified implies the keypad scan pull-up has been enabled.
>> +
>> +- linux,keypad-no-autorepeat: An optional property indicating to
>> +  not enable autorepeat feature.
>
> Unfortunately we've accumulated a lot of bindings for turning autorepeat
> on or off, I would prefer if we standardize on what gpio-keys is doing
> and use "autorepeat" (no "linux,") for new drivers.
OK. I can change it.
>
> Thanks.
>

Re: [PATCH v2 2/2] Input: bcm-keypad: Add Broadcom keypad controller

[Scott Branden]

On 15-02-27 03:44 PM, Dmitry Torokhov wrote:
> Hi Scott,
>
> Mostly style nitpicks here...
>
> On Thu, Feb 26, 2015 at 08:08:49AM -0800, Scott Branden wrote:
>> Add driver for Broadcom's keypad controller.
>>
>> Broadcom Keypad controller is used to interface a SoC with a matrix-type
>> keypad device. The keypad controller supports multiple row and column lines.
>> A key can be placed at each intersection of a unique row and a unique column.
>> The keypad controller can sense a key-press and key-release and report the
>> event using a interrupt to the cpu.
>>
>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>> ---
>>   drivers/input/keyboard/Kconfig      |  10 +
>>   drivers/input/keyboard/Makefile     |   1 +
>>   drivers/input/keyboard/bcm-keypad.c | 464 ++++++++++++++++++++++++++++++++++++
>>   3 files changed, 475 insertions(+)
>>   create mode 100644 drivers/input/keyboard/bcm-keypad.c
>>
>> diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
>> index a5d9b3f..3a0c0f2 100644
>> --- a/drivers/input/keyboard/Kconfig
>> +++ b/drivers/input/keyboard/Kconfig
>> @@ -676,4 +676,14 @@ config KEYBOARD_CAP11XX
>>   	  To compile this driver as a module, choose M here: the
>>   	  module will be called cap11xx.
>>
>> +config KEYBOARD_BCM
>> +	tristate "Broadcom keypad driver"
>> +	select INPUT_MATRIXKMAP
>> +	default ARCH_BCM_CYGNUS
>> +	help
>> +	  Say Y here if you want to use Broadcom keypad.
>> +
>> +	  To compile this driver as a module, choose M here: the
>> +	  module will be called bcm-keypad.
>> +
>>   endif
>> diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
>> index febafa5..3cff8f6 100644
>> --- a/drivers/input/keyboard/Makefile
>> +++ b/drivers/input/keyboard/Makefile
>> @@ -10,6 +10,7 @@ obj-$(CONFIG_KEYBOARD_ADP5589)		+= adp5589-keys.o
>>   obj-$(CONFIG_KEYBOARD_AMIGA)		+= amikbd.o
>>   obj-$(CONFIG_KEYBOARD_ATARI)		+= atakbd.o
>>   obj-$(CONFIG_KEYBOARD_ATKBD)		+= atkbd.o
>> +obj-$(CONFIG_KEYBOARD_BCM)		+= bcm-keypad.o
>>   obj-$(CONFIG_KEYBOARD_BFIN)		+= bf54x-keys.o
>>   obj-$(CONFIG_KEYBOARD_CAP11XX)		+= cap11xx.o
>>   obj-$(CONFIG_KEYBOARD_CLPS711X)		+= clps711x-keypad.o
>> diff --git a/drivers/input/keyboard/bcm-keypad.c b/drivers/input/keyboard/bcm-keypad.c
>> new file mode 100644
>> index 0000000..f229ac0
>> --- /dev/null
>> +++ b/drivers/input/keyboard/bcm-keypad.c
>> @@ -0,0 +1,464 @@
>> +/*
>> + * Copyright (C) 2014 Broadcom Corporation
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation version 2.
>> + *
>> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> + * kind, whether express or implied; without even the implied warranty
>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/mm.h>
>> +#include <linux/module.h>
>> +#include <linux/input.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/bitops.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/delay.h>
>> +#include <linux/sizes.h>
>> +#include <linux/stddef.h>
>> +#include <linux/of.h>
>> +#include <linux/of_irq.h>
>> +#include <linux/slab.h>
>> +#include <linux/clk.h>
>> +#include <linux/types.h>
>> +#include <linux/string.h>
>> +#include <asm/memory.h>
>> +#include <linux/io.h>
>> +#include <linux/input/matrix_keypad.h>
>> +
>> +#define DEFAULT_CLK_HZ                  31250
>> +/* Repeat period (ms) */
>> +#define KEY_REPEAT_PERIOD               100
>> +/* First time press dly (ms) */
>> +#define KEY_REPEAT_DELAY                400
>> +#define MAX_ROWS                        8
>> +#define MAX_COLS                        8
>> +
>> +/* Register/field definitions */
>> +#define KPCR_OFFSET                          0x00000080
>> +#define KPCR_MODE                       0x00000002
>> +#define KPCR_MODE_SHIFT                 1
>> +#define KPCR_MODE_MASK                  1
>> +#define KPCR_ENABLE                     0x00000001
>> +#define KPCR_STATUSFILTERENABLE         0x00008000
>> +#define KPCR_STATUSFILTERTYPE_SHIFT          12
>> +#define KPCR_COLFILTERENABLE            0x00000800
>> +#define KPCR_COLFILTERTYPE_SHIFT             8
>> +#define KPCR_ROWWIDTH_SHIFT                  20
>> +#define KPCR_COLUMNWIDTH_SHIFT               16
>> +
>> +#define KPIOR_OFFSET                         0x00000084
>> +#define KPIOR_ROWOCONTRL_SHIFT               24
>> +#define KPIOR_ROWOCONTRL_MASK                0xFF000000
>> +#define KPIOR_COLUMNOCONTRL_SHIFT            16
>> +#define KPIOR_COLUMNOCONTRL_MASK             0x00FF0000
>> +#define KPIOR_COLUMN_IO_DATA_SHIFT           0
>> +
>> +#define KPEMR0_OFFSET                        0x00000090
>> +#define KPEMR1_OFFSET                        0x00000094
>> +#define KPEMR2_OFFSET                        0x00000098
>> +#define KPEMR3_OFFSET                        0x0000009C
>> +#define KPEMR_EDGETYPE_BOTH 3
>> +
>> +#define KPSSR0_OFFSET                        0x000000A0
>> +#define KPSSR1_OFFSET                        0x000000A4
>> +#define KPSSRN_OFFSET(reg_n)                 (KPSSR0_OFFSET + (4 * reg_n))
>> +#define KPIMR0_OFFSET                        0x000000B0
>> +#define KPIMR1_OFFSET                        0x000000B4
>> +#define KPICR0_OFFSET                        0x000000B8
>> +#define KPICR1_OFFSET                        0x000000BC
>> +#define KPICRN_OFFSET(reg_n)                 (KPICR0_OFFSET + (4 * reg_n))
>> +#define KPISR0_OFFSET                        0x000000C0
>> +#define KPISR1_OFFSET                        0x000000C4
>> +
>> +#define KPCR_STATUSFILTERTYPE_MAX 7
>> +#define KPCR_COLFILTERTYPE_MAX 7
>> +
>> +/* Macros to determine the row/column from a bit that is set in SSR0/1. */
>> +#define BIT_TO_ROW_SSRN(bit_nr, reg_n)  ((bit_nr >> 3) + (4 * reg_n))
>> +#define BIT_TO_COL(bit_nr)       (bit_nr % 8)
>> +
>> +/* Structure representing various run-time entities */
>> +struct bcm_kp {
>> +	void __iomem *base;
>> +	int irq;
>> +	struct clk *clk;
>> +	struct input_dev *input_dev;
>> +	unsigned long last_state[2];
>> +	unsigned int n_rows;
>> +	unsigned int n_cols;
>> +	u32 kpcr;
>> +	u32 kpior;
>> +	u32 kpemr;
>> +	u32 imr0_val;
>> +	u32 imr1_val;
>> +};
>> +
>> +/*
>> + * Returns the keycode from the input device keymap given the row and
>> + * column.
>> + */
>> +static inline int bcm_kp_get_keycode(struct bcm_kp *kp, int row, int col)
>> +{
>> +	unsigned int row_shift = get_count_order(kp->n_cols);
>> +	unsigned short *keymap = kp->input_dev->keycode;
>> +
>> +	return keymap[MATRIX_SCAN_CODE(row, col, row_shift)];
>> +}
>> +
>> +static void bcm_kp_report_keys(struct bcm_kp *kp, int reg_num, int pull_mode)
>> +{
>> +	unsigned long state, change;
>> +	int bit_nr;
>> +	int key_press;
>> +	int row, col;
>> +	unsigned int keycode;
>> +
>> +	/* Clear interrupts */
>> +	writel(0xFFFFFFFF, kp->base + KPICRN_OFFSET(reg_num));
>> +
>> +	state = readl(kp->base + KPSSRN_OFFSET(reg_num));
>> +	change = kp->last_state[reg_num] ^ state;
>> +	kp->last_state[reg_num] = state;
>> +
>> +	for_each_set_bit(bit_nr, &change, BITS_PER_LONG) {
>> +		key_press = state & BIT(bit_nr);
>> +		/* The meaning of SSR register depends on pull mode. */
>> +		key_press = pull_mode ? !key_press : key_press;
>> +		row = BIT_TO_ROW_SSRN(bit_nr, reg_num);
>> +		col = BIT_TO_COL(bit_nr);
>> +		keycode = bcm_kp_get_keycode(kp, row, col);
>> +		input_report_key(kp->input_dev, keycode, key_press);
>> +	}
>> +}
>> +
>> +static irqreturn_t bcm_kp_isr_thread(int irq, void *dev_id)
>> +{
>> +	struct bcm_kp *kp = dev_id;
>> +	int pull_mode = (kp->kpcr >> KPCR_MODE_SHIFT) & KPCR_MODE_MASK;
>> +	int reg_num;
>> +
>> +	for (reg_num = 0; reg_num <= 1; reg_num++)
>> +		bcm_kp_report_keys(kp, reg_num, pull_mode);
>> +
>> +	input_sync(kp->input_dev);
>> +
>> +	return IRQ_HANDLED;
>> +}
>> +
>> +static int bcm_kp_start(struct bcm_kp *kp)
>> +{
>> +	int error;
>> +
>> +	error = clk_prepare_enable(kp->clk);
>> +	if (error)
>> +		return error;
>> +
>> +	writel(kp->kpior, kp->base + KPIOR_OFFSET);
>> +
>> +	writel(kp->imr0_val, kp->base + KPIMR0_OFFSET);
>> +	writel(kp->imr1_val, kp->base + KPIMR1_OFFSET);
>> +
>> +	writel(kp->kpemr, kp->base + KPEMR0_OFFSET);
>> +	writel(kp->kpemr, kp->base + KPEMR1_OFFSET);
>> +	writel(kp->kpemr, kp->base + KPEMR2_OFFSET);
>> +	writel(kp->kpemr, kp->base + KPEMR3_OFFSET);
>> +
>> +	writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET);
>> +	writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET);
>> +
>> +	kp->last_state[0] = readl(kp->base + KPSSR0_OFFSET);
>> +	kp->last_state[0] = readl(kp->base + KPSSR1_OFFSET);
>> +
>> +	writel(kp->kpcr | KPCR_ENABLE, kp->base + KPCR_OFFSET);
>> +
>> +	return 0;
>> +}
>> +
>> +static void bcm_kp_stop(const struct bcm_kp *kp)
>> +{
>> +	u32 val;
>> +
>> +	val = readl(kp->base + KPCR_OFFSET);
>> +	val &= ~KPCR_ENABLE;
>> +	writel(0, kp->base + KPCR_OFFSET);
>> +	writel(0, kp->base + KPIMR0_OFFSET);
>> +	writel(0, kp->base + KPIMR1_OFFSET);
>> +	writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET);
>> +	writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET);
>> +
>> +	clk_disable_unprepare(kp->clk);
>> +}
>> +
>> +static int bcm_kp_open(struct input_dev *dev)
>> +{
>> +	struct bcm_kp *kp = input_get_drvdata(dev);
>> +
>> +	return bcm_kp_start(kp);
>> +}
>> +
>> +static void bcm_kp_close(struct input_dev *dev)
>> +{
>> +	struct bcm_kp *kp = input_get_drvdata(dev);
>> +
>> +	bcm_kp_stop(kp);
>> +}
>> +
>> +static int bcm_kp_matrix_key_parse_dt(struct bcm_kp *kp)
>> +{
>> +	struct device *dev = kp->input_dev->dev.parent;
>> +	struct device_node *np = dev->of_node;
>> +	int error;
>> +	unsigned int dt_val;
>> +	unsigned int i;
>> +
>> +	/* Initialize the KPCR Keypad Configuration Register */
>> +	kp->kpcr = KPCR_STATUSFILTERENABLE | KPCR_COLFILTERENABLE;
>> +
>> +	error = matrix_keypad_parse_of_params(dev, &kp->n_rows, &kp->n_cols);
>> +	if (error) {
>> +		dev_err(dev, "failed to parse kp params\n");
>> +		return error;
>> +	}
>> +	/* Set row width for the ASIC block. */
>> +	kp->kpcr |= (kp->n_rows - 1) << KPCR_ROWWIDTH_SHIFT;
>> +
>> +	/* Set column width for the ASIC block. */
>> +	kp->kpcr |= (kp->n_cols - 1) << KPCR_COLUMNWIDTH_SHIFT;
>> +
>> +	/* Configure the IMR registers */
>> +	{
>
> Woudl prefer not having nested unnamed blocks in functions. If it
> deserves a separate block it deserves its own function.
removed {
>
>> +		unsigned int num_rows, col_mask, rows_set;
>> +
>> +		/* IMR registers contain interrupt enable bits for 8x8 matrix
>> +		 * IMR0 register format: <row3> <row2> <row1> <row0>
>> +		 * IMR1 register format: <row7> <row6> <row5> <row4>
>> +		 */
>
> Multi-line comments are in form
>
> 		/*
> 		 * Multi
> 		 * line
> 		 * comment
> 		 */
>
fixed

>> +
>> +		col_mask = (1 << (kp->n_cols)) - 1;
>> +		num_rows = kp->n_rows;
>> +
>> +		/* Set column bits in rows 0 to 3 in IMR0 */
>> +		kp->imr0_val = col_mask;
>> +
>> +		rows_set = 1;
>> +		while ((--num_rows) && (rows_set++ < 4))
>> +			kp->imr0_val |= (kp->imr0_val << MAX_COLS);
>> +
>> +		/* Set column bits in rows 4 to 7 in IMR1 */
>> +		kp->imr1_val = 0;
>> +		if (num_rows) {
>> +			kp->imr1_val = col_mask;
>> +			while (--num_rows)
>> +				kp->imr1_val |= (kp->imr1_val << MAX_COLS);
>> +		}
>> +	}
>> +
>> +	/* Initialize the KPEMR Keypress Edge Mode Registers */
>> +	/* Trigger on both edges */
>> +	kp->kpemr = 0;
>> +	for (i = 0; i <= 30; i = i + 2)
>> +		kp->kpemr |= (KPEMR_EDGETYPE_BOTH << i);
>> +
>> +	/*
>> +	 * Obtain the Status filter debounce value and verify against the
>> +	 * possible values specified in the DT binding.
>> +	 */
>> +	of_property_read_u32(np, "status-debounce-filter-period",
>> +		&dt_val);
>> +	if (dt_val > KPCR_STATUSFILTERTYPE_MAX) {
>> +		dev_err(dev, "Invalid Status filter debounce value %d\n",
>> +			dt_val);
>> +		return -EINVAL;
>> +	}
>> +	kp->kpcr |= dt_val << KPCR_STATUSFILTERTYPE_SHIFT;
>> +
>> +
>> +	/*
>> +	 * Obtain the Column filter debounce value and verify against the
>> +	 * possible values specified in the DT binding.
>> +	 */
>> +	of_property_read_u32(np, "col-debounce-filter-period",
>> +		&dt_val);
>> +
>> +	if (dt_val > KPCR_COLFILTERTYPE_MAX) {
>> +		dev_err(dev, "Invalid Column filter debounce value %d\n",
>> +			dt_val);
>> +		return -EINVAL;
>> +	}
>> +	kp->kpcr |= dt_val << KPCR_COLFILTERTYPE_SHIFT;
>> +
>> +	/*
>> +	 * Determine between the row and column,
>> +	 * which should be configured as output.
>> +	 */
>> +	if (of_property_read_bool(np, "row-output-enabled")) {
>> +		/*
>> +		* Set RowOContrl or ColumnOContrl in KPIOR
>> +		* to the number of pins to drive as outputs
>> +		*/
>> +		kp->kpior = (((1 << kp->n_rows) - 1) <<
>> +				KPIOR_ROWOCONTRL_SHIFT);
>> +	} else {
>> +		kp->kpior = (((1 << kp->n_cols) - 1) <<
>> +				KPIOR_COLUMNOCONTRL_SHIFT);
>> +	}
>> +
>> +	/*
>> +	 * Determine if the scan pull up needs to be enabled
>> +	 */
>> +	if (of_property_read_bool(np, "pull-up-enabled"))
>> +		kp->kpcr |= KPCR_MODE;
>> +
>> +	dev_dbg(dev, "n_rows=%d n_col=%d kpcr=%x kpior=%x kpemr=%x\n",
>> +		kp->n_rows, kp->n_cols,
>> +		kp->kpcr, kp->kpior, kp->kpemr);
>> +
>> +	return 0;
>> +}
>> +
>> +
>> +static int bcm_kp_probe(struct platform_device *pdev)
>> +{
>> +	struct bcm_kp *kp;
>> +	struct input_dev *input_dev;
>> +	struct resource *res;
>> +	int error;
>> +	bool repeat;
>> +
>> +	kp = devm_kzalloc(&pdev->dev, sizeof(*kp),
>> +				   GFP_KERNEL);
>> +	if (!kp)
>> +		return -ENOMEM;
>> +
>> +	input_dev = devm_input_allocate_device(&pdev->dev);
>> +	if (!input_dev) {
>> +		dev_err(&pdev->dev, "failed to allocate the input device\n");
>> +		return -ENOMEM;
>> +	}
>> +
>> +	__set_bit(EV_KEY, input_dev->evbit);
>> +
>> +	repeat = !of_property_read_bool(pdev->dev.of_node,
>> +					"linux,input-no-autorepeat");
>> +	if (repeat)
>> +		__set_bit(EV_REP, input_dev->evbit);
>> +
>> +	input_dev->name = pdev->name;
>> +	input_dev->phys = "keypad/input0";
>> +	input_dev->dev.parent = &pdev->dev;
>> +	input_dev->open = bcm_kp_open;
>> +	input_dev->close = bcm_kp_close;
>> +
>> +	input_dev->id.bustype = BUS_HOST;
>> +	input_dev->id.vendor = 0x0001;
>> +	input_dev->id.product = 0x0001;
>> +	input_dev->id.version = 0x0100;
>> +
>> +	input_set_drvdata(input_dev, kp);
>> +
>> +	kp->input_dev = input_dev;
>> +
>> +	platform_set_drvdata(pdev, kp);
>> +
>> +	error = bcm_kp_matrix_key_parse_dt(kp);
>> +	if (error)
>> +		return error;
>> +
>> +	error = matrix_keypad_build_keymap(NULL, NULL,
>> +					   kp->n_rows,
>> +					   kp->n_cols,
>> +					   NULL, input_dev);
>> +	if (error) {
>> +		dev_err(&pdev->dev, "failed to build keymap\n");
>> +		return error;
>> +	}
>> +
>> +	/* Get the KEYPAD base address */
>> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +	if (!res) {
>> +		dev_err(&pdev->dev, "Missing keypad base address resource\n");
>> +		return -ENODEV;
>> +	}
>> +
>> +	kp->base = devm_ioremap_resource(&pdev->dev, res);
>> +	if (IS_ERR(kp->base))
>> +		return PTR_ERR(kp->base);
>> +
>> +	/* Enable clock */
>> +
>> +	kp->clk = devm_clk_get(&pdev->dev, "peri_clk");
>> +	if (IS_ERR(kp->clk))
>> +		dev_info(&pdev->dev,
>> +			"No clock specified. Assuming it's enabled\n");
>
> If one branch has curly braces all other have to have them too.
>
ok.  would be nice for checkpatch to deal with such K&R concerns.
>> +	else {
>> +		unsigned int desired_rate;
>> +		long actual_rate;
>> +
>> +		error = of_property_read_u32(pdev->dev.of_node,
>> +				"clock-frequency", &desired_rate);
>> +		if (error < 0)
>> +			desired_rate = DEFAULT_CLK_HZ;
>> +
>> +		actual_rate = clk_round_rate(kp->clk, desired_rate);
>> +		if (actual_rate <= 0)
>> +			return -EINVAL;
>> +
>> +		error = clk_set_rate(kp->clk, actual_rate);
>> +		if (error)
>> +			return -EINVAL;
>> +
>> +		error = clk_prepare_enable(kp->clk);
>> +		if (error)
>> +			return -EINVAL;
>> +	}
>> +
>> +	/* Put the kp into a known sane state */
>> +	bcm_kp_stop(kp);
>> +
>> +	kp->irq = platform_get_irq(pdev, 0);
>> +	if (kp->irq < 0) {
>> +		dev_err(&pdev->dev, "no IRQ specified\n");
>> +		return -EINVAL;
>> +	}
>> +
>> +	error = devm_request_threaded_irq(&pdev->dev, kp->irq, NULL,
>> +		bcm_kp_isr_thread,
>> +		IRQF_ONESHOT, pdev->name, kp);
>> +	if (error) {
>> +		dev_err(&pdev->dev, "failed to request IRQ\n");
>> +		return error;
>> +	}
>> +
>> +	error = input_register_device(input_dev);
>> +	if (error) {
>> +		dev_err(&pdev->dev, "failed to register input device\n");
>> +		return error;
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +static const struct of_device_id bcm_kp_of_match[] = {
>> +	{ .compatible = "brcm,bcm-keypad" },
>> +	{ },
>> +};
>> +MODULE_DEVICE_TABLE(of, bcm_kp_of_match);
>> +
>> +static struct platform_driver bcm_kp_device_driver = {
>> +	.probe		= bcm_kp_probe,
>> +	.driver		= {
>> +		.name	= "bcm-keypad",
>> +		.of_match_table = of_match_ptr(bcm_kp_of_match),
>> +	}
>> +};
>> +
>> +module_platform_driver(bcm_kp_device_driver);
>> +
>> +MODULE_AUTHOR("Broadcom Corporation");
>> +MODULE_DESCRIPTION("BCM Keypad Driver");
>> +MODULE_LICENSE("GPL");
>> --
>> 2.3.0
>>
>
> Thanks!
>

Re: [PATCH v2 2/2] hwrng: iproc-rng200 - Add Broadcom IPROC RNG driver

[Scott Branden]

On 15-02-27 01:14 AM, Arnd Bergmann wrote:
> On Thursday 26 February 2015 14:26:02 Scott Branden wrote:
>> On 15-02-26 12:15 PM, Arnd Bergmann wrote:
>>>> On 15-02-25 11:17 AM, Arnd Bergmann wrote:
>>>>> On Wednesday 25 February 2015 10:16:24 Scott Branden wrote:
>>>> This code was following examples of other open source drivers - bcm2835
>>>> and exynos both use cpu_relax.  I'll have to look into this more to
>>>> understand.
>>>>
>>>
>>> The majority of the driver apparently use udelay(10) to wait, which is
>>> not much better but at least consistent. The cpu_relax() call probably
>>> gives better throughput.
>>>
>>> I don't understand why none of the drivers actually attempts to
>>> msleep(), but that may be because the delay is much too long.
>>>
>>> Can you find out what the expected latency is for new data to
>>> become available on your hardware?
>> RNG generates at a nominal 1 Mbps.  So to generate 32 bits of data takes
>> approximately 32 us.
>
> The udelay(10) that the other drivers have seems about appropriate then,
> and we can independently think of a way to refine the interface.
> Please add a comment that explains the rate. Also, is there some kind
> of FIFO present in the hwrng device? If it can store close to 1ms work
> of data (1000 bits), you can just use an msleep(1) to wait for the
> pool to recover.
FIFO is 512 bits.  I will look as to whether we can live with 1/2 
throughput.
>
> Another option would be to use usleep_range() with the exact amount
> of time to wait for, the lower bound being the minimum number of
> bytes asked for and the fifo size, the upper bound being the fifo
> size.
>
> 	Arnd
>

[PATCH v3 0/2] Add support for Broadcom keypad controller

[Scott Branden]

This series of patchsets contains the Broadcom keypad controller driver
and device tree binding documentation.

Changes from v2:
- changed binding to use autorepeat
- stylistic updates

Changes from v1:
- updated dt documentation to remove to matrix-keymap.txt
- removed bcm_kp_remove as it is not necessary
- removed key-interrupt-trigger-type dt binding
- added bcm_kp_report_keys and call to process key registers

Scott Branden (2):
  Input: bcm-keypad: add device tree bindings
  Input: bcm-keypad: Add Broadcom keypad controller

 .../devicetree/bindings/input/brcm,bcm-keypad.txt  | 108 +++++
 drivers/input/keyboard/Kconfig                     |  10 +
 drivers/input/keyboard/Makefile                    |   1 +
 drivers/input/keyboard/bcm-keypad.c                | 463 +++++++++++++++++++++
 4 files changed, 582 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
 create mode 100644 drivers/input/keyboard/bcm-keypad.c

-- 
2.3.0

[PATCH v3 1/2] Input: bcm-keypad: add device tree bindings

[Scott Branden]

Documents the Broadcom keypad controller device tree bindings.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 .../devicetree/bindings/input/brcm,bcm-keypad.txt  | 108 +++++++++++++++++++++
 1 file changed, 108 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt

diff --git a/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt b/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
new file mode 100644
index 0000000..b77f50b
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
@@ -0,0 +1,108 @@
+* Broadcom Keypad Controller device tree bindings
+
+Broadcom Keypad controller is used to interface a SoC with a matrix-type
+keypad device. The keypad controller supports multiple row and column lines.
+A key can be placed at each intersection of a unique row and a unique column.
+The keypad controller can sense a key-press and key-release and report the
+event using a interrupt to the cpu.
+
+This binding is based on the matrix-keymap binding with the following
+changes:
+
+keypad,num-rows and keypad,num-columns are required.
+
+Required SoC Specific Properties:
+- compatible: should be "brcm,bcm-keypad"
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- interrupts: The interrupt number to the cpu.
+
+Board Specific Properties:
+- keypad,num-rows: Number of row lines connected to the keypad
+  controller.
+
+- keypad,num-columns: Number of column lines connected to the
+  keypad controller.
+
+- col-debounce-filter-period: The debounce period for the Column filter.
+
+	KEYPAD_DEBOUNCE_1_ms	=	0
+	KEYPAD_DEBOUNCE_2_ms	=	1
+	KEYPAD_DEBOUNCE_4_ms	=	2
+	KEYPAD_DEBOUNCE_8_ms	=	3
+	KEYPAD_DEBOUNCE_16_ms	=	4
+	KEYPAD_DEBOUNCE_32_ms	=	5
+	KEYPAD_DEBOUNCE_64_ms	=	6
+	KEYPAD_DEBOUNCE_128_ms	=	7
+
+- status-debounce-filter-period: The debounce period for the Status filter.
+
+	KEYPAD_DEBOUNCE_1_ms	=	0
+	KEYPAD_DEBOUNCE_2_ms	=	1
+	KEYPAD_DEBOUNCE_4_ms	=	2
+	KEYPAD_DEBOUNCE_8_ms	=	3
+	KEYPAD_DEBOUNCE_16_ms	=	4
+	KEYPAD_DEBOUNCE_32_ms	=	5
+	KEYPAD_DEBOUNCE_64_ms	=	6
+	KEYPAD_DEBOUNCE_128_ms	=	7
+
+- row-output-enabled: An optional property indicating whether the row or
+  column is being used as output. If specified the row is being used
+  as the output. Else defaults to column.
+
+- pull-up-enabled: An optional property indicating the Keypad scan mode.
+  If specified implies the keypad scan pull-up has been enabled.
+
+- autorepeat: Boolean, Enable auto repeat feature of Linux input
+	  subsystem (optional).
+
+- linux,keymap: The keymap for keys as described in the binding document
+  devicetree/bindings/input/matrix-keymap.txt.
+
+Example:
+#include "dt-bindings/input/input.h"
+
+/ {
+	keypad: keypad@180ac000 {
+		/* Required SoC specific properties */
+		compatible = "brcm,bcm-keypad";
+
+		/* Required Board specific properties */
+		keypad,num-rows = <5>;
+		keypad,num-columns = <5>;
+		status = "okay";
+
+		linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_F) /* key_forward */
+		MATRIX_KEY(0x00, 0x03, KEY_HOME) /* key_home */
+		MATRIX_KEY(0x00, 0x04, KEY_M) /* key_message */
+		MATRIX_KEY(0x01, 0x00, KEY_A) /* key_contacts */
+		MATRIX_KEY(0x01, 0x01, KEY_1) /* key_1 */
+		MATRIX_KEY(0x01, 0x02, KEY_2) /* key_2 */
+		MATRIX_KEY(0x01, 0x03, KEY_3) /* key_3 */
+		MATRIX_KEY(0x01, 0x04, KEY_S) /* key_speaker */
+		MATRIX_KEY(0x02, 0x00, KEY_P) /* key_phone */
+		MATRIX_KEY(0x02, 0x01, KEY_4) /* key_4 */
+		MATRIX_KEY(0x02, 0x02, KEY_5) /* key_5 */
+		MATRIX_KEY(0x02, 0x03, KEY_6) /* key_6 */
+		MATRIX_KEY(0x02, 0x04, KEY_VOLUMEUP) /* key_vol_up */
+		MATRIX_KEY(0x03, 0x00, KEY_C) /* key_call_log */
+		MATRIX_KEY(0x03, 0x01, KEY_7) /* key_7 */
+		MATRIX_KEY(0x03, 0x02, KEY_8) /* key_8 */
+		MATRIX_KEY(0x03, 0x03, KEY_9) /* key_9 */
+		MATRIX_KEY(0x03, 0x04, KEY_VOLUMEDOWN) /* key_vol_down */
+		MATRIX_KEY(0x04, 0x00, KEY_H) /* key_headset */
+		MATRIX_KEY(0x04, 0x01, KEY_KPASTERISK) /* key_* */
+		MATRIX_KEY(0x04, 0x02, KEY_0) /* key_0 */
+		MATRIX_KEY(0x04, 0x03, KEY_GRAVE) /* key_# */
+		MATRIX_KEY(0x04, 0x04, KEY_MUTE) /* key_mute */
+		>;
+
+		/* Optional board specific properties */
+		col-debounce-filter-period = <5>;
+		row-output-enabled;
+		pull-up-enabled;
+
+	};
+};
-- 
2.3.0

[PATCH v3 2/2] Input: bcm-keypad: Add Broadcom keypad controller

[Scott Branden]

Add driver for Broadcom's keypad controller.

Broadcom Keypad controller is used to interface a SoC with a matrix-type
keypad device. The keypad controller supports multiple row and column lines.
A key can be placed at each intersection of a unique row and a unique column.
The keypad controller can sense a key-press and key-release and report the
event using a interrupt to the cpu.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/input/keyboard/Kconfig      |  10 +
 drivers/input/keyboard/Makefile     |   1 +
 drivers/input/keyboard/bcm-keypad.c | 463 ++++++++++++++++++++++++++++++++++++
 3 files changed, 474 insertions(+)
 create mode 100644 drivers/input/keyboard/bcm-keypad.c

diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index a5d9b3f..3a0c0f2 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -676,4 +676,14 @@ config KEYBOARD_CAP11XX
 	  To compile this driver as a module, choose M here: the
 	  module will be called cap11xx.
 
+config KEYBOARD_BCM
+	tristate "Broadcom keypad driver"
+	select INPUT_MATRIXKMAP
+	default ARCH_BCM_CYGNUS
+	help
+	  Say Y here if you want to use Broadcom keypad.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called bcm-keypad.
+
 endif
diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
index febafa5..3cff8f6 100644
--- a/drivers/input/keyboard/Makefile
+++ b/drivers/input/keyboard/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_KEYBOARD_ADP5589)		+= adp5589-keys.o
 obj-$(CONFIG_KEYBOARD_AMIGA)		+= amikbd.o
 obj-$(CONFIG_KEYBOARD_ATARI)		+= atakbd.o
 obj-$(CONFIG_KEYBOARD_ATKBD)		+= atkbd.o
+obj-$(CONFIG_KEYBOARD_BCM)		+= bcm-keypad.o
 obj-$(CONFIG_KEYBOARD_BFIN)		+= bf54x-keys.o
 obj-$(CONFIG_KEYBOARD_CAP11XX)		+= cap11xx.o
 obj-$(CONFIG_KEYBOARD_CLPS711X)		+= clps711x-keypad.o
diff --git a/drivers/input/keyboard/bcm-keypad.c b/drivers/input/keyboard/bcm-keypad.c
new file mode 100644
index 0000000..8ef8add
--- /dev/null
+++ b/drivers/input/keyboard/bcm-keypad.c
@@ -0,0 +1,463 @@
+/*
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/bitops.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/sizes.h>
+#include <linux/stddef.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <asm/memory.h>
+#include <linux/io.h>
+#include <linux/input/matrix_keypad.h>
+
+#define DEFAULT_CLK_HZ                  31250
+/* Repeat period (ms) */
+#define KEY_REPEAT_PERIOD               100
+/* First time press dly (ms) */
+#define KEY_REPEAT_DELAY                400
+#define MAX_ROWS                        8
+#define MAX_COLS                        8
+
+/* Register/field definitions */
+#define KPCR_OFFSET                          0x00000080
+#define KPCR_MODE                       0x00000002
+#define KPCR_MODE_SHIFT                 1
+#define KPCR_MODE_MASK                  1
+#define KPCR_ENABLE                     0x00000001
+#define KPCR_STATUSFILTERENABLE         0x00008000
+#define KPCR_STATUSFILTERTYPE_SHIFT          12
+#define KPCR_COLFILTERENABLE            0x00000800
+#define KPCR_COLFILTERTYPE_SHIFT             8
+#define KPCR_ROWWIDTH_SHIFT                  20
+#define KPCR_COLUMNWIDTH_SHIFT               16
+
+#define KPIOR_OFFSET                         0x00000084
+#define KPIOR_ROWOCONTRL_SHIFT               24
+#define KPIOR_ROWOCONTRL_MASK                0xFF000000
+#define KPIOR_COLUMNOCONTRL_SHIFT            16
+#define KPIOR_COLUMNOCONTRL_MASK             0x00FF0000
+#define KPIOR_COLUMN_IO_DATA_SHIFT           0
+
+#define KPEMR0_OFFSET                        0x00000090
+#define KPEMR1_OFFSET                        0x00000094
+#define KPEMR2_OFFSET                        0x00000098
+#define KPEMR3_OFFSET                        0x0000009C
+#define KPEMR_EDGETYPE_BOTH 3
+
+#define KPSSR0_OFFSET                        0x000000A0
+#define KPSSR1_OFFSET                        0x000000A4
+#define KPSSRN_OFFSET(reg_n)                 (KPSSR0_OFFSET + (4 * reg_n))
+#define KPIMR0_OFFSET                        0x000000B0
+#define KPIMR1_OFFSET                        0x000000B4
+#define KPICR0_OFFSET                        0x000000B8
+#define KPICR1_OFFSET                        0x000000BC
+#define KPICRN_OFFSET(reg_n)                 (KPICR0_OFFSET + (4 * reg_n))
+#define KPISR0_OFFSET                        0x000000C0
+#define KPISR1_OFFSET                        0x000000C4
+
+#define KPCR_STATUSFILTERTYPE_MAX 7
+#define KPCR_COLFILTERTYPE_MAX 7
+
+/* Macros to determine the row/column from a bit that is set in SSR0/1. */
+#define BIT_TO_ROW_SSRN(bit_nr, reg_n)  ((bit_nr >> 3) + (4 * reg_n))
+#define BIT_TO_COL(bit_nr)       (bit_nr % 8)
+
+/* Structure representing various run-time entities */
+struct bcm_kp {
+	void __iomem *base;
+	int irq;
+	struct clk *clk;
+	struct input_dev *input_dev;
+	unsigned long last_state[2];
+	unsigned int n_rows;
+	unsigned int n_cols;
+	u32 kpcr;
+	u32 kpior;
+	u32 kpemr;
+	u32 imr0_val;
+	u32 imr1_val;
+};
+
+/*
+ * Returns the keycode from the input device keymap given the row and
+ * column.
+ */
+static inline int bcm_kp_get_keycode(struct bcm_kp *kp, int row, int col)
+{
+	unsigned int row_shift = get_count_order(kp->n_cols);
+	unsigned short *keymap = kp->input_dev->keycode;
+
+	return keymap[MATRIX_SCAN_CODE(row, col, row_shift)];
+}
+
+static void bcm_kp_report_keys(struct bcm_kp *kp, int reg_num, int pull_mode)
+{
+	unsigned long state, change;
+	int bit_nr;
+	int key_press;
+	int row, col;
+	unsigned int keycode;
+
+	/* Clear interrupts */
+	writel(0xFFFFFFFF, kp->base + KPICRN_OFFSET(reg_num));
+
+	state = readl(kp->base + KPSSRN_OFFSET(reg_num));
+	change = kp->last_state[reg_num] ^ state;
+	kp->last_state[reg_num] = state;
+
+	for_each_set_bit(bit_nr, &change, BITS_PER_LONG) {
+		key_press = state & BIT(bit_nr);
+		/* The meaning of SSR register depends on pull mode. */
+		key_press = pull_mode ? !key_press : key_press;
+		row = BIT_TO_ROW_SSRN(bit_nr, reg_num);
+		col = BIT_TO_COL(bit_nr);
+		keycode = bcm_kp_get_keycode(kp, row, col);
+		input_report_key(kp->input_dev, keycode, key_press);
+	}
+}
+
+static irqreturn_t bcm_kp_isr_thread(int irq, void *dev_id)
+{
+	struct bcm_kp *kp = dev_id;
+	int pull_mode = (kp->kpcr >> KPCR_MODE_SHIFT) & KPCR_MODE_MASK;
+	int reg_num;
+
+	for (reg_num = 0; reg_num <= 1; reg_num++)
+		bcm_kp_report_keys(kp, reg_num, pull_mode);
+
+	input_sync(kp->input_dev);
+
+	return IRQ_HANDLED;
+}
+
+static int bcm_kp_start(struct bcm_kp *kp)
+{
+	int error;
+
+	error = clk_prepare_enable(kp->clk);
+	if (error)
+		return error;
+
+	writel(kp->kpior, kp->base + KPIOR_OFFSET);
+
+	writel(kp->imr0_val, kp->base + KPIMR0_OFFSET);
+	writel(kp->imr1_val, kp->base + KPIMR1_OFFSET);
+
+	writel(kp->kpemr, kp->base + KPEMR0_OFFSET);
+	writel(kp->kpemr, kp->base + KPEMR1_OFFSET);
+	writel(kp->kpemr, kp->base + KPEMR2_OFFSET);
+	writel(kp->kpemr, kp->base + KPEMR3_OFFSET);
+
+	writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET);
+	writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET);
+
+	kp->last_state[0] = readl(kp->base + KPSSR0_OFFSET);
+	kp->last_state[0] = readl(kp->base + KPSSR1_OFFSET);
+
+	writel(kp->kpcr | KPCR_ENABLE, kp->base + KPCR_OFFSET);
+
+	return 0;
+}
+
+static void bcm_kp_stop(const struct bcm_kp *kp)
+{
+	u32 val;
+
+	val = readl(kp->base + KPCR_OFFSET);
+	val &= ~KPCR_ENABLE;
+	writel(0, kp->base + KPCR_OFFSET);
+	writel(0, kp->base + KPIMR0_OFFSET);
+	writel(0, kp->base + KPIMR1_OFFSET);
+	writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET);
+	writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET);
+
+	clk_disable_unprepare(kp->clk);
+}
+
+static int bcm_kp_open(struct input_dev *dev)
+{
+	struct bcm_kp *kp = input_get_drvdata(dev);
+
+	return bcm_kp_start(kp);
+}
+
+static void bcm_kp_close(struct input_dev *dev)
+{
+	struct bcm_kp *kp = input_get_drvdata(dev);
+
+	bcm_kp_stop(kp);
+}
+
+static int bcm_kp_matrix_key_parse_dt(struct bcm_kp *kp)
+{
+	struct device *dev = kp->input_dev->dev.parent;
+	struct device_node *np = dev->of_node;
+	int error;
+	unsigned int dt_val;
+	unsigned int i;
+	unsigned int num_rows, col_mask, rows_set;
+
+	/* Initialize the KPCR Keypad Configuration Register */
+	kp->kpcr = KPCR_STATUSFILTERENABLE | KPCR_COLFILTERENABLE;
+
+	error = matrix_keypad_parse_of_params(dev, &kp->n_rows, &kp->n_cols);
+	if (error) {
+		dev_err(dev, "failed to parse kp params\n");
+		return error;
+	}
+	/* Set row width for the ASIC block. */
+	kp->kpcr |= (kp->n_rows - 1) << KPCR_ROWWIDTH_SHIFT;
+
+	/* Set column width for the ASIC block. */
+	kp->kpcr |= (kp->n_cols - 1) << KPCR_COLUMNWIDTH_SHIFT;
+
+	/* Configure the IMR registers */
+
+	/* 
+	 * IMR registers contain interrupt enable bits for 8x8 matrix
+	 * IMR0 register format: <row3> <row2> <row1> <row0>
+	 * IMR1 register format: <row7> <row6> <row5> <row4>
+	 */
+	col_mask = (1 << (kp->n_cols)) - 1;
+	num_rows = kp->n_rows;
+
+	/* Set column bits in rows 0 to 3 in IMR0 */
+	kp->imr0_val = col_mask;
+
+	rows_set = 1;
+	while ((--num_rows) && (rows_set++ < 4))
+		kp->imr0_val |= (kp->imr0_val << MAX_COLS);
+
+	/* Set column bits in rows 4 to 7 in IMR1 */
+	kp->imr1_val = 0;
+	if (num_rows) {
+		kp->imr1_val = col_mask;
+		while (--num_rows)
+			kp->imr1_val |= (kp->imr1_val << MAX_COLS);
+	}
+
+	/* Initialize the KPEMR Keypress Edge Mode Registers */
+	/* Trigger on both edges */
+	kp->kpemr = 0;
+	for (i = 0; i <= 30; i = i + 2)
+		kp->kpemr |= (KPEMR_EDGETYPE_BOTH << i);
+
+	/*
+	 * Obtain the Status filter debounce value and verify against the
+	 * possible values specified in the DT binding.
+	 */
+	of_property_read_u32(np, "status-debounce-filter-period",
+		&dt_val);
+	if (dt_val > KPCR_STATUSFILTERTYPE_MAX) {
+		dev_err(dev, "Invalid Status filter debounce value %d\n",
+			dt_val);
+		return -EINVAL;
+	}
+	kp->kpcr |= dt_val << KPCR_STATUSFILTERTYPE_SHIFT;
+
+
+	/*
+	 * Obtain the Column filter debounce value and verify against the
+	 * possible values specified in the DT binding.
+	 */
+	of_property_read_u32(np, "col-debounce-filter-period",
+		&dt_val);
+
+	if (dt_val > KPCR_COLFILTERTYPE_MAX) {
+		dev_err(dev, "Invalid Column filter debounce value %d\n",
+			dt_val);
+		return -EINVAL;
+	}
+	kp->kpcr |= dt_val << KPCR_COLFILTERTYPE_SHIFT;
+
+	/*
+	 * Determine between the row and column,
+	 * which should be configured as output.
+	 */
+	if (of_property_read_bool(np, "row-output-enabled")) {
+		/*
+		* Set RowOContrl or ColumnOContrl in KPIOR
+		* to the number of pins to drive as outputs
+		*/
+		kp->kpior = (((1 << kp->n_rows) - 1) <<
+				KPIOR_ROWOCONTRL_SHIFT);
+	} else {
+		kp->kpior = (((1 << kp->n_cols) - 1) <<
+				KPIOR_COLUMNOCONTRL_SHIFT);
+	}
+
+	/*
+	 * Determine if the scan pull up needs to be enabled
+	 */
+	if (of_property_read_bool(np, "pull-up-enabled"))
+		kp->kpcr |= KPCR_MODE;
+
+	dev_dbg(dev, "n_rows=%d n_col=%d kpcr=%x kpior=%x kpemr=%x\n",
+		kp->n_rows, kp->n_cols,
+		kp->kpcr, kp->kpior, kp->kpemr);
+
+	return 0;
+}
+
+
+static int bcm_kp_probe(struct platform_device *pdev)
+{
+	struct bcm_kp *kp;
+	struct input_dev *input_dev;
+	struct resource *res;
+	int error;
+	bool repeat;
+
+	kp = devm_kzalloc(&pdev->dev, sizeof(*kp),
+				   GFP_KERNEL);
+	if (!kp)
+		return -ENOMEM;
+
+	input_dev = devm_input_allocate_device(&pdev->dev);
+	if (!input_dev) {
+		dev_err(&pdev->dev, "failed to allocate the input device\n");
+		return -ENOMEM;
+	}
+
+	__set_bit(EV_KEY, input_dev->evbit);
+
+	repeat = !!of_get_property(pdev->dev.of_node, "autorepeat", NULL);
+	/* Enable auto repeat feature of Linux input subsystem */
+	if (repeat)
+		__set_bit(EV_REP, input_dev->evbit);
+
+	input_dev->name = pdev->name;
+	input_dev->phys = "keypad/input0";
+	input_dev->dev.parent = &pdev->dev;
+	input_dev->open = bcm_kp_open;
+	input_dev->close = bcm_kp_close;
+
+	input_dev->id.bustype = BUS_HOST;
+	input_dev->id.vendor = 0x0001;
+	input_dev->id.product = 0x0001;
+	input_dev->id.version = 0x0100;
+
+	input_set_drvdata(input_dev, kp);
+
+	kp->input_dev = input_dev;
+
+	platform_set_drvdata(pdev, kp);
+
+	error = bcm_kp_matrix_key_parse_dt(kp);
+	if (error)
+		return error;
+
+	error = matrix_keypad_build_keymap(NULL, NULL,
+					   kp->n_rows,
+					   kp->n_cols,
+					   NULL, input_dev);
+	if (error) {
+		dev_err(&pdev->dev, "failed to build keymap\n");
+		return error;
+	}
+
+	/* Get the KEYPAD base address */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "Missing keypad base address resource\n");
+		return -ENODEV;
+	}
+
+	kp->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(kp->base))
+		return PTR_ERR(kp->base);
+
+	/* Enable clock */
+
+	kp->clk = devm_clk_get(&pdev->dev, "peri_clk");
+	if (IS_ERR(kp->clk)) {
+		dev_info(&pdev->dev,
+			"No clock specified. Assuming it's enabled\n");
+	}
+	else {
+		unsigned int desired_rate;
+		long actual_rate;
+
+		error = of_property_read_u32(pdev->dev.of_node,
+				"clock-frequency", &desired_rate);
+		if (error < 0)
+			desired_rate = DEFAULT_CLK_HZ;
+
+		actual_rate = clk_round_rate(kp->clk, desired_rate);
+		if (actual_rate <= 0)
+			return -EINVAL;
+
+		error = clk_set_rate(kp->clk, actual_rate);
+		if (error)
+			return -EINVAL;
+
+		error = clk_prepare_enable(kp->clk);
+		if (error)
+			return -EINVAL;
+	}
+
+	/* Put the kp into a known sane state */
+	bcm_kp_stop(kp);
+
+	kp->irq = platform_get_irq(pdev, 0);
+	if (kp->irq < 0) {
+		dev_err(&pdev->dev, "no IRQ specified\n");
+		return -EINVAL;
+	}
+
+	error = devm_request_threaded_irq(&pdev->dev, kp->irq, NULL,
+		bcm_kp_isr_thread,
+		IRQF_ONESHOT, pdev->name, kp);
+	if (error) {
+		dev_err(&pdev->dev, "failed to request IRQ\n");
+		return error;
+	}
+
+	error = input_register_device(input_dev);
+	if (error) {
+		dev_err(&pdev->dev, "failed to register input device\n");
+		return error;
+	}
+
+	return 0;
+}
+
+static const struct of_device_id bcm_kp_of_match[] = {
+	{ .compatible = "brcm,bcm-keypad" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, bcm_kp_of_match);
+
+static struct platform_driver bcm_kp_device_driver = {
+	.probe		= bcm_kp_probe,
+	.driver		= {
+		.name	= "bcm-keypad",
+		.of_match_table = of_match_ptr(bcm_kp_of_match),
+	}
+};
+
+module_platform_driver(bcm_kp_device_driver);
+
+MODULE_AUTHOR("Broadcom Corporation");
+MODULE_DESCRIPTION("BCM Keypad Driver");
+MODULE_LICENSE("GPL");
-- 
2.3.0

[PATCH v4 0/2] Add support for Broadcom keypad controller

[Scott Branden]

This series of patchsets contains the Broadcom keypad controller driver
and device tree binding documentation.

Changes from v3:
- corrected GPL to GPL v2

Changes from v2:
- changed binding to use autorepeat
- stylistic updates

Changes from v1:
- updated dt documentation to remove to matrix-keymap.txt
- removed bcm_kp_remove as it is not necessary
- removed key-interrupt-trigger-type dt binding
- added bcm_kp_report_keys and call to process key registers

Scott Branden (2):
  Input: bcm-keypad: add device tree bindings
  Input: bcm-keypad: Add Broadcom keypad controller

 .../devicetree/bindings/input/brcm,bcm-keypad.txt  | 108 +++++
 drivers/input/keyboard/Kconfig                     |  10 +
 drivers/input/keyboard/Makefile                    |   1 +
 drivers/input/keyboard/bcm-keypad.c                | 463 +++++++++++++++++++++
 4 files changed, 582 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
 create mode 100644 drivers/input/keyboard/bcm-keypad.c

-- 
2.3.0

[PATCH v4 1/2] Input: bcm-keypad: add device tree bindings

[Scott Branden]

Documents the Broadcom keypad controller device tree bindings.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 .../devicetree/bindings/input/brcm,bcm-keypad.txt  | 108 +++++++++++++++++++++
 1 file changed, 108 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt

diff --git a/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt b/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
new file mode 100644
index 0000000..b77f50b
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
@@ -0,0 +1,108 @@
+* Broadcom Keypad Controller device tree bindings
+
+Broadcom Keypad controller is used to interface a SoC with a matrix-type
+keypad device. The keypad controller supports multiple row and column lines.
+A key can be placed at each intersection of a unique row and a unique column.
+The keypad controller can sense a key-press and key-release and report the
+event using a interrupt to the cpu.
+
+This binding is based on the matrix-keymap binding with the following
+changes:
+
+keypad,num-rows and keypad,num-columns are required.
+
+Required SoC Specific Properties:
+- compatible: should be "brcm,bcm-keypad"
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- interrupts: The interrupt number to the cpu.
+
+Board Specific Properties:
+- keypad,num-rows: Number of row lines connected to the keypad
+  controller.
+
+- keypad,num-columns: Number of column lines connected to the
+  keypad controller.
+
+- col-debounce-filter-period: The debounce period for the Column filter.
+
+	KEYPAD_DEBOUNCE_1_ms	=	0
+	KEYPAD_DEBOUNCE_2_ms	=	1
+	KEYPAD_DEBOUNCE_4_ms	=	2
+	KEYPAD_DEBOUNCE_8_ms	=	3
+	KEYPAD_DEBOUNCE_16_ms	=	4
+	KEYPAD_DEBOUNCE_32_ms	=	5
+	KEYPAD_DEBOUNCE_64_ms	=	6
+	KEYPAD_DEBOUNCE_128_ms	=	7
+
+- status-debounce-filter-period: The debounce period for the Status filter.
+
+	KEYPAD_DEBOUNCE_1_ms	=	0
+	KEYPAD_DEBOUNCE_2_ms	=	1
+	KEYPAD_DEBOUNCE_4_ms	=	2
+	KEYPAD_DEBOUNCE_8_ms	=	3
+	KEYPAD_DEBOUNCE_16_ms	=	4
+	KEYPAD_DEBOUNCE_32_ms	=	5
+	KEYPAD_DEBOUNCE_64_ms	=	6
+	KEYPAD_DEBOUNCE_128_ms	=	7
+
+- row-output-enabled: An optional property indicating whether the row or
+  column is being used as output. If specified the row is being used
+  as the output. Else defaults to column.
+
+- pull-up-enabled: An optional property indicating the Keypad scan mode.
+  If specified implies the keypad scan pull-up has been enabled.
+
+- autorepeat: Boolean, Enable auto repeat feature of Linux input
+	  subsystem (optional).
+
+- linux,keymap: The keymap for keys as described in the binding document
+  devicetree/bindings/input/matrix-keymap.txt.
+
+Example:
+#include "dt-bindings/input/input.h"
+
+/ {
+	keypad: keypad@180ac000 {
+		/* Required SoC specific properties */
+		compatible = "brcm,bcm-keypad";
+
+		/* Required Board specific properties */
+		keypad,num-rows = <5>;
+		keypad,num-columns = <5>;
+		status = "okay";
+
+		linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_F) /* key_forward */
+		MATRIX_KEY(0x00, 0x03, KEY_HOME) /* key_home */
+		MATRIX_KEY(0x00, 0x04, KEY_M) /* key_message */
+		MATRIX_KEY(0x01, 0x00, KEY_A) /* key_contacts */
+		MATRIX_KEY(0x01, 0x01, KEY_1) /* key_1 */
+		MATRIX_KEY(0x01, 0x02, KEY_2) /* key_2 */
+		MATRIX_KEY(0x01, 0x03, KEY_3) /* key_3 */
+		MATRIX_KEY(0x01, 0x04, KEY_S) /* key_speaker */
+		MATRIX_KEY(0x02, 0x00, KEY_P) /* key_phone */
+		MATRIX_KEY(0x02, 0x01, KEY_4) /* key_4 */
+		MATRIX_KEY(0x02, 0x02, KEY_5) /* key_5 */
+		MATRIX_KEY(0x02, 0x03, KEY_6) /* key_6 */
+		MATRIX_KEY(0x02, 0x04, KEY_VOLUMEUP) /* key_vol_up */
+		MATRIX_KEY(0x03, 0x00, KEY_C) /* key_call_log */
+		MATRIX_KEY(0x03, 0x01, KEY_7) /* key_7 */
+		MATRIX_KEY(0x03, 0x02, KEY_8) /* key_8 */
+		MATRIX_KEY(0x03, 0x03, KEY_9) /* key_9 */
+		MATRIX_KEY(0x03, 0x04, KEY_VOLUMEDOWN) /* key_vol_down */
+		MATRIX_KEY(0x04, 0x00, KEY_H) /* key_headset */
+		MATRIX_KEY(0x04, 0x01, KEY_KPASTERISK) /* key_* */
+		MATRIX_KEY(0x04, 0x02, KEY_0) /* key_0 */
+		MATRIX_KEY(0x04, 0x03, KEY_GRAVE) /* key_# */
+		MATRIX_KEY(0x04, 0x04, KEY_MUTE) /* key_mute */
+		>;
+
+		/* Optional board specific properties */
+		col-debounce-filter-period = <5>;
+		row-output-enabled;
+		pull-up-enabled;
+
+	};
+};
-- 
2.3.0

[PATCH v4 2/2] Input: bcm-keypad: Add Broadcom keypad controller

[Scott Branden]

Add driver for Broadcom's keypad controller.

Broadcom Keypad controller is used to interface a SoC with a matrix-type
keypad device. The keypad controller supports multiple row and column lines.
A key can be placed at each intersection of a unique row and a unique column.
The keypad controller can sense a key-press and key-release and report the
event using a interrupt to the cpu.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/input/keyboard/Kconfig      |  10 +
 drivers/input/keyboard/Makefile     |   1 +
 drivers/input/keyboard/bcm-keypad.c | 463 ++++++++++++++++++++++++++++++++++++
 3 files changed, 474 insertions(+)
 create mode 100644 drivers/input/keyboard/bcm-keypad.c

diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index a5d9b3f..3a0c0f2 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -676,4 +676,14 @@ config KEYBOARD_CAP11XX
 	  To compile this driver as a module, choose M here: the
 	  module will be called cap11xx.
 
+config KEYBOARD_BCM
+	tristate "Broadcom keypad driver"
+	select INPUT_MATRIXKMAP
+	default ARCH_BCM_CYGNUS
+	help
+	  Say Y here if you want to use Broadcom keypad.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called bcm-keypad.
+
 endif
diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
index febafa5..3cff8f6 100644
--- a/drivers/input/keyboard/Makefile
+++ b/drivers/input/keyboard/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_KEYBOARD_ADP5589)		+= adp5589-keys.o
 obj-$(CONFIG_KEYBOARD_AMIGA)		+= amikbd.o
 obj-$(CONFIG_KEYBOARD_ATARI)		+= atakbd.o
 obj-$(CONFIG_KEYBOARD_ATKBD)		+= atkbd.o
+obj-$(CONFIG_KEYBOARD_BCM)		+= bcm-keypad.o
 obj-$(CONFIG_KEYBOARD_BFIN)		+= bf54x-keys.o
 obj-$(CONFIG_KEYBOARD_CAP11XX)		+= cap11xx.o
 obj-$(CONFIG_KEYBOARD_CLPS711X)		+= clps711x-keypad.o
diff --git a/drivers/input/keyboard/bcm-keypad.c b/drivers/input/keyboard/bcm-keypad.c
new file mode 100644
index 0000000..0fde149
--- /dev/null
+++ b/drivers/input/keyboard/bcm-keypad.c
@@ -0,0 +1,463 @@
+/*
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/bitops.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/sizes.h>
+#include <linux/stddef.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <asm/memory.h>
+#include <linux/io.h>
+#include <linux/input/matrix_keypad.h>
+
+#define DEFAULT_CLK_HZ                  31250
+/* Repeat period (ms) */
+#define KEY_REPEAT_PERIOD               100
+/* First time press dly (ms) */
+#define KEY_REPEAT_DELAY                400
+#define MAX_ROWS                        8
+#define MAX_COLS                        8
+
+/* Register/field definitions */
+#define KPCR_OFFSET                          0x00000080
+#define KPCR_MODE                       0x00000002
+#define KPCR_MODE_SHIFT                 1
+#define KPCR_MODE_MASK                  1
+#define KPCR_ENABLE                     0x00000001
+#define KPCR_STATUSFILTERENABLE         0x00008000
+#define KPCR_STATUSFILTERTYPE_SHIFT          12
+#define KPCR_COLFILTERENABLE            0x00000800
+#define KPCR_COLFILTERTYPE_SHIFT             8
+#define KPCR_ROWWIDTH_SHIFT                  20
+#define KPCR_COLUMNWIDTH_SHIFT               16
+
+#define KPIOR_OFFSET                         0x00000084
+#define KPIOR_ROWOCONTRL_SHIFT               24
+#define KPIOR_ROWOCONTRL_MASK                0xFF000000
+#define KPIOR_COLUMNOCONTRL_SHIFT            16
+#define KPIOR_COLUMNOCONTRL_MASK             0x00FF0000
+#define KPIOR_COLUMN_IO_DATA_SHIFT           0
+
+#define KPEMR0_OFFSET                        0x00000090
+#define KPEMR1_OFFSET                        0x00000094
+#define KPEMR2_OFFSET                        0x00000098
+#define KPEMR3_OFFSET                        0x0000009C
+#define KPEMR_EDGETYPE_BOTH 3
+
+#define KPSSR0_OFFSET                        0x000000A0
+#define KPSSR1_OFFSET                        0x000000A4
+#define KPSSRN_OFFSET(reg_n)                 (KPSSR0_OFFSET + (4 * reg_n))
+#define KPIMR0_OFFSET                        0x000000B0
+#define KPIMR1_OFFSET                        0x000000B4
+#define KPICR0_OFFSET                        0x000000B8
+#define KPICR1_OFFSET                        0x000000BC
+#define KPICRN_OFFSET(reg_n)                 (KPICR0_OFFSET + (4 * reg_n))
+#define KPISR0_OFFSET                        0x000000C0
+#define KPISR1_OFFSET                        0x000000C4
+
+#define KPCR_STATUSFILTERTYPE_MAX 7
+#define KPCR_COLFILTERTYPE_MAX 7
+
+/* Macros to determine the row/column from a bit that is set in SSR0/1. */
+#define BIT_TO_ROW_SSRN(bit_nr, reg_n)  ((bit_nr >> 3) + (4 * reg_n))
+#define BIT_TO_COL(bit_nr)       (bit_nr % 8)
+
+/* Structure representing various run-time entities */
+struct bcm_kp {
+	void __iomem *base;
+	int irq;
+	struct clk *clk;
+	struct input_dev *input_dev;
+	unsigned long last_state[2];
+	unsigned int n_rows;
+	unsigned int n_cols;
+	u32 kpcr;
+	u32 kpior;
+	u32 kpemr;
+	u32 imr0_val;
+	u32 imr1_val;
+};
+
+/*
+ * Returns the keycode from the input device keymap given the row and
+ * column.
+ */
+static inline int bcm_kp_get_keycode(struct bcm_kp *kp, int row, int col)
+{
+	unsigned int row_shift = get_count_order(kp->n_cols);
+	unsigned short *keymap = kp->input_dev->keycode;
+
+	return keymap[MATRIX_SCAN_CODE(row, col, row_shift)];
+}
+
+static void bcm_kp_report_keys(struct bcm_kp *kp, int reg_num, int pull_mode)
+{
+	unsigned long state, change;
+	int bit_nr;
+	int key_press;
+	int row, col;
+	unsigned int keycode;
+
+	/* Clear interrupts */
+	writel(0xFFFFFFFF, kp->base + KPICRN_OFFSET(reg_num));
+
+	state = readl(kp->base + KPSSRN_OFFSET(reg_num));
+	change = kp->last_state[reg_num] ^ state;
+	kp->last_state[reg_num] = state;
+
+	for_each_set_bit(bit_nr, &change, BITS_PER_LONG) {
+		key_press = state & BIT(bit_nr);
+		/* The meaning of SSR register depends on pull mode. */
+		key_press = pull_mode ? !key_press : key_press;
+		row = BIT_TO_ROW_SSRN(bit_nr, reg_num);
+		col = BIT_TO_COL(bit_nr);
+		keycode = bcm_kp_get_keycode(kp, row, col);
+		input_report_key(kp->input_dev, keycode, key_press);
+	}
+}
+
+static irqreturn_t bcm_kp_isr_thread(int irq, void *dev_id)
+{
+	struct bcm_kp *kp = dev_id;
+	int pull_mode = (kp->kpcr >> KPCR_MODE_SHIFT) & KPCR_MODE_MASK;
+	int reg_num;
+
+	for (reg_num = 0; reg_num <= 1; reg_num++)
+		bcm_kp_report_keys(kp, reg_num, pull_mode);
+
+	input_sync(kp->input_dev);
+
+	return IRQ_HANDLED;
+}
+
+static int bcm_kp_start(struct bcm_kp *kp)
+{
+	int error;
+
+	error = clk_prepare_enable(kp->clk);
+	if (error)
+		return error;
+
+	writel(kp->kpior, kp->base + KPIOR_OFFSET);
+
+	writel(kp->imr0_val, kp->base + KPIMR0_OFFSET);
+	writel(kp->imr1_val, kp->base + KPIMR1_OFFSET);
+
+	writel(kp->kpemr, kp->base + KPEMR0_OFFSET);
+	writel(kp->kpemr, kp->base + KPEMR1_OFFSET);
+	writel(kp->kpemr, kp->base + KPEMR2_OFFSET);
+	writel(kp->kpemr, kp->base + KPEMR3_OFFSET);
+
+	writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET);
+	writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET);
+
+	kp->last_state[0] = readl(kp->base + KPSSR0_OFFSET);
+	kp->last_state[0] = readl(kp->base + KPSSR1_OFFSET);
+
+	writel(kp->kpcr | KPCR_ENABLE, kp->base + KPCR_OFFSET);
+
+	return 0;
+}
+
+static void bcm_kp_stop(const struct bcm_kp *kp)
+{
+	u32 val;
+
+	val = readl(kp->base + KPCR_OFFSET);
+	val &= ~KPCR_ENABLE;
+	writel(0, kp->base + KPCR_OFFSET);
+	writel(0, kp->base + KPIMR0_OFFSET);
+	writel(0, kp->base + KPIMR1_OFFSET);
+	writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET);
+	writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET);
+
+	clk_disable_unprepare(kp->clk);
+}
+
+static int bcm_kp_open(struct input_dev *dev)
+{
+	struct bcm_kp *kp = input_get_drvdata(dev);
+
+	return bcm_kp_start(kp);
+}
+
+static void bcm_kp_close(struct input_dev *dev)
+{
+	struct bcm_kp *kp = input_get_drvdata(dev);
+
+	bcm_kp_stop(kp);
+}
+
+static int bcm_kp_matrix_key_parse_dt(struct bcm_kp *kp)
+{
+	struct device *dev = kp->input_dev->dev.parent;
+	struct device_node *np = dev->of_node;
+	int error;
+	unsigned int dt_val;
+	unsigned int i;
+	unsigned int num_rows, col_mask, rows_set;
+
+	/* Initialize the KPCR Keypad Configuration Register */
+	kp->kpcr = KPCR_STATUSFILTERENABLE | KPCR_COLFILTERENABLE;
+
+	error = matrix_keypad_parse_of_params(dev, &kp->n_rows, &kp->n_cols);
+	if (error) {
+		dev_err(dev, "failed to parse kp params\n");
+		return error;
+	}
+	/* Set row width for the ASIC block. */
+	kp->kpcr |= (kp->n_rows - 1) << KPCR_ROWWIDTH_SHIFT;
+
+	/* Set column width for the ASIC block. */
+	kp->kpcr |= (kp->n_cols - 1) << KPCR_COLUMNWIDTH_SHIFT;
+
+	/* Configure the IMR registers */
+
+	/* 
+	 * IMR registers contain interrupt enable bits for 8x8 matrix
+	 * IMR0 register format: <row3> <row2> <row1> <row0>
+	 * IMR1 register format: <row7> <row6> <row5> <row4>
+	 */
+	col_mask = (1 << (kp->n_cols)) - 1;
+	num_rows = kp->n_rows;
+
+	/* Set column bits in rows 0 to 3 in IMR0 */
+	kp->imr0_val = col_mask;
+
+	rows_set = 1;
+	while ((--num_rows) && (rows_set++ < 4))
+		kp->imr0_val |= (kp->imr0_val << MAX_COLS);
+
+	/* Set column bits in rows 4 to 7 in IMR1 */
+	kp->imr1_val = 0;
+	if (num_rows) {
+		kp->imr1_val = col_mask;
+		while (--num_rows)
+			kp->imr1_val |= (kp->imr1_val << MAX_COLS);
+	}
+
+	/* Initialize the KPEMR Keypress Edge Mode Registers */
+	/* Trigger on both edges */
+	kp->kpemr = 0;
+	for (i = 0; i <= 30; i = i + 2)
+		kp->kpemr |= (KPEMR_EDGETYPE_BOTH << i);
+
+	/*
+	 * Obtain the Status filter debounce value and verify against the
+	 * possible values specified in the DT binding.
+	 */
+	of_property_read_u32(np, "status-debounce-filter-period",
+		&dt_val);
+	if (dt_val > KPCR_STATUSFILTERTYPE_MAX) {
+		dev_err(dev, "Invalid Status filter debounce value %d\n",
+			dt_val);
+		return -EINVAL;
+	}
+	kp->kpcr |= dt_val << KPCR_STATUSFILTERTYPE_SHIFT;
+
+
+	/*
+	 * Obtain the Column filter debounce value and verify against the
+	 * possible values specified in the DT binding.
+	 */
+	of_property_read_u32(np, "col-debounce-filter-period",
+		&dt_val);
+
+	if (dt_val > KPCR_COLFILTERTYPE_MAX) {
+		dev_err(dev, "Invalid Column filter debounce value %d\n",
+			dt_val);
+		return -EINVAL;
+	}
+	kp->kpcr |= dt_val << KPCR_COLFILTERTYPE_SHIFT;
+
+	/*
+	 * Determine between the row and column,
+	 * which should be configured as output.
+	 */
+	if (of_property_read_bool(np, "row-output-enabled")) {
+		/*
+		* Set RowOContrl or ColumnOContrl in KPIOR
+		* to the number of pins to drive as outputs
+		*/
+		kp->kpior = (((1 << kp->n_rows) - 1) <<
+				KPIOR_ROWOCONTRL_SHIFT);
+	} else {
+		kp->kpior = (((1 << kp->n_cols) - 1) <<
+				KPIOR_COLUMNOCONTRL_SHIFT);
+	}
+
+	/*
+	 * Determine if the scan pull up needs to be enabled
+	 */
+	if (of_property_read_bool(np, "pull-up-enabled"))
+		kp->kpcr |= KPCR_MODE;
+
+	dev_dbg(dev, "n_rows=%d n_col=%d kpcr=%x kpior=%x kpemr=%x\n",
+		kp->n_rows, kp->n_cols,
+		kp->kpcr, kp->kpior, kp->kpemr);
+
+	return 0;
+}
+
+
+static int bcm_kp_probe(struct platform_device *pdev)
+{
+	struct bcm_kp *kp;
+	struct input_dev *input_dev;
+	struct resource *res;
+	int error;
+	bool repeat;
+
+	kp = devm_kzalloc(&pdev->dev, sizeof(*kp),
+				   GFP_KERNEL);
+	if (!kp)
+		return -ENOMEM;
+
+	input_dev = devm_input_allocate_device(&pdev->dev);
+	if (!input_dev) {
+		dev_err(&pdev->dev, "failed to allocate the input device\n");
+		return -ENOMEM;
+	}
+
+	__set_bit(EV_KEY, input_dev->evbit);
+
+	repeat = !!of_get_property(pdev->dev.of_node, "autorepeat", NULL);
+	/* Enable auto repeat feature of Linux input subsystem */
+	if (repeat)
+		__set_bit(EV_REP, input_dev->evbit);
+
+	input_dev->name = pdev->name;
+	input_dev->phys = "keypad/input0";
+	input_dev->dev.parent = &pdev->dev;
+	input_dev->open = bcm_kp_open;
+	input_dev->close = bcm_kp_close;
+
+	input_dev->id.bustype = BUS_HOST;
+	input_dev->id.vendor = 0x0001;
+	input_dev->id.product = 0x0001;
+	input_dev->id.version = 0x0100;
+
+	input_set_drvdata(input_dev, kp);
+
+	kp->input_dev = input_dev;
+
+	platform_set_drvdata(pdev, kp);
+
+	error = bcm_kp_matrix_key_parse_dt(kp);
+	if (error)
+		return error;
+
+	error = matrix_keypad_build_keymap(NULL, NULL,
+					   kp->n_rows,
+					   kp->n_cols,
+					   NULL, input_dev);
+	if (error) {
+		dev_err(&pdev->dev, "failed to build keymap\n");
+		return error;
+	}
+
+	/* Get the KEYPAD base address */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "Missing keypad base address resource\n");
+		return -ENODEV;
+	}
+
+	kp->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(kp->base))
+		return PTR_ERR(kp->base);
+
+	/* Enable clock */
+
+	kp->clk = devm_clk_get(&pdev->dev, "peri_clk");
+	if (IS_ERR(kp->clk)) {
+		dev_info(&pdev->dev,
+			"No clock specified. Assuming it's enabled\n");
+	}
+	else {
+		unsigned int desired_rate;
+		long actual_rate;
+
+		error = of_property_read_u32(pdev->dev.of_node,
+				"clock-frequency", &desired_rate);
+		if (error < 0)
+			desired_rate = DEFAULT_CLK_HZ;
+
+		actual_rate = clk_round_rate(kp->clk, desired_rate);
+		if (actual_rate <= 0)
+			return -EINVAL;
+
+		error = clk_set_rate(kp->clk, actual_rate);
+		if (error)
+			return -EINVAL;
+
+		error = clk_prepare_enable(kp->clk);
+		if (error)
+			return -EINVAL;
+	}
+
+	/* Put the kp into a known sane state */
+	bcm_kp_stop(kp);
+
+	kp->irq = platform_get_irq(pdev, 0);
+	if (kp->irq < 0) {
+		dev_err(&pdev->dev, "no IRQ specified\n");
+		return -EINVAL;
+	}
+
+	error = devm_request_threaded_irq(&pdev->dev, kp->irq, NULL,
+		bcm_kp_isr_thread,
+		IRQF_ONESHOT, pdev->name, kp);
+	if (error) {
+		dev_err(&pdev->dev, "failed to request IRQ\n");
+		return error;
+	}
+
+	error = input_register_device(input_dev);
+	if (error) {
+		dev_err(&pdev->dev, "failed to register input device\n");
+		return error;
+	}
+
+	return 0;
+}
+
+static const struct of_device_id bcm_kp_of_match[] = {
+	{ .compatible = "brcm,bcm-keypad" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, bcm_kp_of_match);
+
+static struct platform_driver bcm_kp_device_driver = {
+	.probe		= bcm_kp_probe,
+	.driver		= {
+		.name	= "bcm-keypad",
+		.of_match_table = of_match_ptr(bcm_kp_of_match),
+	}
+};
+
+module_platform_driver(bcm_kp_device_driver);
+
+MODULE_AUTHOR("Broadcom Corporation");
+MODULE_DESCRIPTION("BCM Keypad Driver");
+MODULE_LICENSE("GPL v2");
-- 
2.3.0

Re: [PATCH v2 2/2] hwrng: iproc-rng200 - Add Broadcom IPROC RNG driver

[Arnd Bergmann]

On Saturday 28 February 2015 08:01:11 Scott Branden wrote:
> > The udelay(10) that the other drivers have seems about appropriate then,
> > and we can independently think of a way to refine the interface.
> > Please add a comment that explains the rate. Also, is there some kind
> > of FIFO present in the hwrng device? If it can store close to 1ms work
> > of data (1000 bits), you can just use an msleep(1) to wait for the
> > pool to recover.
> FIFO is 512 bits.  I will look as to whether we can live with 1/2 
> throughput.

In that case, I think usleep_range(min(len * 8, 500), 500)) would be
a good compromise: it waits at most until the fifo is full, but might
return earlier if enough bits are available to fulfill the request.

	Arnd

Re: [PATCH v4 2/2] Input: bcm-keypad: Add Broadcom keypad controller

[Dmitry Torokhov]

Hi Scott,

On Sat, Feb 28, 2015 at 08:35:57AM -0800, Scott Branden wrote:
> +	/* Enable clock */
> +
> +	kp->clk = devm_clk_get(&pdev->dev, "peri_clk");
> +	if (IS_ERR(kp->clk)) {
> +		dev_info(&pdev->dev,
> +			"No clock specified. Assuming it's enabled\n");

I was doing the final pass before applying and I think that this is not
quite correct, as it does not handle -EPROBE_DEFER properly which is
quite common. I think we should do something like this:

		error = PTR_ERR(kp->clk);
		if (error != -ENOENT) {
			if (error != -EPROBE_DEFER)
				dev_err(.. "Failed to get clock" ...);
			return error;
		}
		dev_dbg(... "No clock specified" ...);

No need to resubmit if you are OK with this, I can make the change
locally.

> +	}
> +	else {

Checkpach should have warned you that it should have been "} else {";
I'll fix it up locally along with few other cosmetic changes and
dropping a few extra headers.

Thanks.

-- 
Dmitry

Re: [PATCH v4 2/2] Input: bcm-keypad: Add Broadcom keypad controller

[Dmitry Torokhov]

On Sat, Feb 28, 2015 at 02:10:22PM -0800, Dmitry Torokhov wrote:
> Hi Scott,
> 
> On Sat, Feb 28, 2015 at 08:35:57AM -0800, Scott Branden wrote:
> > +	/* Enable clock */
> > +
> > +	kp->clk = devm_clk_get(&pdev->dev, "peri_clk");
> > +	if (IS_ERR(kp->clk)) {
> > +		dev_info(&pdev->dev,
> > +			"No clock specified. Assuming it's enabled\n");
> 
> I was doing the final pass before applying and I think that this is not
> quite correct, as it does not handle -EPROBE_DEFER properly which is
> quite common. I think we should do something like this:
> 
> 		error = PTR_ERR(kp->clk);
> 		if (error != -ENOENT) {
> 			if (error != -EPROBE_DEFER)
> 				dev_err(.. "Failed to get clock" ...);
> 			return error;
> 		}
> 		dev_dbg(... "No clock specified" ...);
> 
> No need to resubmit if you are OK with this, I can make the change
> locally.

Hmm, also bcm_kp_start() and bcm_kp_stop() should check if kp->clk is
valid before trying to enable/disable it.

> 
> > +	}
> > +	else {
> 
> Checkpach should have warned you that it should have been "} else {";
> I'll fix it up locally along with few other cosmetic changes and
> dropping a few extra headers.
> 
> Thanks.
> 
> -- 
> Dmitry

-- 
Dmitry

Re: [PATCH v2 0/2] Add support for Broadcom RNG200

[Herbert Xu]

On Wed, Feb 25, 2015 at 10:16:22AM -0800, Scott Branden wrote:
> This series of patchsets contains the Broadcom Random Number Generator
> driver and device tree binding documentation.
> 
> Changes from v1:
>  added \n to 2 dev_err messages

If you want this to go through the crypto tree please add a cc
to linux-crypto@vger.kernel.org.

Thanks,
-- 
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt

Re: [PATCH v4 2/2] Input: bcm-keypad: Add Broadcom keypad controller

[Scott Branden]

Hi Dmitry,

I don't see the need for a check of the clock in bcm_kp_start or stop. 
See comment below.

On 15-02-28 02:15 PM, Dmitry Torokhov wrote:
> On Sat, Feb 28, 2015 at 02:10:22PM -0800, Dmitry Torokhov wrote:
>> Hi Scott,
>>
>> On Sat, Feb 28, 2015 at 08:35:57AM -0800, Scott Branden wrote:
>>> +	/* Enable clock */
>>> +
>>> +	kp->clk = devm_clk_get(&pdev->dev, "peri_clk");
>>> +	if (IS_ERR(kp->clk)) {
>>> +		dev_info(&pdev->dev,
>>> +			"No clock specified. Assuming it's enabled\n");
>>
>> I was doing the final pass before applying and I think that this is not
>> quite correct, as it does not handle -EPROBE_DEFER properly which is
>> quite common. I think we should do something like this:
>>
>> 		error = PTR_ERR(kp->clk);
>> 		if (error != -ENOENT) {
>> 			if (error != -EPROBE_DEFER)
>> 				dev_err(.. "Failed to get clock" ...);
>> 			return error;
>> 		}
>> 		dev_dbg(... "No clock specified" ...);
>>
>> No need to resubmit if you are OK with this, I can make the change
>> locally.
>
> Hmm, also bcm_kp_start() and bcm_kp_stop() should check if kp->clk is
> valid before trying to enable/disable it.
>
I checked and other keyboard drivers do not check this.  I return an 
error in bcm_kp_start if the clk enable fails.  On stop, if the clk is 
not valid something is really, really wrong as well.
>>
>>> +	}
>>> +	else {
>>
>> Checkpach should have warned you that it should have been "} else {";
>> I'll fix it up locally along with few other cosmetic changes and
>> dropping a few extra headers.
>>
>> Thanks.
>>
>> --
>> Dmitry
>

Re: [PATCH v4 2/2] Input: bcm-keypad: Add Broadcom keypad controller

[Scott Branden]

Hi Dmitry,

Yes, please improve the driver and make the local change.

Regards,
  Scott

On 15-02-28 02:15 PM, Dmitry Torokhov wrote:
> On Sat, Feb 28, 2015 at 02:10:22PM -0800, Dmitry Torokhov wrote:
>> Hi Scott,
>>
>> On Sat, Feb 28, 2015 at 08:35:57AM -0800, Scott Branden wrote:
>>> +	/* Enable clock */
>>> +
>>> +	kp->clk = devm_clk_get(&pdev->dev, "peri_clk");
>>> +	if (IS_ERR(kp->clk)) {
>>> +		dev_info(&pdev->dev,
>>> +			"No clock specified. Assuming it's enabled\n");
>>
>> I was doing the final pass before applying and I think that this is not
>> quite correct, as it does not handle -EPROBE_DEFER properly which is
>> quite common. I think we should do something like this:
>>
>> 		error = PTR_ERR(kp->clk);
>> 		if (error != -ENOENT) {
>> 			if (error != -EPROBE_DEFER)
>> 				dev_err(.. "Failed to get clock" ...);
>> 			return error;
>> 		}
>> 		dev_dbg(... "No clock specified" ...);
>>
>> No need to resubmit if you are OK with this, I can make the change
>> locally.
>
> Hmm, also bcm_kp_start() and bcm_kp_stop() should check if kp->clk is
> valid before trying to enable/disable it.
>
I am ok with these changes if you want to change locally.

>>
>>> +	}
>>> +	else {
>>
>> Checkpach should have warned you that it should have been "} else {";
>> I'll fix it up locally along with few other cosmetic changes and
>> dropping a few extra headers.
>>
>> Thanks.
>>
>> --
>> Dmitry
>

Re: [PATCH v2 2/2] hwrng: iproc-rng200 - Add Broadcom IPROC RNG driver

[Scott Branden]

Hi Arnd,

Thanks for the suggested change.

On 15-02-28 11:31 AM, Arnd Bergmann wrote:
> On Saturday 28 February 2015 08:01:11 Scott Branden wrote:
>>> The udelay(10) that the other drivers have seems about appropriate then,
>>> and we can independently think of a way to refine the interface.
>>> Please add a comment that explains the rate. Also, is there some kind
>>> of FIFO present in the hwrng device? If it can store close to 1ms work
>>> of data (1000 bits), you can just use an msleep(1) to wait for the
>>> pool to recover.
>> FIFO is 512 bits.  I will look as to whether we can live with 1/2
>> throughput.
>
> In that case, I think usleep_range(min(len * 8, 500), 500)) would be
> a good compromise: it waits at most until the fifo is full, but might
> return earlier if enough bits are available to fulfill the request.
OK, will change in next version.
>
> 	Arnd
>

Re: [PATCH v4 2/2] Input: bcm-keypad: Add Broadcom keypad controller

[Dmitry Torokhov]

Hi Scott,

On Mon, Mar 02, 2015 at 11:37:57AM -0800, Scott Branden wrote:
> Hi Dmitry,
> 
> I don't see the need for a check of the clock in bcm_kp_start or
> stop. See comment below.
> 
> On 15-02-28 02:15 PM, Dmitry Torokhov wrote:
> >On Sat, Feb 28, 2015 at 02:10:22PM -0800, Dmitry Torokhov wrote:
> >>Hi Scott,
> >>
> >>On Sat, Feb 28, 2015 at 08:35:57AM -0800, Scott Branden wrote:
> >>>+	/* Enable clock */
> >>>+
> >>>+	kp->clk = devm_clk_get(&pdev->dev, "peri_clk");
> >>>+	if (IS_ERR(kp->clk)) {
> >>>+		dev_info(&pdev->dev,
> >>>+			"No clock specified. Assuming it's enabled\n");
> >>
> >>I was doing the final pass before applying and I think that this is not
> >>quite correct, as it does not handle -EPROBE_DEFER properly which is
> >>quite common. I think we should do something like this:
> >>
> >>		error = PTR_ERR(kp->clk);
> >>		if (error != -ENOENT) {
> >>			if (error != -EPROBE_DEFER)
> >>				dev_err(.. "Failed to get clock" ...);
> >>			return error;
> >>		}
> >>		dev_dbg(... "No clock specified" ...);
> >>
> >>No need to resubmit if you are OK with this, I can make the change
> >>locally.
> >
> >Hmm, also bcm_kp_start() and bcm_kp_stop() should check if kp->clk is
> >valid before trying to enable/disable it.
> >
> I checked and other keyboard drivers do not check this.  I return an
> error in bcm_kp_start if the clk enable fails.  On stop, if the clk
> is not valid something is really, really wrong as well.

The other drivers simply abort probe() if they can't get clock, you
decided to allow probe() to finish and assume that clock is already
enabled, leaving kp->clk == ERR_PTR(-ENOENT) in your version. If you try
then calling clk_prepare_enable() with that pointer it is going to bomb,
that is why I said you need to check pointer validity in bcm_kp_start()
and bcm_kp_stop().

Thanks.

-- 
Dmitry

Re: [PATCH v4 2/2] Input: bcm-keypad: Add Broadcom keypad controller

[Scott Branden]

Hi Dmitry,

I understand what's missing now.

Thanks,
  Scott

On 15-03-02 12:23 PM, Dmitry Torokhov wrote:
> Hi Scott,
>
>>> Hmm, also bcm_kp_start() and bcm_kp_stop() should check if kp->clk is
>>> valid before trying to enable/disable it.
>>>
>> I checked and other keyboard drivers do not check this.  I return an
>> error in bcm_kp_start if the clk enable fails.  On stop, if the clk
>> is not valid something is really, really wrong as well.
>
> The other drivers simply abort probe() if they can't get clock, you
> decided to allow probe() to finish and assume that clock is already
> enabled, leaving kp->clk == ERR_PTR(-ENOENT) in your version. If you try
> then calling clk_prepare_enable() with that pointer it is going to bomb,
> that is why I said you need to check pointer validity in bcm_kp_start()
> and bcm_kp_stop().
>
> Thanks.
>

Re: [PATCH v2 1/2] hwrng: iproc-rng200 - Add device tree bindings

[Florian Fainelli]

On 25/02/15 10:16, Scott Branden wrote:
> Documents the IPROC random number generator device tree bindings
> used in some Broadcom chipsets.
> 
> Reviewed-by: Ray Jui <rjui@broadcom.com>
> Signed-off-by: Scott Branden <sbranden@broadcom.com>

Applied to devicetree/next at github.com/stblinux, thanks!
-- 
Florian

Re: [PATCH 4/4] mmc: sdhci-iproc: add device tree bindings

[Florian Fainelli]

On 09/02/15 16:06, Scott Branden wrote:
> Add device tree binding documentation for IPROC SDHCI driver.
> 
> Acked-by: Ray Jui <rjui@broadcom.com>
> Signed-off-by: Corneliu Doban <cdoban@broadcom.com>
> Signed-off-by: Scott Branden <sbranden@broadcom.com>
> ---
>  .../devicetree/bindings/mmc/brcm,sdhci-iproc.txt   | 23 ++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt
> 
> diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt b/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt
> new file mode 100644
> index 0000000..72cc9cc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt
> @@ -0,0 +1,23 @@
> +Broadcom IPROC SDHCI controller
> +
> +This file documents differences between the core properties described
> +by mmc.txt and the properties that represent the IPROC SDHCI controller.
> +
> +Required properties:
> +- compatible : Should be "brcm,sdhci-iproc-cygnus".
> +- clocks : The clock feeding the SDHCI controller.
> +
> +Optional properties:
> +  - sdhci,auto-cmd12: specifies that controller should use auto CMD12.

Formatting is a little different here, there is one too many space to
begin the line.

> +
> +Example:
> +
> +sdhci0: sdhci@0x18041000 {

0x is typically dropped from this part, to only appear in the "reg"
property.

> +	compatible = "brcm,sdhci-iproc-cygnus";
> +	reg = <0x18041000 0x100>;
> +	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> +	clocks = <&lcpll0_clks BCM_CYGNUS_LCPLL0_SDIO_CLK>;
> +	bus-width = <4>;
> +	sdhci,auto-cmd12;
> +	no-1-8-v;
> +};
> 

Unless there is a re-spin, I will fix this myself while applying this
patch to devicetree/next.

Thanks
-- 
Florian

Re: [PATCH v4 1/2] Input: bcm-keypad: add device tree bindings

[Dmitry Torokhov]

On Sat, Feb 28, 2015 at 08:35:56AM -0800, Scott Branden wrote:
> Documents the Broadcom keypad controller device tree bindings.
> 
> Reviewed-by: Ray Jui <rjui@broadcom.com>
> Signed-off-by: Scott Branden <sbranden@broadcom.com>

I folded this into the patch adding the driver itself and queued for
4.1.

Thank you.

> ---
>  .../devicetree/bindings/input/brcm,bcm-keypad.txt  | 108 +++++++++++++++++++++
>  1 file changed, 108 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
> 
> diff --git a/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt b/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
> new file mode 100644
> index 0000000..b77f50b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/input/brcm,bcm-keypad.txt
> @@ -0,0 +1,108 @@
> +* Broadcom Keypad Controller device tree bindings
> +
> +Broadcom Keypad controller is used to interface a SoC with a matrix-type
> +keypad device. The keypad controller supports multiple row and column lines.
> +A key can be placed at each intersection of a unique row and a unique column.
> +The keypad controller can sense a key-press and key-release and report the
> +event using a interrupt to the cpu.
> +
> +This binding is based on the matrix-keymap binding with the following
> +changes:
> +
> +keypad,num-rows and keypad,num-columns are required.
> +
> +Required SoC Specific Properties:
> +- compatible: should be "brcm,bcm-keypad"
> +
> +- reg: physical base address of the controller and length of memory mapped
> +  region.
> +
> +- interrupts: The interrupt number to the cpu.
> +
> +Board Specific Properties:
> +- keypad,num-rows: Number of row lines connected to the keypad
> +  controller.
> +
> +- keypad,num-columns: Number of column lines connected to the
> +  keypad controller.
> +
> +- col-debounce-filter-period: The debounce period for the Column filter.
> +
> +	KEYPAD_DEBOUNCE_1_ms	=	0
> +	KEYPAD_DEBOUNCE_2_ms	=	1
> +	KEYPAD_DEBOUNCE_4_ms	=	2
> +	KEYPAD_DEBOUNCE_8_ms	=	3
> +	KEYPAD_DEBOUNCE_16_ms	=	4
> +	KEYPAD_DEBOUNCE_32_ms	=	5
> +	KEYPAD_DEBOUNCE_64_ms	=	6
> +	KEYPAD_DEBOUNCE_128_ms	=	7
> +
> +- status-debounce-filter-period: The debounce period for the Status filter.
> +
> +	KEYPAD_DEBOUNCE_1_ms	=	0
> +	KEYPAD_DEBOUNCE_2_ms	=	1
> +	KEYPAD_DEBOUNCE_4_ms	=	2
> +	KEYPAD_DEBOUNCE_8_ms	=	3
> +	KEYPAD_DEBOUNCE_16_ms	=	4
> +	KEYPAD_DEBOUNCE_32_ms	=	5
> +	KEYPAD_DEBOUNCE_64_ms	=	6
> +	KEYPAD_DEBOUNCE_128_ms	=	7
> +
> +- row-output-enabled: An optional property indicating whether the row or
> +  column is being used as output. If specified the row is being used
> +  as the output. Else defaults to column.
> +
> +- pull-up-enabled: An optional property indicating the Keypad scan mode.
> +  If specified implies the keypad scan pull-up has been enabled.
> +
> +- autorepeat: Boolean, Enable auto repeat feature of Linux input
> +	  subsystem (optional).
> +
> +- linux,keymap: The keymap for keys as described in the binding document
> +  devicetree/bindings/input/matrix-keymap.txt.
> +
> +Example:
> +#include "dt-bindings/input/input.h"
> +
> +/ {
> +	keypad: keypad@180ac000 {
> +		/* Required SoC specific properties */
> +		compatible = "brcm,bcm-keypad";
> +
> +		/* Required Board specific properties */
> +		keypad,num-rows = <5>;
> +		keypad,num-columns = <5>;
> +		status = "okay";
> +
> +		linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_F) /* key_forward */
> +		MATRIX_KEY(0x00, 0x03, KEY_HOME) /* key_home */
> +		MATRIX_KEY(0x00, 0x04, KEY_M) /* key_message */
> +		MATRIX_KEY(0x01, 0x00, KEY_A) /* key_contacts */
> +		MATRIX_KEY(0x01, 0x01, KEY_1) /* key_1 */
> +		MATRIX_KEY(0x01, 0x02, KEY_2) /* key_2 */
> +		MATRIX_KEY(0x01, 0x03, KEY_3) /* key_3 */
> +		MATRIX_KEY(0x01, 0x04, KEY_S) /* key_speaker */
> +		MATRIX_KEY(0x02, 0x00, KEY_P) /* key_phone */
> +		MATRIX_KEY(0x02, 0x01, KEY_4) /* key_4 */
> +		MATRIX_KEY(0x02, 0x02, KEY_5) /* key_5 */
> +		MATRIX_KEY(0x02, 0x03, KEY_6) /* key_6 */
> +		MATRIX_KEY(0x02, 0x04, KEY_VOLUMEUP) /* key_vol_up */
> +		MATRIX_KEY(0x03, 0x00, KEY_C) /* key_call_log */
> +		MATRIX_KEY(0x03, 0x01, KEY_7) /* key_7 */
> +		MATRIX_KEY(0x03, 0x02, KEY_8) /* key_8 */
> +		MATRIX_KEY(0x03, 0x03, KEY_9) /* key_9 */
> +		MATRIX_KEY(0x03, 0x04, KEY_VOLUMEDOWN) /* key_vol_down */
> +		MATRIX_KEY(0x04, 0x00, KEY_H) /* key_headset */
> +		MATRIX_KEY(0x04, 0x01, KEY_KPASTERISK) /* key_* */
> +		MATRIX_KEY(0x04, 0x02, KEY_0) /* key_0 */
> +		MATRIX_KEY(0x04, 0x03, KEY_GRAVE) /* key_# */
> +		MATRIX_KEY(0x04, 0x04, KEY_MUTE) /* key_mute */
> +		>;
> +
> +		/* Optional board specific properties */
> +		col-debounce-filter-period = <5>;
> +		row-output-enabled;
> +		pull-up-enabled;
> +
> +	};
> +};
> -- 
> 2.3.0
> 

-- 
Dmitry

Re: [PATCH v2 2/2] hwrng: iproc-rng200 - Add Broadcom IPROC RNG driver

[Scott Branden]

Hi Dmitry,

Looking at the driver based on your comments it is following models of 
older hwrng drivers.  I will work on cleaning up based on your comments 
as well.

On 15-02-25 10:43 AM, Dmitry Torokhov wrote:
> Hi Scott,
>
> On Wed, Feb 25, 2015 at 10:16:24AM -0800, Scott Branden wrote:
>> This adds a driver for random number generator present on Broadcom
>> IPROC devices.
>>
>> Reviewed-by: Ray Jui <rjui@broadcom.com>
>> Signed-off-by: Scott Branden <sbranden@broadcom.com>
>> ---
>>   drivers/char/hw_random/Kconfig        |  13 ++
>>   drivers/char/hw_random/Makefile       |   1 +
>>   drivers/char/hw_random/iproc-rng200.c | 239 ++++++++++++++++++++++++++++++++++
>>   3 files changed, 253 insertions(+)
>>   create mode 100644 drivers/char/hw_random/iproc-rng200.c
>>
>> diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
>> index de57b38..f48cf11 100644
>> --- a/drivers/char/hw_random/Kconfig
>> +++ b/drivers/char/hw_random/Kconfig
>> @@ -101,6 +101,19 @@ config HW_RANDOM_BCM2835
>>
>>   	  If unsure, say Y.
>>
>> +config HW_RANDOM_IPROC_RNG200
>> +	tristate "Broadcom iProc RNG200 support"
>> +	depends on ARCH_BCM_IPROC
>> +	default HW_RANDOM
>> +	---help---
>> +	  This driver provides kernel-side support for the RNG200
>> +	  hardware found on the Broadcom iProc SoCs.
>> +
>> +	  To compile this driver as a module, choose M here: the
>> +	  module will be called iproc-rng200
>> +
>> +	  If unsure, say Y.
>> +
>>   config HW_RANDOM_GEODE
>>   	tristate "AMD Geode HW Random Number Generator support"
>>   	depends on X86_32 && PCI
>> diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
>> index 0b4cd57..055bb01 100644
>> --- a/drivers/char/hw_random/Makefile
>> +++ b/drivers/char/hw_random/Makefile
>> @@ -28,5 +28,6 @@ obj-$(CONFIG_HW_RANDOM_POWERNV) += powernv-rng.o
>>   obj-$(CONFIG_HW_RANDOM_EXYNOS)	+= exynos-rng.o
>>   obj-$(CONFIG_HW_RANDOM_TPM) += tpm-rng.o
>>   obj-$(CONFIG_HW_RANDOM_BCM2835) += bcm2835-rng.o
>> +obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) += iproc-rng200.o
>>   obj-$(CONFIG_HW_RANDOM_MSM) += msm-rng.o
>>   obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o
>> diff --git a/drivers/char/hw_random/iproc-rng200.c b/drivers/char/hw_random/iproc-rng200.c
>> new file mode 100644
>> index 0000000..4643aa9
>> --- /dev/null
>> +++ b/drivers/char/hw_random/iproc-rng200.c
>> @@ -0,0 +1,239 @@
>> +/*
>> +* Copyright (C) 2014 Broadcom Corporation
>> +*
>> +* This program is free software; you can redistribute it and/or
>> +* modify it under the terms of the GNU General Public License as
>> +* published by the Free Software Foundation version 2.
>> +*
>> +* This program is distributed "as is" WITHOUT ANY WARRANTY of any
>> +* kind, whether express or implied; without even the implied warranty
>> +* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> +* GNU General Public License for more details.
>> +*/
>> +/*
>> + * DESCRIPTION: The Broadcom iProc RNG200 Driver
>> + */
>> +
>> +#include <linux/hw_random.h>
>> +#include <linux/init.h>
>> +#include <linux/io.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of_address.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/delay.h>
>> +
>> +
>> +/* Registers */
>> +#define RNG_CTRL_OFFSET					0x00
>> +#define RNG_CTRL_RNG_RBGEN_MASK				0x00001FFF
>> +#define RNG_CTRL_RNG_RBGEN_ENABLE			0x00000001
>> +#define RNG_CTRL_RNG_RBGEN_DISABLE			0x00000000
>> +
>> +#define RNG_SOFT_RESET_OFFSET				0x04
>> +#define RNG_SOFT_RESET_RNG_SOFT_RESET_MASK		0x00000001
>> +#define RNG_SOFT_RESET_RNG_SOFT_RESET_ACTIVE		0x00000001
>> +#define RNG_SOFT_RESET_RNG_SOFT_RESET_CLEAR		0x00000000
>> +
>> +#define RBG_SOFT_RESET_OFFSET				0x08
>> +#define RBG_SOFT_RESET_RNG_SOFT_RESET_MASK		0x00000001
>> +#define RBG_SOFT_RESET_RNG_SOFT_RESET_ACTIVE		0x00000001
>> +#define RBG_SOFT_RESET_RNG_SOFT_RESET_CLEAR		0x00000000
>> +
>> +#define RNG_INT_STATUS_OFFSET				0x18
>> +#define RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK	0x80000000
>> +#define RNG_INT_STATUS_STARTUP_TRANSITIONS_MET_IRQ_MASK	0x00020000
>> +#define RNG_INT_STATUS_NIST_FAIL_IRQ_MASK		0x00000020
>> +#define RNG_INT_STATUS_TOTAL_BITS_COUNT_IRQ_MASK	0x00000001
>> +
>> +#define RNG_FIFO_DATA_OFFSET				0x20
>> +
>> +#define RNG_FIFO_COUNT_OFFSET				0x24
>> +#define RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK		0x000000FF
>> +
>> +static void iproc_rng200_restart(void __iomem *rng_base)
>> +{
>> +	uint32_t val;
>> +
>> +	/* Disable RBG */
>> +	val = ioread32(rng_base + RNG_CTRL_OFFSET);
>> +	val &= ~RNG_CTRL_RNG_RBGEN_MASK;
>> +	val |= RNG_CTRL_RNG_RBGEN_DISABLE;
>> +	iowrite32(val, rng_base + RNG_CTRL_OFFSET);
>> +
>> +	/* Clear all interrupt status */
>> +	iowrite32(0xFFFFFFFFUL, rng_base + RNG_INT_STATUS_OFFSET);
>> +
>> +	/* Reset RNG and RBG */
>> +	val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
>> +	val &= ~RBG_SOFT_RESET_RNG_SOFT_RESET_MASK;
>> +	val |= RBG_SOFT_RESET_RNG_SOFT_RESET_ACTIVE;
>> +	iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
>> +
>> +	val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
>> +	val &= ~RNG_SOFT_RESET_RNG_SOFT_RESET_MASK;
>> +	val |= RNG_SOFT_RESET_RNG_SOFT_RESET_ACTIVE;
>> +	iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
>> +
>> +	val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
>> +	val &= ~RNG_SOFT_RESET_RNG_SOFT_RESET_MASK;
>> +	val |= RNG_SOFT_RESET_RNG_SOFT_RESET_CLEAR;
>> +	iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
>> +
>> +	val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
>> +	val &= ~RBG_SOFT_RESET_RNG_SOFT_RESET_MASK;
>> +	val |= RBG_SOFT_RESET_RNG_SOFT_RESET_CLEAR;
>> +	iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
>> +
>> +	/* Enable RBG */
>> +	val = ioread32(rng_base + RNG_CTRL_OFFSET);
>> +	val &= ~RNG_CTRL_RNG_RBGEN_MASK;
>> +	val |= RNG_CTRL_RNG_RBGEN_ENABLE;
>> +	iowrite32(val, rng_base + RNG_CTRL_OFFSET);
>> +}
>> +
>> +static int iproc_rng200_read(struct hwrng *rng, void *buf, size_t max,
>> +			       bool wait)
>> +{
>> +	uint32_t status = 0;
>> +	uint32_t num_remaining = max;
>> +
>> +	#define MAX_RESETS_PER_READ	1
>> +	uint32_t num_resets = 0;
>> +
>> +	#define MAX_IDLE_TIME	(1 * HZ)
>> +	unsigned long idle_endtime = jiffies + MAX_IDLE_TIME;
>> +
>> +	/* Retrieve HW RNG registers base address. */
>> +	void __iomem *rng_base = (void __iomem *)rng->priv;
>> +
>> +	while ((num_remaining > 0) && time_before(jiffies, idle_endtime)) {
>> +
>> +		/* Is RNG sane? If not, reset it. */
>> +		status = ioread32(rng_base + RNG_INT_STATUS_OFFSET);
>> +		if ((status & (RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK |
>> +			RNG_INT_STATUS_NIST_FAIL_IRQ_MASK)) != 0) {
>> +
>> +			if (num_resets >= MAX_RESETS_PER_READ)
>> +				return max - num_remaining;
>> +
>> +			iproc_rng200_restart(rng_base);
>> +			num_resets++;
>> +		}
>> +
>> +		/* Are there any random numbers available? */
>> +		if ((ioread32(rng_base + RNG_FIFO_COUNT_OFFSET) &
>> +				RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK) > 0) {
>> +
>> +			if (num_remaining >= sizeof(uint32_t)) {
>> +				/* Buffer has room to store entire word */
>> +				*(uint32_t *)buf = ioread32(rng_base +
>> +							RNG_FIFO_DATA_OFFSET);
>> +				buf += sizeof(uint32_t);
>> +				num_remaining -= sizeof(uint32_t);
>> +			} else {
>> +				/* Buffer can only store partial word */
>> +				uint32_t rnd_number = ioread32(rng_base +
>> +							RNG_FIFO_DATA_OFFSET);
>> +				memcpy(buf, &rnd_number, num_remaining);
>> +				buf += num_remaining;
>> +				num_remaining = 0;
>> +			}
>> +
>> +			/* Reset the IDLE timeout */
>> +			idle_endtime = jiffies + MAX_IDLE_TIME;
>> +		} else {
>> +			if (!wait)
>> +				/* Cannot wait, return immediately */
>> +				return max - num_remaining;
>> +
>> +			/* Can wait, give others chance to run */
>> +			cpu_relax();
>> +		}
>> +	}
>> +
>> +	return max - num_remaining;
>> +}
>> +
>> +static struct hwrng iproc_rng200_ops = {
>> +	.name	= "iproc-rng200",
>> +	.read	= iproc_rng200_read,
>> +};
>
> I would prefer if we allocated a driver-private structure that wraps
> hwrng instead of using statically allocated singleton as I wonder how it
> will behave if I bind/unbind the device several times.
ok, will revamp.
>
>> +
>> +static int iproc_rng200_probe(struct platform_device *pdev)
>> +{
>> +	struct device *dev = &pdev->dev;
>> +	void __iomem *rng_base = 0;
>> +	uint32_t val = 0;
>> +	int err = 0;
>
> There is no need to initialize all variables as it suppressed "used but
> uninitialized" warnings from the compiler. Imagine someone adding a new
> init operation and when they handle failure they forget to adjust error
> code so it stays 0: for upper layers we'd signal success even though
> our device/driver are half-bound.
yes, will cleanup in other functions as well.
>
>> +
>> +	/* Map peripheral */
>> +	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +
>> +	if (!res) {
>> +		dev_err(dev, "failed to get rng resources\n");
>> +		return -ENODEV;
>
> If we have platform device but it is missing parts of necessary data it
> should be -EINVAL.
ok
>
>> +	}
>> +
>> +	rng_base = devm_ioremap_resource(dev, res);
>> +	if (!rng_base) {
>
> devm_ioremap_resource() returns ERR_PTR-encoded result, you need to
> check with IS_ERR().
ok
>
>> +		dev_err(dev, "failed to remap rng regs\n");
>> +		return -ENODEV;
>
> 		return PTR_ERR(rng_base);
ok
>
>> +	}
>
> There is no clock for RNG?
no additional clock needs to be enabled.
>
>> +
>> +	iproc_rng200_ops.priv = (unsigned long)rng_base;
>> +
>> +	/* Setup RNG. */
>> +	val = ioread32(rng_base + RNG_CTRL_OFFSET);
>> +	val &= ~RNG_CTRL_RNG_RBGEN_MASK;
>> +	val |= RNG_CTRL_RNG_RBGEN_ENABLE;
>> +	iowrite32(val, rng_base + RNG_CTRL_OFFSET);
>
> That should be in [new] iproc_rng200_init().
ok, it looks like you are commenting based on what is done in omap-rng. 
  I can follow that model and move this into an init function.
>
>> +
>> +	/* Register driver */
>> +	err = hwrng_register(&iproc_rng200_ops);
>> +	if (err) {
>> +		dev_err(dev, "hwrng registration failed\n");
>> +		return err;
>> +	}
>> +	dev_info(dev, "hwrng registered\n");
>> +
>> +	return 0;
>> +}
>> +
>> +static int iproc_rng200_remove(struct platform_device *pdev)
>> +{
>> +	uint32_t val = 0;
>> +	void __iomem *rng_base = (void __iomem *)iproc_rng200_ops.priv;
>> +
>> +	/* Unregister driver */
>> +	hwrng_unregister(&iproc_rng200_ops);
>> +
>> +	/* Disable RNG hardware */
>> +	val = ioread32(rng_base + RNG_CTRL_OFFSET);
>> +	val &= ~RNG_CTRL_RNG_RBGEN_MASK;
>> +	val |= RNG_CTRL_RNG_RBGEN_DISABLE;
>> +	iowrite32(val, rng_base + RNG_CTRL_OFFSET);
>
> That should be in [new] iproc_rng200_cleanup().
ok, it looks like you are commenting based on what is done in omap-rng.

I can follow that model and move this into a cleanup function.
>
>> +
>> +	return 0;
>> +}
>> +
>
> #ifdef CONFIG_OF
>
> maybe?
driver will only be used with devicetree
>
>> +static const struct of_device_id iproc_rng200_of_match[] = {
>> +	{ .compatible = "brcm,iproc-rng200", },
>> +	{},
>> +};
>> +MODULE_DEVICE_TABLE(of, iproc_rng200_of_match);
>> +
>> +static struct platform_driver iproc_rng200_driver = {
>> +	.driver = {
>> +		.name = "iproc-rng200",
>> +		.of_match_table = iproc_rng200_of_match,
>> +	},
>> +	.probe		= iproc_rng200_probe,
>> +	.remove		= iproc_rng200_remove,
>> +};
>> +module_platform_driver(iproc_rng200_driver);
>> +
>> +MODULE_AUTHOR("Broadcom");
>> +MODULE_DESCRIPTION("iProc RNG200 Random Number Generator driver");
>> +MODULE_LICENSE("GPL v2");
>> --
>> 2.3.0
>>
>
> Thanks.
>

[PATCH v3 0/2] Add support for Broadcom RNG200

[Scott Branden]

This series of patchsets contains the Broadcom Random Number Generator
driver and device tree binding documentation.

Changes from v2:
 added usleep_range instead of cpu_relax
 add init and cleanup functions following new hwrng model
 
Changes from v1:
 added \n to 2 dev_err messages

Scott Branden (2):
  hwrng: iproc-rng200 - Add device tree bindings
  hwrng: iproc-rng200 - Add Broadcom IPROC RNG driver

 .../bindings/hwrng/brcm,iproc-rng200.txt           |  12 +
 drivers/char/hw_random/Kconfig                     |  13 ++
 drivers/char/hw_random/Makefile                    |   1 +
 drivers/char/hw_random/iproc-rng200.c              | 254 +++++++++++++++++++++
 4 files changed, 280 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwrng/brcm,iproc-rng200.txt
 create mode 100644 drivers/char/hw_random/iproc-rng200.c

-- 
2.3.0

[PATCH v3 1/2] hwrng: iproc-rng200 - Add device tree bindings

[Scott Branden]

Documents the IPROC random number generator device tree bindings
used in some Broadcom chipsets.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 .../devicetree/bindings/hwrng/brcm,iproc-rng200.txt          | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwrng/brcm,iproc-rng200.txt

diff --git a/Documentation/devicetree/bindings/hwrng/brcm,iproc-rng200.txt b/Documentation/devicetree/bindings/hwrng/brcm,iproc-rng200.txt
new file mode 100644
index 0000000..e25a456
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwrng/brcm,iproc-rng200.txt
@@ -0,0 +1,12 @@
+HWRNG support for the iproc-rng200 driver
+
+Required properties:
+- compatible : "brcm,iproc-rng200"
+- reg : base address and size of control register block
+
+Example:
+
+rng {
+        compatible = "brcm,iproc-rng200";
+        reg = <0x18032000 0x28>;
+};
-- 
2.3.0

[PATCH v3 2/2] hwrng: iproc-rng200 - Add Broadcom IPROC RNG driver

[Scott Branden]

This adds a driver for random number generator present on Broadcom
IPROC devices.

Reviewed-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/char/hw_random/Kconfig        |  13 ++
 drivers/char/hw_random/Makefile       |   1 +
 drivers/char/hw_random/iproc-rng200.c | 254 ++++++++++++++++++++++++++++++++++
 3 files changed, 268 insertions(+)
 create mode 100644 drivers/char/hw_random/iproc-rng200.c

diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index de57b38..f48cf11 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -101,6 +101,19 @@ config HW_RANDOM_BCM2835
 
 	  If unsure, say Y.
 
+config HW_RANDOM_IPROC_RNG200
+	tristate "Broadcom iProc RNG200 support"
+	depends on ARCH_BCM_IPROC
+	default HW_RANDOM
+	---help---
+	  This driver provides kernel-side support for the RNG200
+	  hardware found on the Broadcom iProc SoCs.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called iproc-rng200
+
+	  If unsure, say Y.
+
 config HW_RANDOM_GEODE
 	tristate "AMD Geode HW Random Number Generator support"
 	depends on X86_32 && PCI
diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
index 0b4cd57..055bb01 100644
--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
@@ -28,5 +28,6 @@ obj-$(CONFIG_HW_RANDOM_POWERNV) += powernv-rng.o
 obj-$(CONFIG_HW_RANDOM_EXYNOS)	+= exynos-rng.o
 obj-$(CONFIG_HW_RANDOM_TPM) += tpm-rng.o
 obj-$(CONFIG_HW_RANDOM_BCM2835) += bcm2835-rng.o
+obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) += iproc-rng200.o
 obj-$(CONFIG_HW_RANDOM_MSM) += msm-rng.o
 obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o
diff --git a/drivers/char/hw_random/iproc-rng200.c b/drivers/char/hw_random/iproc-rng200.c
new file mode 100644
index 0000000..276cb8a
--- /dev/null
+++ b/drivers/char/hw_random/iproc-rng200.c
@@ -0,0 +1,254 @@
+/*
+* Copyright (C) 2015 Broadcom Corporation
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation version 2.
+*
+* This program is distributed "as is" WITHOUT ANY WARRANTY of any
+* kind, whether express or implied; without even the implied warranty
+* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*/
+/*
+ * DESCRIPTION: The Broadcom iProc RNG200 Driver
+ */
+
+#include <linux/hw_random.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+
+/* Registers */
+#define RNG_CTRL_OFFSET					0x00
+#define RNG_CTRL_RNG_RBGEN_MASK				0x00001FFF
+#define RNG_CTRL_RNG_RBGEN_ENABLE			0x00000001
+#define RNG_CTRL_RNG_RBGEN_DISABLE			0x00000000
+
+#define RNG_SOFT_RESET_OFFSET				0x04
+#define RNG_SOFT_RESET					0x00000001
+
+#define RBG_SOFT_RESET_OFFSET				0x08
+#define RBG_SOFT_RESET					0x00000001
+
+#define RNG_INT_STATUS_OFFSET				0x18
+#define RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK	0x80000000
+#define RNG_INT_STATUS_STARTUP_TRANSITIONS_MET_IRQ_MASK	0x00020000
+#define RNG_INT_STATUS_NIST_FAIL_IRQ_MASK		0x00000020
+#define RNG_INT_STATUS_TOTAL_BITS_COUNT_IRQ_MASK	0x00000001
+
+#define RNG_FIFO_DATA_OFFSET				0x20
+
+#define RNG_FIFO_COUNT_OFFSET				0x24
+#define RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK		0x000000FF
+
+struct iproc_rng200_dev {
+	void __iomem			*base;
+};
+
+static void iproc_rng200_restart(void __iomem *rng_base)
+{
+	uint32_t val;
+
+	/* Disable RBG */
+	val = ioread32(rng_base + RNG_CTRL_OFFSET);
+	val &= ~RNG_CTRL_RNG_RBGEN_MASK;
+	val |= RNG_CTRL_RNG_RBGEN_DISABLE;
+	iowrite32(val, rng_base + RNG_CTRL_OFFSET);
+
+	/* Clear all interrupt status */
+	iowrite32(0xFFFFFFFFUL, rng_base + RNG_INT_STATUS_OFFSET);
+
+	/* Reset RNG and RBG */
+	val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
+	val |= RBG_SOFT_RESET;
+	iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
+
+	val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
+	val |= RNG_SOFT_RESET;
+	iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
+
+	val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET);
+	val &= ~RNG_SOFT_RESET;
+	iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET);
+
+	val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET);
+	val &= ~RBG_SOFT_RESET;
+	iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET);
+
+	/* Enable RBG */
+	val = ioread32(rng_base + RNG_CTRL_OFFSET);
+	val &= ~RNG_CTRL_RNG_RBGEN_MASK;
+	val |= RNG_CTRL_RNG_RBGEN_ENABLE;
+	iowrite32(val, rng_base + RNG_CTRL_OFFSET);
+}
+
+static int iproc_rng200_read(struct hwrng *rng, void *buf, size_t max,
+			       bool wait)
+{
+	uint32_t status;
+	uint32_t num_remaining = max;
+	struct iproc_rng200_dev *priv = (struct iproc_rng200_dev *)rng->priv;
+
+	#define MAX_RESETS_PER_READ	1
+	uint32_t num_resets = 0;
+
+	#define MAX_IDLE_TIME	(1 * HZ)
+	unsigned long idle_endtime = jiffies + MAX_IDLE_TIME;
+
+	while ((num_remaining > 0) && time_before(jiffies, idle_endtime)) {
+
+		/* Is RNG sane? If not, reset it. */
+		status = ioread32(priv->base + RNG_INT_STATUS_OFFSET);
+		if ((status & (RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK |
+			RNG_INT_STATUS_NIST_FAIL_IRQ_MASK)) != 0) {
+
+			if (num_resets >= MAX_RESETS_PER_READ)
+				return max - num_remaining;
+
+			iproc_rng200_restart(priv->base);
+			num_resets++;
+		}
+
+		/* Are there any random numbers available? */
+		if ((ioread32(priv->base + RNG_FIFO_COUNT_OFFSET) &
+				RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK) > 0) {
+
+			if (num_remaining >= sizeof(uint32_t)) {
+				/* Buffer has room to store entire word */
+				*(uint32_t *)buf = ioread32(priv->base +
+							RNG_FIFO_DATA_OFFSET);
+				buf += sizeof(uint32_t);
+				num_remaining -= sizeof(uint32_t);
+			} else {
+				/* Buffer can only store partial word */
+				uint32_t rnd_number = ioread32(priv->base +
+							RNG_FIFO_DATA_OFFSET);
+				memcpy(buf, &rnd_number, num_remaining);
+				buf += num_remaining;
+				num_remaining = 0;
+			}
+
+			/* Reset the IDLE timeout */
+			idle_endtime = jiffies + MAX_IDLE_TIME;
+		} else {
+			if (!wait)
+				/* Cannot wait, return immediately */
+				return max - num_remaining;
+
+			/* Can wait, give others chance to run */
+			usleep_range(min(num_remaining * 10, 500U), 500);
+		}
+	}
+
+	return max - num_remaining;
+}
+
+static int iproc_rng200_init(struct hwrng *rng)
+{
+	uint32_t val;
+	struct iproc_rng200_dev *priv;
+
+	priv = (struct iproc_rng200_dev *)rng->priv;
+
+	/* Setup RNG. */
+	val = ioread32(priv->base + RNG_CTRL_OFFSET);
+	val &= ~RNG_CTRL_RNG_RBGEN_MASK;
+	val |= RNG_CTRL_RNG_RBGEN_ENABLE;
+	iowrite32(val, priv->base + RNG_CTRL_OFFSET);
+
+	return 0;
+}
+
+static void iproc_rng200_cleanup(struct hwrng *rng)
+{
+	uint32_t val;
+	struct iproc_rng200_dev *priv;
+
+	priv = (struct iproc_rng200_dev *)rng->priv;
+
+	/* Disable RNG hardware */
+	val = ioread32(priv->base + RNG_CTRL_OFFSET);
+	val &= ~RNG_CTRL_RNG_RBGEN_MASK;
+	val |= RNG_CTRL_RNG_RBGEN_DISABLE;
+	iowrite32(val, priv->base + RNG_CTRL_OFFSET);
+}
+
+static struct hwrng iproc_rng200_ops = {
+	.name		= "iproc-rng200",
+	.read		= iproc_rng200_read,
+	.init		= iproc_rng200_init,
+	.cleanup	= iproc_rng200_cleanup,
+};
+
+static int iproc_rng200_probe(struct platform_device *pdev)
+{
+	struct iproc_rng200_dev *priv;
+	struct resource *res;
+	struct device *dev = &pdev->dev;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(struct iproc_rng200_dev), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	iproc_rng200_ops.priv = (unsigned long)priv;
+	platform_set_drvdata(pdev, priv);
+
+	/* Map peripheral */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(dev, "failed to get rng resources\n");
+		return -EINVAL;
+	}
+
+	priv->base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(priv->base)) {
+		dev_err(dev, "failed to remap rng regs\n");
+		return PTR_ERR(priv->base);
+	}
+
+	/* Register driver */
+	ret = hwrng_register(&iproc_rng200_ops);
+	if (ret) {
+		dev_err(dev, "hwrng registration failed\n");
+		return ret;
+	}
+
+	dev_info(dev, "hwrng registered\n");
+
+	return 0;
+}
+
+static int iproc_rng200_remove(struct platform_device *pdev)
+{
+	/* Unregister driver */
+	hwrng_unregister(&iproc_rng200_ops);
+
+	return 0;
+}
+
+static const struct of_device_id iproc_rng200_of_match[] = {
+	{ .compatible = "brcm,iproc-rng200", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, iproc_rng200_of_match);
+
+static struct platform_driver iproc_rng200_driver = {
+	.driver = {
+		.name		= "iproc-rng200",
+		.of_match_table = iproc_rng200_of_match,
+	},
+	.probe		= iproc_rng200_probe,
+	.remove		= iproc_rng200_remove,
+};
+module_platform_driver(iproc_rng200_driver);
+
+MODULE_AUTHOR("Broadcom");
+MODULE_DESCRIPTION("iProc RNG200 Random Number Generator driver");
+MODULE_LICENSE("GPL v2");
-- 
2.3.0

Re: [PATCH 4/4] mmc: sdhci-iproc: add device tree bindings

[Scott Branden]

Hi Florian,

On 15-03-02 03:50 PM, Florian Fainelli wrote:
>
> Unless there is a re-spin, I will fix this myself while applying this
> patch to devicetree/next.
>
> Thanks
>
Yes, you can patch the formatting if the driver is being integrated. 
But I have had no response or feedback on the sdhci driver.  It has been 
sitting for 1 month.

[PATCH RESEND 0/4] Add support for IPROC SDHCI controller

[Scott Branden]

This series of patchsets contains the IPROC SDHCI driver used
in a series of Broadcom SoCs
Quirks are also added to support this controller.

Corneliu Doban (1):
  mmc: sdhci: do not set AUTO_CMD12 for multi-block CMD53

Scott Branden (3):
  mmc: sdhci: add quirk for ACMD23 broken
  mmc: sdhci-iproc: add IPROC SDHCI driver
  mmc: sdhci-iproc: add device tree bindings

 .../devicetree/bindings/mmc/brcm,sdhci-iproc.txt   |  23 ++
 drivers/mmc/host/Kconfig                           |  14 ++
 drivers/mmc/host/Makefile                          |   1 +
 drivers/mmc/host/sdhci-iproc.c                     | 241 +++++++++++++++++++++
 drivers/mmc/host/sdhci.c                           |   7 +-
 include/linux/mmc/sdhci.h                          |   2 +
 6 files changed, 286 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt
 create mode 100644 drivers/mmc/host/sdhci-iproc.c

-- 
2.2.2

[PATCH 1/4] mmc: sdhci: add quirk for ACMD23 broken

[Scott Branden]

Add quirk to handle broken auto-CMD23.
Some controllers do not respond after the first auto-CMD23 is issued.

This allows CMD23 to still work (mandatory for the faster UHS-I mode)
rather than disabling CMD23 entirely via SDHCI_QUIRK2_HOST_NO_CMD23.

Signed-off by: Corneliu Doban <cdoban@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>

Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/mmc/host/sdhci.c  | 3 ++-
 include/linux/mmc/sdhci.h | 2 ++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index f1a488e..fcf78ab 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -3085,7 +3085,8 @@ int sdhci_add_host(struct sdhci_host *host)
 	/* Auto-CMD23 stuff only works in ADMA or PIO. */
 	if ((host->version >= SDHCI_SPEC_300) &&
 	    ((host->flags & SDHCI_USE_ADMA) ||
-	     !(host->flags & SDHCI_USE_SDMA))) {
+	     !(host->flags & SDHCI_USE_SDMA)) &&
+	     !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
 		host->flags |= SDHCI_AUTO_CMD23;
 		DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
 	} else {
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index f767a0d..a29e9bb 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -106,6 +106,8 @@ struct sdhci_host {
 #define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD	(1<<10)
 /* Capability register bit-63 indicates HS400 support */
 #define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400		(1<<11)
+/* Controller broken with using ACMD23 */
+#define SDHCI_QUIRK2_ACMD23_BROKEN			(1<<12)
 
 	int irq;		/* Device IRQ */
 	void __iomem *ioaddr;	/* Mapped address */
-- 
2.2.2

[PATCH 2/4] mmc: sdhci: do not set AUTO_CMD12 for multi-block CMD53

[Scott Branden]

From: Corneliu Doban <cdoban@broadcom.com>

For CMD53 in block mode, the host does not need to stop the transfer,
as it stops when the block count (present in CMD53) is reached.

Signed-off-by: Corneliu Doban <cdoban@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/mmc/host/sdhci.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index fcf78ab..f35d413 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -28,6 +28,7 @@
 #include <linux/mmc/mmc.h>
 #include <linux/mmc/host.h>
 #include <linux/mmc/card.h>
+#include <linux/mmc/sdio.h>
 #include <linux/mmc/slot-gpio.h>
 
 #include "sdhci.h"
@@ -934,7 +935,8 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host,
 		 * If we are sending CMD23, CMD12 never gets sent
 		 * on successful completion (so no Auto-CMD12).
 		 */
-		if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
+		if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
+		    (cmd->opcode != SD_IO_RW_EXTENDED))
 			mode |= SDHCI_TRNS_AUTO_CMD12;
 		else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 			mode |= SDHCI_TRNS_AUTO_CMD23;
-- 
2.2.2

[PATCH 3/4] mmc: sdhci-iproc: add IPROC SDHCI driver

[Scott Branden]

Add IPROC SDHCI driver for IPROC family of Broadcom devices.

Acked-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Corneliu Doban <cdoban@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/mmc/host/Kconfig       |  14 +++
 drivers/mmc/host/Makefile      |   1 +
 drivers/mmc/host/sdhci-iproc.c | 241 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 256 insertions(+)
 create mode 100644 drivers/mmc/host/sdhci-iproc.c

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 2d6fbdd..d6a2ff1 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -292,6 +292,20 @@ config MMC_SDHCI_BCM2835
 
 	  If unsure, say N.
 
+config MMC_SDHCI_IPROC
+	tristate "SDHCI platform support for the iProc SD/MMC Controller"
+	depends on ARCH_BCM_IPROC || COMPILE_TEST
+	depends on MMC_SDHCI_PLTFM
+	default ARCH_BCM_IPROC
+	select MMC_SDHCI_IO_ACCESSORS
+	help
+	  This selects the iProc SD/MMC controller.
+
+	  If you have an IPROC platform with SD or MMC devices,
+	  say Y or M here.
+
+	  If unsure, say N.
+
 config MMC_MOXART
 	tristate "MOXART SD/MMC Host Controller support"
 	depends on ARCH_MOXART && MMC
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index f7b0a77..32f24bd 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -70,6 +70,7 @@ obj-$(CONFIG_MMC_SDHCI_OF_ESDHC)	+= sdhci-of-esdhc.o
 obj-$(CONFIG_MMC_SDHCI_OF_HLWD)		+= sdhci-of-hlwd.o
 obj-$(CONFIG_MMC_SDHCI_BCM_KONA)	+= sdhci-bcm-kona.o
 obj-$(CONFIG_MMC_SDHCI_BCM2835)		+= sdhci-bcm2835.o
+obj-$(CONFIG_MMC_SDHCI_IPROC)		+= sdhci-iproc.o
 obj-$(CONFIG_MMC_SDHCI_MSM)		+= sdhci-msm.o
 obj-$(CONFIG_MMC_SDHCI_ST)		+= sdhci-st.o
 
diff --git a/drivers/mmc/host/sdhci-iproc.c b/drivers/mmc/host/sdhci-iproc.c
new file mode 100644
index 0000000..4139d34
--- /dev/null
+++ b/drivers/mmc/host/sdhci-iproc.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (C) 2014 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * iProc SDHCI platform driver
+ */
+
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/mmc/host.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include "sdhci-pltfm.h"
+
+struct sdhci_iproc_data {
+	const struct sdhci_pltfm_data *pdata;
+	u32 caps;
+	u32 caps1;
+};
+
+struct sdhci_iproc_host {
+	const struct sdhci_iproc_data *data;
+	u32 shadow_cmd;
+	u32 shadow_blk;
+};
+
+#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
+
+static inline u32 sdhci_iproc_readl(struct sdhci_host *host, int reg)
+{
+	u32 val = readl(host->ioaddr + reg);
+
+	pr_debug("%s: readl [0x%02x] 0x%08x\n",
+		 mmc_hostname(host->mmc), reg, val);
+	return val;
+}
+
+static u16 sdhci_iproc_readw(struct sdhci_host *host, int reg)
+{
+	u32 val = sdhci_iproc_readl(host, (reg & ~3));
+	u16 word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
+	return word;
+}
+
+static u8 sdhci_iproc_readb(struct sdhci_host *host, int reg)
+{
+	u32 val = sdhci_iproc_readl(host, (reg & ~3));
+	u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
+	return byte;
+}
+
+static inline void sdhci_iproc_writel(struct sdhci_host *host, u32 val, int reg)
+{
+	pr_debug("%s: writel [0x%02x] 0x%08x\n",
+		 mmc_hostname(host->mmc), reg, val);
+
+	writel(val, host->ioaddr + reg);
+
+	if (host->clock <= 400000) {
+		/* Round up to micro-second four SD clock delay */
+		if (host->clock)
+			udelay((4 * 1000000 + host->clock - 1) / host->clock);
+		else
+			udelay(10);
+	}
+}
+
+/*
+ * The Arasan has a bugette whereby it may lose the content of successive
+ * writes to the same register that are within two SD-card clock cycles of
+ * each other (a clock domain crossing problem). The data
+ * register does not have this problem, which is just as well - otherwise we'd
+ * have to nobble the DMA engine too.
+ *
+ * This wouldn't be a problem with the code except that we can only write the
+ * controller with 32-bit writes.  So two different 16-bit registers are
+ * written back to back creates the problem.
+ *
+ * In reality, this only happens when SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT
+ * are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND.
+ * The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so
+ * the work around can be further optimized. We can keep shadow values of
+ * BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued.
+ * Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed
+ * by the TRANSFER+COMMAND in another 32-bit write.
+ */
+static void sdhci_iproc_writew(struct sdhci_host *host, u16 val, int reg)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct sdhci_iproc_host *iproc_host = pltfm_host->priv;
+	u32 word_shift = REG_OFFSET_IN_BITS(reg);
+	u32 mask = 0xffff << word_shift;
+	u32 oldval, newval;
+
+	if (reg == SDHCI_COMMAND) {
+		/* Write the block now as we are issuing a command */
+		if (iproc_host->shadow_blk != 0) {
+			sdhci_iproc_writel(host, iproc_host->shadow_blk,
+				SDHCI_BLOCK_SIZE);
+			iproc_host->shadow_blk = 0;
+		}
+		oldval = iproc_host->shadow_cmd;
+	} else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
+		/* Block size and count are stored in shadow reg */
+		oldval = iproc_host->shadow_blk;
+	} else {
+		/* Read reg, all other registers are not shadowed */
+		oldval = sdhci_iproc_readl(host, (reg & ~3));
+	}
+	newval = (oldval & ~mask) | (val << word_shift);
+
+	if (reg == SDHCI_TRANSFER_MODE) {
+		/* Save the transfer mode until the command is issued */
+		iproc_host->shadow_cmd = newval;
+	} else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
+		/* Save the block info until the command is issued */
+		iproc_host->shadow_blk = newval;
+	} else {
+		/* Command or other regular 32-bit write */
+		sdhci_iproc_writel(host, newval, reg & ~3);
+	}
+}
+
+static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg)
+{
+	u32 oldval = sdhci_iproc_readl(host, (reg & ~3));
+	u32 byte_shift = REG_OFFSET_IN_BITS(reg);
+	u32 mask = 0xff << byte_shift;
+	u32 newval = (oldval & ~mask) | (val << byte_shift);
+
+	sdhci_iproc_writel(host, newval, reg & ~3);
+}
+
+static const struct sdhci_ops sdhci_iproc_ops = {
+	.read_l = sdhci_iproc_readl,
+	.read_w = sdhci_iproc_readw,
+	.read_b = sdhci_iproc_readb,
+	.write_l = sdhci_iproc_writel,
+	.write_w = sdhci_iproc_writew,
+	.write_b = sdhci_iproc_writeb,
+	.set_clock = sdhci_set_clock,
+	.get_max_clock = sdhci_pltfm_clk_get_max_clock,
+	.set_bus_width = sdhci_set_bus_width,
+	.reset = sdhci_reset,
+	.set_uhs_signaling = sdhci_set_uhs_signaling,
+};
+
+static const struct sdhci_pltfm_data sdhci_iproc_pltfm_data = {
+	.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
+	.quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN,
+	.ops = &sdhci_iproc_ops,
+};
+
+static const struct sdhci_iproc_data iproc_data = {
+	.pdata = &sdhci_iproc_pltfm_data,
+	.caps = 0x05E90000,
+	.caps1 = 0x00000064,
+};
+
+static const struct of_device_id sdhci_iproc_of_match[] = {
+	{ .compatible = "brcm,sdhci-iproc-cygnus", .data = &iproc_data },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, sdhci_iproc_of_match);
+
+static int sdhci_iproc_probe(struct platform_device *pdev)
+{
+	const struct of_device_id *match;
+	const struct sdhci_iproc_data *iproc_data;
+	struct sdhci_host *host;
+	struct sdhci_iproc_host *iproc_host;
+	struct sdhci_pltfm_host *pltfm_host;
+	int ret;
+
+	match = of_match_device(sdhci_iproc_of_match, &pdev->dev);
+	if (!match)
+		return -EINVAL;
+	iproc_data = match->data;
+
+	host = sdhci_pltfm_init(pdev, iproc_data->pdata, sizeof(*iproc_host));
+	if (IS_ERR(host))
+		return PTR_ERR(host);
+
+	pltfm_host = sdhci_priv(host);
+	iproc_host = sdhci_pltfm_priv(pltfm_host);
+
+	iproc_host->data = iproc_data;
+
+	mmc_of_parse(host->mmc);
+	sdhci_get_of_property(pdev);
+
+	/* Enable EMMC 1/8V DDR capable */
+	host->mmc->caps |= MMC_CAP_1_8V_DDR;
+
+	pltfm_host->clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(pltfm_host->clk)) {
+		ret = PTR_ERR(pltfm_host->clk);
+		goto err;
+	}
+
+	if (iproc_host->data->pdata->quirks & SDHCI_QUIRK_MISSING_CAPS) {
+		host->caps = iproc_host->data->caps;
+		host->caps1 = iproc_host->data->caps1;
+	}
+
+	return sdhci_add_host(host);
+
+err:
+	sdhci_pltfm_free(pdev);
+	return ret;
+}
+
+static int sdhci_iproc_remove(struct platform_device *pdev)
+{
+	return sdhci_pltfm_unregister(pdev);
+}
+
+static struct platform_driver sdhci_iproc_driver = {
+	.driver = {
+		.name = "sdhci-iproc",
+		.of_match_table = sdhci_iproc_of_match,
+		.pm = SDHCI_PLTFM_PMOPS,
+	},
+	.probe = sdhci_iproc_probe,
+	.remove = sdhci_iproc_remove,
+};
+module_platform_driver(sdhci_iproc_driver);
+
+MODULE_AUTHOR("Broadcom");
+MODULE_DESCRIPTION("IPROC SDHCI driver");
+MODULE_LICENSE("GPL v2");
-- 
2.2.2

[PATCH 4/4] mmc: sdhci-iproc: add device tree bindings

[Scott Branden]

Add device tree binding documentation for IPROC SDHCI driver.

Acked-by: Ray Jui <rjui@broadcom.com>
Signed-off-by: Corneliu Doban <cdoban@broadcom.com>
Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 .../devicetree/bindings/mmc/brcm,sdhci-iproc.txt   | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt

diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt b/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt
new file mode 100644
index 0000000..72cc9cc
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt
@@ -0,0 +1,23 @@
+Broadcom IPROC SDHCI controller
+
+This file documents differences between the core properties described
+by mmc.txt and the properties that represent the IPROC SDHCI controller.
+
+Required properties:
+- compatible : Should be "brcm,sdhci-iproc-cygnus".
+- clocks : The clock feeding the SDHCI controller.
+
+Optional properties:
+  - sdhci,auto-cmd12: specifies that controller should use auto CMD12.
+
+Example:
+
+sdhci0: sdhci@0x18041000 {
+	compatible = "brcm,sdhci-iproc-cygnus";
+	reg = <0x18041000 0x100>;
+	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+	clocks = <&lcpll0_clks BCM_CYGNUS_LCPLL0_SDIO_CLK>;
+	bus-width = <4>;
+	sdhci,auto-cmd12;
+	no-1-8-v;
+};
-- 
2.2.2

Re: [PATCH RESEND 0/4] Add support for IPROC SDHCI controller

[Ulf Hansson]

On 5 March 2015 at 16:59, Scott Branden <sbranden@broadcom.com> wrote:
> This series of patchsets contains the IPROC SDHCI driver used
> in a series of Broadcom SoCs
> Quirks are also added to support this controller.
>
> Corneliu Doban (1):
>   mmc: sdhci: do not set AUTO_CMD12 for multi-block CMD53
>
> Scott Branden (3):
>   mmc: sdhci: add quirk for ACMD23 broken
>   mmc: sdhci-iproc: add IPROC SDHCI driver
>   mmc: sdhci-iproc: add device tree bindings
>
>  .../devicetree/bindings/mmc/brcm,sdhci-iproc.txt   |  23 ++
>  drivers/mmc/host/Kconfig                           |  14 ++
>  drivers/mmc/host/Makefile                          |   1 +
>  drivers/mmc/host/sdhci-iproc.c                     | 241 +++++++++++++++++++++
>  drivers/mmc/host/sdhci.c                           |   7 +-
>  include/linux/mmc/sdhci.h                          |   2 +
>  6 files changed, 286 insertions(+), 2 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt
>  create mode 100644 drivers/mmc/host/sdhci-iproc.c
>
> --
> 2.2.2
>

Applied, thanks!

Actually, I needed to re-solve some conflicts and I switched to order
of patch3 and patch4, to avoid checkpatch warnings. Just so you know.

Kind regards
Uffe

Re: [PATCH RESEND 0/4] Add support for IPROC SDHCI controller

[Florian Fainelli]

On 05/03/15 08:16, Ulf Hansson wrote:
> On 5 March 2015 at 16:59, Scott Branden <sbranden@broadcom.com> wrote:
>> This series of patchsets contains the IPROC SDHCI driver used
>> in a series of Broadcom SoCs
>> Quirks are also added to support this controller.
>>
>> Corneliu Doban (1):
>>   mmc: sdhci: do not set AUTO_CMD12 for multi-block CMD53
>>
>> Scott Branden (3):
>>   mmc: sdhci: add quirk for ACMD23 broken
>>   mmc: sdhci-iproc: add IPROC SDHCI driver
>>   mmc: sdhci-iproc: add device tree bindings
>>
>>  .../devicetree/bindings/mmc/brcm,sdhci-iproc.txt   |  23 ++
>>  drivers/mmc/host/Kconfig                           |  14 ++
>>  drivers/mmc/host/Makefile                          |   1 +
>>  drivers/mmc/host/sdhci-iproc.c                     | 241 +++++++++++++++++++++
>>  drivers/mmc/host/sdhci.c                           |   7 +-
>>  include/linux/mmc/sdhci.h                          |   2 +
>>  6 files changed, 286 insertions(+), 2 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt
>>  create mode 100644 drivers/mmc/host/sdhci-iproc.c
>>
>> --
>> 2.2.2
>>
> 
> Applied, thanks!
> 
> Actually, I needed to re-solve some conflicts and I switched to order
> of patch3 and patch4, to avoid checkpatch warnings. Just so you know.

Thanks, patch 4 dropped from devicetree/next.
-- 
Florian

Re: [PATCH v3 0/2] Add support for Broadcom RNG200

[Herbert Xu]

On Wed, Mar 04, 2015 at 12:42:12PM -0800, Scott Branden wrote:
> This series of patchsets contains the Broadcom Random Number Generator
> driver and device tree binding documentation.
> 
> Changes from v2:
>  added usleep_range instead of cpu_relax
>  add init and cleanup functions following new hwrng model

All applied.  Thanks!
-- 
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt

[PATCH] mmc: sdhci: fix card presence logic in sdhci_request function

[Scott Branden]

The sdhci_request function should consider a non-removable device
always present.
Call the correct logic already available in sdhci_do_get_cd function.

This fixes some logic paths where MMC requests are being made to
non-removable devices that do not have the card detect pin connected
on the hardware as it is non-removable.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
---
 drivers/mmc/host/sdhci.c | 20 +++-----------------
 1 file changed, 3 insertions(+), 17 deletions(-)

diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 0ad412a..bafc7ac 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -56,6 +56,7 @@ static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
 					struct mmc_data *data,
 					struct sdhci_host_next *next);
+static int sdhci_do_get_cd(struct sdhci_host *host);
 
 #ifdef CONFIG_PM
 static int sdhci_runtime_pm_get(struct sdhci_host *host);
@@ -1356,7 +1357,8 @@ static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 
 	sdhci_runtime_pm_get(host);
 
-	present = mmc_gpio_get_cd(host->mmc);
+	/* Firstly check card presence */
+	present = sdhci_do_get_cd(host);
 
 	spin_lock_irqsave(&host->lock, flags);
 
@@ -1379,22 +1381,6 @@ static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 
 	host->mrq = mrq;
 
-	/*
-	 * Firstly check card presence from cd-gpio.  The return could
-	 * be one of the following possibilities:
-	 *     negative: cd-gpio is not available
-	 *     zero: cd-gpio is used, and card is removed
-	 *     one: cd-gpio is used, and card is present
-	 */
-	if (present < 0) {
-		/* If polling, assume that the card is always present. */
-		if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
-			present = 1;
-		else
-			present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
-					SDHCI_CARD_PRESENT;
-	}
-
 	if (!present || host->flags & SDHCI_DEVICE_DEAD) {
 		host->mrq->cmd->error = -ENOMEDIUM;
 		tasklet_schedule(&host->finish_tasklet);
-- 
2.3.0

Re: [PATCH] mmc: sdhci: fix card presence logic in sdhci_request function

[Ulf Hansson]

On 10 March 2015 at 19:35, Scott Branden <sbranden@broadcom.com> wrote:
> The sdhci_request function should consider a non-removable device
> always present.
> Call the correct logic already available in sdhci_do_get_cd function.
>
> This fixes some logic paths where MMC requests are being made to
> non-removable devices that do not have the card detect pin connected
> on the hardware as it is non-removable.
>
> Signed-off-by: Scott Branden <sbranden@broadcom.com>

Thanks, applied!

Kind regards
Uffe

> ---
>  drivers/mmc/host/sdhci.c | 20 +++-----------------
>  1 file changed, 3 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index 0ad412a..bafc7ac 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -56,6 +56,7 @@ static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
>  static int sdhci_pre_dma_transfer(struct sdhci_host *host,
>                                         struct mmc_data *data,
>                                         struct sdhci_host_next *next);
> +static int sdhci_do_get_cd(struct sdhci_host *host);
>
>  #ifdef CONFIG_PM
>  static int sdhci_runtime_pm_get(struct sdhci_host *host);
> @@ -1356,7 +1357,8 @@ static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
>
>         sdhci_runtime_pm_get(host);
>
> -       present = mmc_gpio_get_cd(host->mmc);
> +       /* Firstly check card presence */
> +       present = sdhci_do_get_cd(host);
>
>         spin_lock_irqsave(&host->lock, flags);
>
> @@ -1379,22 +1381,6 @@ static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
>
>         host->mrq = mrq;
>
> -       /*
> -        * Firstly check card presence from cd-gpio.  The return could
> -        * be one of the following possibilities:
> -        *     negative: cd-gpio is not available
> -        *     zero: cd-gpio is used, and card is removed
> -        *     one: cd-gpio is used, and card is present
> -        */
> -       if (present < 0) {
> -               /* If polling, assume that the card is always present. */
> -               if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
> -                       present = 1;
> -               else
> -                       present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
> -                                       SDHCI_CARD_PRESENT;
> -       }
> -
>         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
>                 host->mrq->cmd->error = -ENOMEDIUM;
>                 tasklet_schedule(&host->finish_tasklet);
> --
> 2.3.0
>

[PATCH] wireless: rt2x00: add new rt2800usb device DWA 130

[Scott Branden]

Add the USB Id to link the D-Link DWA 130 USB Wifi adapter
to the rt2830 driver.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Pieter Truter <ptruter@broadcom.com>
---
 drivers/net/wireless/rt2x00/rt2800usb.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/wireless/rt2x00/rt2800usb.c b/drivers/net/wireless/rt2x00/rt2800usb.c
index 8444313..8694ddd 100644
--- a/drivers/net/wireless/rt2x00/rt2800usb.c
+++ b/drivers/net/wireless/rt2x00/rt2800usb.c
@@ -1040,6 +1040,7 @@ static struct usb_device_id rt2800usb_device_table[] = {
 	{ USB_DEVICE(0x07d1, 0x3c17) },
 	{ USB_DEVICE(0x2001, 0x3317) },
 	{ USB_DEVICE(0x2001, 0x3c1b) },
+	{ USB_DEVICE(0x2001, 0x3c25) },
 	/* Draytek */
 	{ USB_DEVICE(0x07fa, 0x7712) },
 	/* DVICO */
-- 
2.3.3

[PATCH] ARM: amba: Increase number of IRQs

[Scott Branden]

The current AMBA bus only allows up to 9 IRQs per device. This is
incorrect, as in peripherals like PL330 can have up to 32 IRQs.
Increase AMBA_NR_IRQS from 9 to 32.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Ray Jui <rjui@broadcom.com>
---
 include/linux/amba/bus.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h
index 50fc668..475e090 100644
--- a/include/linux/amba/bus.h
+++ b/include/linux/amba/bus.h
@@ -21,7 +21,7 @@
 #include <linux/resource.h>
 #include <linux/regulator/consumer.h>
 
-#define AMBA_NR_IRQS	9
+#define AMBA_NR_IRQS	32
 #define AMBA_CID	0xb105f00d
 #define CORESIGHT_CID	0xb105900d
 
-- 
2.3.3

Re: [PATCH] ARM: amba: Increase number of IRQs

[Russell King - ARM Linux]

On Mon, Mar 16, 2015 at 11:19:22AM -0700, Scott Branden wrote:
> The current AMBA bus only allows up to 9 IRQs per device. This is
> incorrect, as in peripherals like PL330 can have up to 32 IRQs.
> Increase AMBA_NR_IRQS from 9 to 32.

I'm quite certain that 32 will also be "incorrect" at some point in the
future, so let's not use such language.  Let's make this more neutral
and say "This does not suit peripherals like the PL330 which can have
up to 32 IRQs."

Thanks.

-- 
FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up
according to speedtest.net.

[PATCH v2 1/1] ARM: amba: Increase number of IRQs

[Scott Branden]

The current AMBA bus only allows up to 9 IRQs per device.
This does not suit peripherals like PL330 which can have up to 32 IRQs.
Increase AMBA_NR_IRQS from 9 to 32.

Signed-off-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Ray Jui <rjui@broadcom.com>
---
 include/linux/amba/bus.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/linux/amba/bus.h b/include/linux/amba/bus.h
index 50fc668..475e090 100644
--- a/include/linux/amba/bus.h
+++ b/include/linux/amba/bus.h
@@ -21,7 +21,7 @@
 #include <linux/resource.h>
 #include <linux/regulator/consumer.h>
 
-#define AMBA_NR_IRQS	9
+#define AMBA_NR_IRQS	32
 #define AMBA_CID	0xb105f00d
 #define CORESIGHT_CID	0xb105900d
 
-- 
2.3.3

Re: [PATCH] ARM: amba: Increase number of IRQs

[Scott Branden]

Hi Russell,

On 15-03-16 02:08 PM, Russell King - ARM Linux wrote:
> On Mon, Mar 16, 2015 at 11:19:22AM -0700, Scott Branden wrote:
>> The current AMBA bus only allows up to 9 IRQs per device. This is
>> incorrect, as in peripherals like PL330 can have up to 32 IRQs.
>> Increase AMBA_NR_IRQS from 9 to 32.
>
> I'm quite certain that 32 will also be "incorrect" at some point in the
> future, so let's not use such language.  Let's make this more neutral
> and say "This does not suit peripherals like the PL330 which can have
> up to 32 IRQs."

OK, I sent out a new patch with update commit message.

Thanks,
  Scott

>
> Thanks.
>

Re: rt2x00: add new rt2800usb device DWA 130

[Kalle Valo]

> Add the USB Id to link the D-Link DWA 130 USB Wifi adapter
> to the rt2830 driver.
> 
> Signed-off-by: Scott Branden <sbranden@broadcom.com>
> Signed-off-by: Pieter Truter <ptruter@broadcom.com>

Thanks, applied to wireless-drivers-next.git.

Kalle Valo

Re: [PATCHv2 4/5] mmc: shdci-bcm2835: add verify for 32-bit back-to-back workaround

[Stefan Wahren]

Hi Scott,

Am 07.11.2014 um 19:31 schrieb Scott Branden:
> On 14-11-05 09:01 PM, Stephen Warren wrote:
>> On 11/05/2014 12:00 AM, Scott Branden wrote:
>>> On 14-11-04 08:59 PM, Stephen Warren wrote:
>>>> On 10/30/2014 12:36 AM, Scott Branden wrote:
>>>>> Add a verify option to driver to print out an error message if a
>>>>> potential back to back write could cause a clock domain issue.
>>>>
>>>>> index f8c450a..11af27f 100644
>>>>
>>>>> +#ifdef CONFIG_MMC_SDHCI_BCM2835_VERIFY_WORKAROUND
>>>>> +    struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>>>>> +    struct bcm2835_sdhci_host *bcm2835_host = pltfm_host->priv;
>>>>> +
>>>>> +    if (bcm2835_host->previous_reg == reg) {
>>>>> +        if ((reg != SDHCI_HOST_CONTROL)
>>>>> +            && (reg != SDHCI_CLOCK_CONTROL)) {
>>>>
>>>> The comment in patch 3 says the problem doesn't apply to the data
>>>> register. Why does this check for these two registers rather than data?
>>> This Verify workaround patch still a work in progress.  I'm still
>>> getting more info from the silicon designers on the back-to-back
>>> register writes that are affect.  The spew of 0x20 or 0x28 or 0x2c
>>> register writes are all ok locations that don't need to be worked
>>> around.  This patch needs to be corrected with the proper register rules
>>> still.
> Thanks for testing.  Yes, I have work to do on the verify patch above
> still.

do you still have plans to submit a V3 of this patch series?

I attached an improved version of this patch which avoids a possible
endless loop caused by the dev_err call. So only the first occurence
of a specific register will be logged.

Regards
Stefan


-------------------8<-------------------------------------------

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 1526b8a..7b0990f 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -306,6 +306,15 @@ config MMC_SDHCI_BCM2835

 	  If unsure, say N.

+config MMC_SDHCI_BCM2835_VERIFY_WORKAROUND
+	bool "Verify BCM2835 workaround does not do back to back writes"
+	depends on MMC_SDHCI_BCM2835
+	default y
+	help
+	  This enables code that verifies the bcm2835 workaround.
+	  The verification code checks that back to back writes to the same
+	  register do not occur.
+
 config MMC_SDHCI_F_SDH30
 	tristate "SDHCI support for Fujitsu Semiconductor F_SDH30"
 	depends on MMC_SDHCI_PLTFM
diff --git a/drivers/mmc/host/sdhci-bcm2835.c
b/drivers/mmc/host/sdhci-bcm2835.c
index 01ce193d..c1c70df 100644
--- a/drivers/mmc/host/sdhci-bcm2835.c
+++ b/drivers/mmc/host/sdhci-bcm2835.c
@@ -20,15 +20,27 @@
  */

 #include <linux/delay.h>
+#include <linux/hashtable.h>
 #include <linux/module.h>
 #include <linux/mmc/host.h>
+#include <linux/slab.h>
 #include "sdhci-pltfm.h"

 struct bcm2835_sdhci_host {
 	u32 shadow_cmd;
 	u32 shadow_blk;
+	int previous_reg;
 };

+struct reg_hash {
+	struct hlist_node node;
+	int reg;
+};
+
+#define BCM2835_REG_HT_BITS 4
+
+static DEFINE_HASHTABLE(bcm2835_used_regs, BCM2835_REG_HT_BITS);
+
 #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)

 static inline u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg)
@@ -56,8 +68,37 @@ static u8 bcm2835_sdhci_readb(struct sdhci_host
*host, int reg)
 }

 static inline void bcm2835_sdhci_writel(struct sdhci_host *host,
+					u32 val, int reg)
+{
+	writel(val, host->ioaddr + reg);
+}
+
+static inline void bcm2835_sdhci_writel_verify(struct sdhci_host *host,
 						u32 val, int reg)
 {
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct bcm2835_sdhci_host *bcm2835_host = pltfm_host->priv;
+	struct reg_hash *rh;
+	struct hlist_head *head;
+
+	head = &bcm2835_used_regs[hash_min(reg, BCM2835_REG_HT_BITS)];
+
+	if (bcm2835_host->previous_reg == reg) {
+		if ((reg != SDHCI_HOST_CONTROL) &&
+		    (reg != SDHCI_CLOCK_CONTROL) &&
+		    (hlist_empty(head))) {
+			rh = kzalloc(sizeof(*rh), GFP_KERNEL);
+			if (WARN_ON(!rh))
+				return;
+
+			rh->reg = reg;
+			hash_add(bcm2835_used_regs, &rh->node, rh->reg);
+			dev_err(mmc_dev(host->mmc), "back-to-back write to 0x%x\n",
+				reg);
+		}
+	}
+	bcm2835_host->previous_reg = reg;
+
 	writel(val, host->ioaddr + reg);
 }

@@ -131,7 +172,11 @@ static const struct sdhci_ops bcm2835_sdhci_ops = {
 	.read_l = bcm2835_sdhci_readl,
 	.read_w = bcm2835_sdhci_readw,
 	.read_b = bcm2835_sdhci_readb,
+#ifdef CONFIG_MMC_SDHCI_BCM2835_VERIFY_WORKAROUND
+	.write_l = bcm2835_sdhci_writel_verify,
+#else
 	.write_l = bcm2835_sdhci_writel,
+#endif
 	.write_w = bcm2835_sdhci_writew,
 	.write_b = bcm2835_sdhci_writeb,
 	.set_clock = sdhci_set_clock,

Re: [PATCHv2 4/5] mmc: shdci-bcm2835: add verify for 32-bit back-to-back workaround

[Scott Branden]

Hi Stefan,

On 15-12-22 07:55 AM, Stefan Wahren wrote:
> Hi Scott,
>
> Am 07.11.2014 um 19:31 schrieb Scott Branden:
>> On 14-11-05 09:01 PM, Stephen Warren wrote:
>>> On 11/05/2014 12:00 AM, Scott Branden wrote:
>>>> On 14-11-04 08:59 PM, Stephen Warren wrote:
>>>>> On 10/30/2014 12:36 AM, Scott Branden wrote:
>>>>>> Add a verify option to driver to print out an error message if a
>>>>>> potential back to back write could cause a clock domain issue.
>>>>>
>>>>>> index f8c450a..11af27f 100644
>>>>>
>>>>>> +#ifdef CONFIG_MMC_SDHCI_BCM2835_VERIFY_WORKAROUND
>>>>>> +    struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>>>>>> +    struct bcm2835_sdhci_host *bcm2835_host = pltfm_host->priv;
>>>>>> +
>>>>>> +    if (bcm2835_host->previous_reg == reg) {
>>>>>> +        if ((reg != SDHCI_HOST_CONTROL)
>>>>>> +            && (reg != SDHCI_CLOCK_CONTROL)) {
>>>>>
>>>>> The comment in patch 3 says the problem doesn't apply to the data
>>>>> register. Why does this check for these two registers rather than data?
>>>> This Verify workaround patch still a work in progress.  I'm still
>>>> getting more info from the silicon designers on the back-to-back
>>>> register writes that are affect.  The spew of 0x20 or 0x28 or 0x2c
>>>> register writes are all ok locations that don't need to be worked
>>>> around.  This patch needs to be corrected with the proper register rules
>>>> still.
>> Thanks for testing.  Yes, I have work to do on the verify patch above
>> still.
>
> do you still have plans to submit a V3 of this patch series?
No, I do not have plans to submit a V3 of this patch series.

I submitted this patch as RPI has a similar controller to the SoCs I am 
familiar with as well as needing similar work arounds   You can take 
over the patchset.  Or, try and get the sdhci-iproc.c driver going on 
RPI.  The sdhci-iproc is the production driver we use on a variety of 
SoCs and support and test this driver.
>
> I attached an improved version of this patch which avoids a possible
> endless loop caused by the dev_err call. So only the first occurence
> of a specific register will be logged.
OK, but is this really necessary?  If veryify workaround ever prints 
anything then the driver workarounds aren't doing what it is supposed to 
anyway?
>
> Regards
> Stefan
>
>
> -------------------8<-------------------------------------------
>
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 1526b8a..7b0990f 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -306,6 +306,15 @@ config MMC_SDHCI_BCM2835
>
>   	  If unsure, say N.
>
> +config MMC_SDHCI_BCM2835_VERIFY_WORKAROUND
> +	bool "Verify BCM2835 workaround does not do back to back writes"
> +	depends on MMC_SDHCI_BCM2835
> +	default y
> +	help
> +	  This enables code that verifies the bcm2835 workaround.
> +	  The verification code checks that back to back writes to the same
> +	  register do not occur.
> +
>   config MMC_SDHCI_F_SDH30
>   	tristate "SDHCI support for Fujitsu Semiconductor F_SDH30"
>   	depends on MMC_SDHCI_PLTFM
> diff --git a/drivers/mmc/host/sdhci-bcm2835.c
> b/drivers/mmc/host/sdhci-bcm2835.c
> index 01ce193d..c1c70df 100644
> --- a/drivers/mmc/host/sdhci-bcm2835.c
> +++ b/drivers/mmc/host/sdhci-bcm2835.c
> @@ -20,15 +20,27 @@
>    */
>
>   #include <linux/delay.h>
> +#include <linux/hashtable.h>
>   #include <linux/module.h>
>   #include <linux/mmc/host.h>
> +#include <linux/slab.h>
>   #include "sdhci-pltfm.h"
>
>   struct bcm2835_sdhci_host {
>   	u32 shadow_cmd;
>   	u32 shadow_blk;
> +	int previous_reg;
>   };
>
> +struct reg_hash {
> +	struct hlist_node node;
> +	int reg;
> +};
> +
> +#define BCM2835_REG_HT_BITS 4
> +
> +static DEFINE_HASHTABLE(bcm2835_used_regs, BCM2835_REG_HT_BITS);
> +
>   #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
>
>   static inline u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg)
> @@ -56,8 +68,37 @@ static u8 bcm2835_sdhci_readb(struct sdhci_host
> *host, int reg)
>   }
>
>   static inline void bcm2835_sdhci_writel(struct sdhci_host *host,
> +					u32 val, int reg)
> +{
> +	writel(val, host->ioaddr + reg);
> +}
> +
> +static inline void bcm2835_sdhci_writel_verify(struct sdhci_host *host,
>   						u32 val, int reg)
>   {
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct bcm2835_sdhci_host *bcm2835_host = pltfm_host->priv;
> +	struct reg_hash *rh;
> +	struct hlist_head *head;
> +
> +	head = &bcm2835_used_regs[hash_min(reg, BCM2835_REG_HT_BITS)];
> +
> +	if (bcm2835_host->previous_reg == reg) {
> +		if ((reg != SDHCI_HOST_CONTROL) &&
> +		    (reg != SDHCI_CLOCK_CONTROL) &&
> +		    (hlist_empty(head))) {
> +			rh = kzalloc(sizeof(*rh), GFP_KERNEL);
> +			if (WARN_ON(!rh))
> +				return;
> +
> +			rh->reg = reg;
> +			hash_add(bcm2835_used_regs, &rh->node, rh->reg);
> +			dev_err(mmc_dev(host->mmc), "back-to-back write to 0x%x\n",
> +				reg);
> +		}
> +	}
> +	bcm2835_host->previous_reg = reg;
> +
>   	writel(val, host->ioaddr + reg);
>   }
>
> @@ -131,7 +172,11 @@ static const struct sdhci_ops bcm2835_sdhci_ops = {
>   	.read_l = bcm2835_sdhci_readl,
>   	.read_w = bcm2835_sdhci_readw,
>   	.read_b = bcm2835_sdhci_readb,
> +#ifdef CONFIG_MMC_SDHCI_BCM2835_VERIFY_WORKAROUND
> +	.write_l = bcm2835_sdhci_writel_verify,
> +#else
>   	.write_l = bcm2835_sdhci_writel,
> +#endif
>   	.write_w = bcm2835_sdhci_writew,
>   	.write_b = bcm2835_sdhci_writeb,
>   	.set_clock = sdhci_set_clock,
>
>
>
>

Re: [PATCHv2 4/5] mmc: shdci-bcm2835: add verify for 32-bit back-to-back workaround

[Stefan Wahren]

Hi Scott,

Am 22.12.2015 um 20:23 schrieb Scott Branden:
> Hi Stefan,
>
> On 15-12-22 07:55 AM, Stefan Wahren wrote:
>> Hi Scott,
>>
>> Am 07.11.2014 um 19:31 schrieb Scott Branden:
>>> On 14-11-05 09:01 PM, Stephen Warren wrote:
>>>> On 11/05/2014 12:00 AM, Scott Branden wrote:
>>>>> On 14-11-04 08:59 PM, Stephen Warren wrote:
>>>>>> On 10/30/2014 12:36 AM, Scott Branden wrote:
>>>>>>> Add a verify option to driver to print out an error message if a
>>>>>>> potential back to back write could cause a clock domain issue.
>>>>>>
>>>>>>> index f8c450a..11af27f 100644
>>>>>>
>>>>>>> +#ifdef CONFIG_MMC_SDHCI_BCM2835_VERIFY_WORKAROUND
>>>>>>> +    struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>>>>>>> +    struct bcm2835_sdhci_host *bcm2835_host = pltfm_host->priv;
>>>>>>> +
>>>>>>> +    if (bcm2835_host->previous_reg == reg) {
>>>>>>> +        if ((reg != SDHCI_HOST_CONTROL)
>>>>>>> +            && (reg != SDHCI_CLOCK_CONTROL)) {
>>>>>>
>>>>>> The comment in patch 3 says the problem doesn't apply to the data
>>>>>> register. Why does this check for these two registers rather than
>>>>>> data?
>>>>> This Verify workaround patch still a work in progress.  I'm still
>>>>> getting more info from the silicon designers on the back-to-back
>>>>> register writes that are affect.  The spew of 0x20 or 0x28 or 0x2c
>>>>> register writes are all ok locations that don't need to be worked
>>>>> around.  This patch needs to be corrected with the proper register
>>>>> rules
>>>>> still.
>>> Thanks for testing.  Yes, I have work to do on the verify patch above
>>> still.
>>
>> do you still have plans to submit a V3 of this patch series?
> No, I do not have plans to submit a V3 of this patch series.
>
> I submitted this patch as RPI has a similar controller to the SoCs I am
> familiar with as well as needing similar work arounds   You can take
> over the patchset.  Or, try and get the sdhci-iproc.c driver going on
> RPI.  The sdhci-iproc is the production driver we use on a variety of
> SoCs and support and test this driver.

after applying the patch series both drivers are very similiar so i 
prefer the latter. I will give it a try. Thanks for the hint about 
sdhci-iproc.

Regards
Stefan