From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932163AbbCYQ2u (ORCPT ); Wed, 25 Mar 2015 12:28:50 -0400 Received: from mail.kmu-office.ch ([178.209.48.109]:34774 "EHLO mail.kmu-office.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752634AbbCYQ2l (ORCPT ); Wed, 25 Mar 2015 12:28:41 -0400 From: Stefan Agner To: dwmw2@infradead.org, computersforpeace@gmail.com Cc: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, shawn.guo@linaro.org, kernel@pengutronix.de, boris.brezillon@free-electrons.com, marb@ixxat.de, aaron@tastycactus.com, bpringlemeir@nbsps.com, linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Stefan Agner Subject: [PATCH v4 6/6] ARM: dts: vf-colibri: enable NAND flash controller Date: Wed, 25 Mar 2015 17:28:29 +0100 Message-Id: <1427300909-20825-7-git-send-email-stefan@agner.ch> X-Mailer: git-send-email 2.3.3 In-Reply-To: <1427300909-20825-1-git-send-email-stefan@agner.ch> References: <1427300909-20825-1-git-send-email-stefan@agner.ch> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable NAND access by adding pinmux and NAND flash controller node to device tree. The NAND chips currently used on the Colibri VF61 requires 8-bit ECC per 512 byte page, hence specify 32-bit ECC strength per 2k page size. Signed-off-by: Stefan Agner --- arch/arm/boot/dts/vf-colibri.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi index 5c2b732..76139d7 100644 --- a/arch/arm/boot/dts/vf-colibri.dtsi +++ b/arch/arm/boot/dts/vf-colibri.dtsi @@ -46,6 +46,19 @@ pinctrl-0 = <&pinctrl_i2c0>; }; +&nfc { + assigned-clocks = <&clks VF610_CLK_NFC>; + assigned-clock-rates = <33000000>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + nand-ecc-strength = <32>; + nand-ecc-step-size = <2048>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nfc_1>; + status = "okay"; +}; + &pwm0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm0>; @@ -141,6 +154,25 @@ >; }; + pinctrl_nfc_1: nfcgrp_1 { + fsl,pins = < + VF610_PAD_PTD23__NF_IO7 0x28df + VF610_PAD_PTD22__NF_IO6 0x28df + VF610_PAD_PTD21__NF_IO5 0x28df + VF610_PAD_PTD20__NF_IO4 0x28df + VF610_PAD_PTD19__NF_IO3 0x28df + VF610_PAD_PTD18__NF_IO2 0x28df + VF610_PAD_PTD17__NF_IO1 0x28df + VF610_PAD_PTD16__NF_IO0 0x28df + VF610_PAD_PTB24__NF_WE_B 0x28c2 + VF610_PAD_PTB25__NF_CE0_B 0x28c2 + VF610_PAD_PTB27__NF_RE_B 0x28c2 + VF610_PAD_PTC26__NF_RB_B 0x283d + VF610_PAD_PTC27__NF_ALE 0x28c2 + VF610_PAD_PTC28__NF_CLE 0x28c2 + >; + }; + pinctrl_pwm0: pwm0grp { fsl,pins = < VF610_PAD_PTB0__FTM0_CH0 0x1182 -- 2.3.3