From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753397AbbCaHfg (ORCPT ); Tue, 31 Mar 2015 03:35:36 -0400 Received: from mail-wi0-f179.google.com ([209.85.212.179]:32959 "EHLO mail-wi0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753166AbbCaHfY (ORCPT ); Tue, 31 Mar 2015 03:35:24 -0400 From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, maxime.coquelin@st.com, patrice.chotard@st.com, tj@kernel.org, srinivas.kandagatla@gmail.com Cc: peter.griffin@linaro.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-ide@vger.kernel.org Subject: [PATCH 2/3] ARM: DT: STi: STiH407: Add sata DT nodes. Date: Tue, 31 Mar 2015 08:35:08 +0100 Message-Id: <1427787309-1601-3-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1427787309-1601-1-git-send-email-peter.griffin@linaro.org> References: <1427787309-1601-1-git-send-email-peter.griffin@linaro.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Now that the miphy28lp is upstream, we can add the sata dt nodes for stih407 family silicon. This has been tested on b2120 board J4 (sata0 channel). These nodes are disabled by default as a special mini pci-e to sata daughter board is required which isn't shipped with the board. Signed-off-by: Peter Griffin Acked-by: Lee Jones Acked-by: Maxime Coquelin --- arch/arm/boot/dts/stih407-family.dtsi | 44 +++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index a57c06e..d526921 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -338,6 +338,50 @@ }; }; + sata0: sata@9b20000 { + compatible = "st,ahci"; + reg = <0x9b20000 0x1000>; + + interrupts = ; + interrupt-names = "hostc"; + + phys = <&phy_port0 PHY_TYPE_SATA>; + phy-names = "ahci_phy"; + + resets = <&powerdown STIH407_SATA0_POWERDOWN>, + <&softreset STIH407_SATA0_SOFTRESET>, + <&softreset STIH407_SATA0_PWR_SOFTRESET>; + reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; + + clock-names = "ahci_clk"; + clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; + + status = "disabled"; + }; + + sata1: sata@9b28000 { + compatible = "st,ahci"; + reg = <0x9b28000 0x1000>; + + interrupts = ; + interrupt-names = "hostc"; + + phys = <&phy_port1 PHY_TYPE_SATA>; + phy-names = "ahci_phy"; + + resets = <&powerdown STIH407_SATA1_POWERDOWN>, + <&softreset STIH407_SATA1_SOFTRESET>, + <&softreset STIH407_SATA1_PWR_SOFTRESET>; + reset-names = "pwr-dwn", + "sw-rst", + "pwr-rst"; + + clock-names = "ahci_clk"; + clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; + + status = "disabled"; + }; + st_dwc3: dwc3@8f94000 { compatible = "st,stih407-dwc3"; reg = <0x08f94000 0x1000>, <0x110 0x4>; -- 1.9.1